JPH0766301A - Semiconductor element, memory cell using it, and semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a high-speed memory cell without increasing the cell area. CONSTITUTION:An NMOS 61 and PMOS 62 formed in parallel in a laminated structure constitute a transfer gate 60. Another NMOS 71 and PMOS 72 similarly formed in parallel in a laminated structure constitute another transfer gate 70. Depending upon the potential across word lines WL and WL/, the transfer gates 60 and 70 electrically connect the input-output nodes N1 and N2 of a data holding section to bit lines BL and BL/, respectively. The on resistances of the gates 60 and 70 are the resultant resistances of their laminated NMOSs and PMOSs and are stabilized regardless of the potentials at the nodes N1 and N2. Therefore, the potentials across the bit lines BL and BL/ symmetrically changes with respect to the half level of the power supply voltage at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element having a laminated structure used for a semiconductor memory or the like, a memory cell using the semiconductor element, and a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a memory cell of a conventional static random access memory (hereinafter referred to as SRAM). The memory cell in FIG. 2 is an SRAM having six MOS transistors 1 to 6,
Inverters 10, 2 forming a holding unit for holding data
0 and the bit line B is opened / closed based on the potential of the word line WL.
It is composed of NMOSs 31 and 32 which are transfer gates for connecting L and BL / to the memory cell. The inverter 10 has a PMOS 11 and an NMOS 12 whose drains are connected to each other at a node N1.
The source of the NMOS 12 has a power supply potential VCC and a ground potential G.
It is connected to each ND. Node N1 is NMOS
32 is connected to the bit line BL / via 32
The gate electrodes of the NMOS 12 and the NMOS 12 are connected to the bit line BL via the NMOS 31. Similarly, the inverter 20 has a PMO whose drains are connected to each other at the node N2.
S21 and NMOS22, each PMOS21, NMO
The source of S22 is connected to the power supply potential VCC and the ground potential GND, respectively. The node N2 is connected to the bit line BL via the NMOS 31, and is connected to the PMOS 21 and NM.
The gate electrode of the OS 22 is connected to the bit line BL / via the NMOS 32.

The bit line BL transmits write or read data to / from the memory cell, and the bit line BL /
Transmits write or read data whose phase is opposite to that of the bit line BL. The node N1, which is the output point of the inverter 10, is connected to the gate electrodes of the PMOS 21 and the NMOS 22 of the inverter 20. The node N2, which is the output point of the inverter 20, is
It is connected to the gates of the MOS 11 and the NMOS 12. Therefore, the inverters 10 and 20 function as flip-flops that hold data, hold the data from the bit lines BL and BL / via the NMOSs 31 and 32, and store the data in the bit lines BL and BL / via the NMOSs 31 and 32. It is a configuration to output. When reading data from the memory cell of FIG. 2, the word line WL is selectively activated by an address decoder (not shown) and becomes "H" level. As a result, the NMOSs 31 and 32 are turned on, and the data held in the flip-flop is read to the bit lines BL and BL /. At this time, NMO
Since S31 and S32 are semiconductor switches, the NMOS3
The ON resistances of 1 and 32 are the word line WL and the bit line B, respectively.
It is affected by the voltages of L and BL /.

FIG. 3 is a diagram showing changes in the potential of the bit line in FIG. For example, when the potential level of the node N1 is "L", the on-resistance of the NMOS 31 is small, so that the bit line B
The level of L becomes "L" in a comparative short time. However, the level of the node N2 is "H", and the ON resistance of the NMOS 32 becomes large. Therefore, the level of the bit line BL /
It takes a long time to rise to "H" as shown in FIG. In addition, the level of the bit line BL / is equal to the power source potential VCC by the threshold value Vth even if the potential is stable after a long time.
It only rises to a lower potential. That is, it takes time to increase the voltage between the bit lines BL and BL /. In order to prevent an increase in access time caused by the delay in the voltage rise, each bit line BL, BL is read before reading data.
The level of / is precharged to the “H” level and the potentials of the bit lines BL and BL / drop from “H” to “L” in a sense circuit (not shown) at the set reference voltage Vs. It is detecting. Further, in the conventional semiconductor device, a semiconductor device having an improved transfer gate structure is also used. FIG. 4 is a circuit diagram showing the improved transfer gate. In the transfer gate shown in FIG. 4, the NMOS 33 and the PMO are provided between the terminals D _n and D _{n + 1.}
S34 is connected in parallel, and each NMOS33, PMOS3
Complementary signals Φ and Φ / are input to the gate electrode of No. 4, respectively. By inputting complementary signals Φ and Φ /, each NM
The OS 33 and the PMOS 34 are turned on. In this process, the resistance of this transfer gate is
It becomes a combined resistance of the PMOS 34. FIG. 5 is a diagram showing the combined resistance of FIG. 4, in which the combined resistance of the improved transfer gate with respect to the voltage between the terminals D _n and D _{n + 1} is indicated by a broken line. This combined resistance is stable with respect to the voltage between the terminals D _n and D _{n + 1} . Therefore, the semiconductor device using the transfer gate shown in FIG. 4 can maintain high-speed operation.

[0005]

However, the memory cell of the conventional semiconductor memory device has the following problems. In the semiconductor memory device using the memory cell of FIG. 2, when the level of each bit line BL, BL / is detected,
The potentials of the nodes N1 and N2 are determined by the power supply voltage VCC. When the power supply voltage VCC changes, each bit line BL,
It becomes impossible to stably detect the level change of BL /, and the reading of data becomes unstable. Power supply voltage VCC
In order to maintain the stability of the level change detection, it is necessary to greatly change the level of each bit line BL, BL /. That is, it is necessary to lower the level of the reference voltage Vs in FIG. 3 for detection. This essentially slows down access time and this method was not suitable for high speed operation. Further, the semiconductor memory device using the transfer gate shown in FIG. 4 has a large area of each memory cell and is not suitable for the semiconductor memory device of the high density memory cell. The present invention has the problems that the prior art has, as a result of the change in the on-resistance in the transfer gate, making data reading unstable, and reducing the change in the on-resistance in the transfer gate increases the area of the memory cell. The present invention provides a semiconductor memory device that solves the above problems.

[0006]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a first diffusion layer and a second diffusion layer which are formed on a substrate or an underlayer at predetermined intervals, and the first and second diffusion layers. A first gate insulating film formed on the second diffusion layer via a first gate insulating film;
The semiconductor element is provided with the first MOS transistor of the first conductivity type having the gate electrode. Further, the first,
Of the third and fourth diffusion layers respectively connected to the second diffusion layer and formed above them and above the first gate electrode via an interlayer insulating film, and the first gate electrode. In the vicinity of the upper third and fourth diffusion layers, the third and fourth diffusion layers are electrically insulated from the second gate insulating film, and the first gate electrode is insulated from the interlayer insulating film. Second conductivity type second MOS having a second gate electrode formed by
A semiconductor element is provided with a transistor. According to a second invention, the first and second diffusion layers of the semiconductor device of the first invention are formed on the single crystal substrate, and the third and fourth diffusion layers are single crystal or polycrystalline. Is formed on the semiconductor film. A third aspect of the invention is based on a potential of a complementary first and second word line, which is connected in parallel between a data holding unit having an output node and holding data, and a bit line and the input / output node. In a memory cell including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, each of which is gate-controlled, the transfer gate is the first invention or the first invention. It is composed of the semiconductor element of the second invention. Fourth
In the invention, the data holding unit of the third invention is composed of a flip-flop or a MOS capacitor.

In the fifth invention, the first conductivity type first MO is provided.
A first inverter formed of a series circuit of an S transistor and a second MOS transistor of the second conductivity type, a third MOS transistor of the first conductivity type, and a fourth MOS transistor of the second conductivity type.
A second inverter composed of a series circuit of MOS transistors, and a data holding section connected in a crossed manner between the first and second input / output nodes, and a first of the complementary first and second bit lines. A fifth MOS transistor of the first conductivity type, which is connected in parallel between two bit lines and the first input / output node and is gate-controlled based on the potentials of the complementary first and second word lines, respectively. And a sixth MOS of the second conductivity type
A first transfer gate having a transistor is connected in parallel between the first bit line and the second input / output node, and each gate is controlled based on the potentials of the first and second word lines. Seventh MOS of the first conductivity type
In the memory cell including the transistor and the second transfer gate having the eighth MOS transistor of the second conductivity type, the following measures are taken. That is,
In the present invention, the first MOS transistor, the third M
OS transistor, fifth MOS transistor and seventh
Are formed on substantially the same plane with a predetermined distance therebetween, and the second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are substantially separated with the predetermined distance. Formed on the same plane, and the first and second
MOS transistor, the third and fourth MOS transistors, the fifth and sixth MOS transistors, and the seventh
And an eighth MOS transistor are laminated so as to face each other vertically with an insulating film interposed therebetween to form a memory cell having a laminated structure. According to a sixth aspect of the invention, the semiconductor memory device includes the third, fourth or fifth memory cell and a sense amplifier for detecting and amplifying the potential difference between the first and second bit lines.

[0008]

According to the first and second aspects of the invention, since the semiconductor element is constructed as described above, the complementary signals are transmitted to the first and second signals.
The first and second MOS transistors are simultaneously turned on by inputting to the gate electrode of the. The resistance of the semiconductor element in the on state becomes a combined resistance of the first and second MOS transistors in the on state. According to the third, fourth, and fifth inventions, the first and second transfer gates are rendered conductive based on the potentials of the first and second word lines,
The second bit line is connected to the first and second input / output nodes to input / output data to / from the holding unit. At this time, the ON resistance of the first and second transfer gates is a combined resistance of the first and second MOS transistors. According to a fourth aspect of the invention, the above operation is carried out in a memory cell that is an SRAM or a dynamic RAM. In the fifth invention, the above operation is performed in a memory cell having a small area in which all MOS transistors in the memory cell have a laminated structure. In the sixth invention, read data is output from the memory cells of the third, fourth and fifth inventions via the first and second bit lines, and the first and second
The potential difference between the bit lines is detected and amplified by the sense amplifier. Therefore, the above problem can be solved.

[0009]

1 is a circuit diagram showing a memory cell according to an embodiment of the present invention. This memory cell is an SRAM having eight MOS transistors, and is a memory based on the potentials of the first and second word lines WL and WL / complementary to the inverters 40 and 50 that form the data holding unit. It is provided with first and second transfer gates 60 and 70 for controlling conduction between the cell and complementary first and second bit lines BL and BL /. The first inverter 40 has a second conductivity type MO whose drains are connected to each other at the first input / output node N1.
PMOS 41 of S transistor and first conductivity type MOS
It has a transistor NMOS 42, and each NMOS 41,
The source of the PMOS 42 is the power supply potential VCC and the ground G.
It is connected to each ND. The node N1 is connected to the bit line BL / via the transfer gate 60, and N
Gate electrodes of the MOS 41 and the PMOS 42 are connected to the bit line BL via the transfer gate 70. Similarly, in the second inverter 50, the drains are connected to the NMOS 51 and P connected to each other at the second input / output node N2.
The MOS 52 is provided, and the sources of the NMOS 51 and the PMOS 52 are connected to the power supply potential VCC and the ground GND, respectively. The node N2 is connected to the bit line BL via the transfer gate 70, and the NMOS 51 and PM are connected.
The gate electrode of the OS 52 is connected to the bit line BL / via the transfer gate 60.

The bit line BL transmits write or read data to / from the memory cell, and the bit line BL /
Transmits write or read data whose phase is opposite to that of the bit line BL. The node N1, which is the output point of the inverter 40, is connected to the gate electrodes of the NMOS 51 and the PMOS 52 of the inverter 50. The node N2, which is the output point of the inverter 50, is
The gates of the MOS 41 and the PMOS 42 are connected to the electrodes. Therefore, the inverters 40, 50 function as flip-flops for holding data, hold the data from the bit lines BL, BL / via the transfer gates 60, 70, and bit lines BL, BL via the transfer gates 60, 70. The data is output to /. The first transfer gate 60 has a bit line BL /
Between the NMOS 61 and the PM connected in parallel between the node N1 and the node N1
The gate electrode of the NMOS 61 is connected to the word line WL, and the gate electrode of the PMOS 62 is connected to the word line WL /. The second transfer gate has a structure similar to that of the transfer gate 60, and has an NMOS 71 and a PMOS 72 connected in parallel between the bit line BL and the node N2. The gate electrode of the NMOS 71 is connected to the word line WL and the gate electrode of the PMOS 72 is connected. But the word line W
Each is connected to L /.

FIG. 6 shows the transfer gate 60 in FIG.
It is a figure explaining the structure of. Single crystal silicon (hereinafter,
The first conductivity type NMO is formed on the surface of the substrate 80A (referred to as Si).
The first diffusion layer 81a, which is the drain region of S61, and N
A second diffusion layer 81b which is a source region of the MOS 61 is formed. A first gate electrode 81c, which is the gate electrode of the NMOS 61, is formed between the diffusion layers 81a and 81b with a gate oxide film 82, which is an insulating film, interposed therebetween. An interlayer insulating film 83 is formed above the first gate electrode 81c.
A second gate electrode 84c, which is the gate electrode of the second conductivity type PMOS 62, is formed so as to face the gate electrode 81c, and the semiconductor film is formed on the gate electrode 84c with the gate oxide film 82 interposed therebetween. 80B is laminated.
The semiconductor film 80B is a single crystal or polycrystal semiconductor film, and the semiconductor film 80B has a second conductivity type PMOS 62.
The third diffusion layer 84a which is the drain region of the
A fourth diffusion layer 84b, which is the source region of 62, is formed. The first diffusion layer 81a and the third diffusion layer 84a are formed facing each other and are connected by the conductive material 85. The second diffusion layer 81b and the fourth diffusion layer 84b are formed so as to face each other and are connected by the conductive material 86. That is,
The PMOS 62 is a so-called SOI (Silicon on insulator)
r) composed of structure. Electrically connected NMOS
61, the drain of the PMOS 62 is, for example, the bit line BL
The source is connected to the node N1 by being connected to /.
Therefore, the NMOS 61 and the PMOS 62 are connected in parallel between the bit line BL / and the node N1. The first
The area around the second diffusion layers 81a and 81b is separated from other circuits by the element isolation film 87, and the protective film 88 is formed on the semiconductor film 80B. The transfer gate 70 also has the same configuration as the transfer gate 60,
The NMOS 71 is formed on the substrate 80A, and the PMOS 7 is formed.
2 is formed on the semiconductor film 85B.

Further, the other MOS transistors shown in FIG. 1 also have a laminated structure to form an integrated semiconductor memory cell. FIG. 7 is a diagram illustrating the layout of the memory cell of FIG. The NMOS 41 and 51 in FIG. 1 are NMOS
Similar to 61 and 71, it is formed on the Si substrate 80A, and the PMO
S42 and S52 are formed in the semiconductor film 80B similarly to the PMOSs 62 and 72. 7A shows the arrangement of the NMOSs 41, 51, 61, 71 formed on the Si substrate 80A, and FIG. 7B shows the arrangement of the PMOSs 42, 52, 62, 72 formed on the semiconductor film 80B. It is shown. 7B is stacked on FIG. 7A, and the NMOS
Placed on the PMOS 42 above the 41, and likewise the NMOS
PMOS 52 on 41 and PMOS 6 on NMOS 61
2. The PMOS 72 is arranged on the NMOS 71. In FIG. 7, a region surrounded by diagonal lines indicates an active region, and the active region indicates a drain or source region of each MOS transistor. The word lines WL, WL / shown in FIG. 7 are provided between the Si substrate 80A and the semiconductor film 80B, and the bit lines BL, BL /
Are installed above the semiconductor film 80B.

Next, the operation of the memory cell of FIG. 1 will be described. When writing or reading data to or from the memory cell of FIG. 1, complementary word lines WL and WL / are selectively activated by an address decoder (not shown).
The word line WL is set to "H" level and the word line W
L / becomes "L". As a result, the NMOS 61 and the PMOS 62 in the transfer gate 60 and the NMOS 71 and the PMOS 72 in the transfer gate 70 are turned on. Each transfer gate 60, 70
Is turned on, each node N1, N2
However, it is electrically connected to the bit lines BL and BL /, respectively, and data is written or read. NMOS 61, PMO
Since S62 is connected in parallel, when the transfer gate 60 is conductive, the on-resistance of the transfer gate 60 is smaller than that of the conventional memory cell of FIG. The on resistance of the transfer gate 60 is stable regardless of the voltage between the bit line BL / and the node N1.
In the transfer gate 70, the NMOS 71, PM
Since the OS 72 is connected in parallel, the on-resistance of the transfer gate 70 is smaller than that of the conventional memory cell of FIG. 2 and is stable regardless of the voltage between the bit line BL and the node N2.

FIG. 8 is a diagram showing changes in the potential of the bit line in FIG. For example, when reading data, the node N
Since the on-resistances of the transfer gates 60 and 70 are little changed regardless of whether the potential level of 1 and the node N2 is "H" or "L", the bit lines BL and BL /
Potential changes symmetrically with respect to 1/2 Vcc. Further, since the on resistances of the transfer gates 60 and 70 are small, the potentials of the bit lines BL and BL / change rapidly and rise to the power supply potential Vcc. Each bit line BL, BL
Since the potential of / changes symmetrically with respect to the potential of 1/2 Vcc, it is possible to employ a sense amplifier that differentially amplifies the potential difference between the bit lines BL and BL /. FIG. 9 shows the sense amplifier and the memory cell of FIG. The data read from the memory cell 90 is the bit lines BL and B.
It is transmitted to the sense amplifier 91 via L /. The sense amplifier 91 differentially amplifies the potential difference between the bit lines BL and BL /, and determines the read data at time t1 when the set potential difference is reached. This time t1 is faster than the level detecting method as in the conventional semiconductor memory device. That is, high speed access is possible. As mentioned above,
In this embodiment, NMOS 61, PMOS 62, NMO
The memory cell is provided with transfer gates 60 and 70 in which S71 and PMOS 72 are laminated respectively. As a result, it is possible to realize a memory cell capable of high-speed access and stable data reading without increasing the area of the memory cell. In addition, the MOS that constitutes the memory cell
By making all transistors have a laminated structure, 8
A memory cell can be formed with the area of four MOS transistors for each MOS transistor. Therefore, it is possible to realize a high-density semiconductor memory device.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) Although the memory cell is composed of the SRAM, the same effect can be exhibited also as a dynamic RAM having a MOS capacitor. (2) Although the MOS transistor formed on the Si substrate 80A is the NMOS and the MOS transistor formed on the semiconductor film 80B is the PMOS, they may be formed in reverse. Rather, it is better to have the NMOS on the upper layer side. In this case, S
The carrier mobility of the PMOS on the i-substrate 80A side (about 200
cm ² / V · s) is close to the carrier mobility (about 150 cm ² / V · s) of the NMOS on the semiconductor film 80B side,
The on resistance is about the same. Even considering that the on-resistance is about the same, it is possible to stack the elements while keeping the dimensions of the element substantially the same as that of this embodiment. (3) The semiconductor film 80B is formed by a large crystallized film or a single crystal film formed by laser / electron beam annealing, a large grain polycrystalline Si film formed by a solid phase growth method, or a lateral solid phase growth method. It may be a single crystal Si film or the like. (4) The MOS transistor is formed on the Si substrate 80A and the MOS transistor is formed on the semiconductor film 80B. However, the MOS transistors may be stacked in pairs so that the two MOS transistors are layered. Different semiconductor films may be formed.

[0016]

As described in detail above, according to the first and second inventions, the first conductive type first MOS transistor and the second conductive type second MOS transistor connected in parallel are provided. Since it has a laminated structure, the resistance change of the semiconductor element can be reduced without increasing the formation area. In the second invention, since the first MOS transistor is formed on the substrate, it is possible to manufacture a semiconductor element having the above effect with a small number of manufacturing steps. According to a third invention, the semiconductor element of the first or second invention is the memory cell of the first invention.
And used as a second transfer gate. Therefore, the on resistance of the first and second transfer gates is stable regardless of the potential of the input / output node, and high-speed access and highly reliable read operation in the memory cell is realized without increasing the area of the memory cell. it can. Fourth
According to the invention, even if the data holding unit in the memory cell of the third invention is an SRAM or a dynamic RAM, the same effect as the third invention can be obtained. According to the fifth invention,
Since all the MOS transistors in the memory cell have a laminated structure, the formation area of the memory cell can be reduced. Further, since the semiconductor element of the first or second invention is used as the first and second transfer gates of the memory cell, similar to the effect of the third invention, high speed access in the memory cell and A highly reliable read operation can be realized. According to the sixth aspect of the invention, since the sense amplifier detects and amplifies the potential difference between the first and second bit lines, it can be used as a high speed access semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory cell according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a memory cell of a conventional SRAM.

FIG. 3 is a diagram showing a potential change of a bit line in FIG.

FIG. 4 is a circuit diagram showing an improved transfer gate.

5 is a diagram showing the combined resistance of FIG.

FIG. 6 is a diagram illustrating a structure of a transfer gate in FIG.

FIG. 7 is a diagram illustrating the layout of the MOS transistor in FIG.

FIG. 8 is a diagram showing a potential change of the bit line in FIG.

9 is a configuration block diagram showing a sense amplifier and the memory cell of FIG. 1. FIG.

[Explanation of symbols]

40, 50 First and second inverters 41, 51, 61, 71 NMOS 42, 52, 62, 72 PMOS 60, 70 First and second transfer gates 81a, 81b First and second diffusion layers 81c First gate electrode 82 Gate oxide film 83 Interlayer insulating film 84a, 84b Third and fourth diffusion layers 84c Second gate electrode BL, BL / First and second bit lines WL, WL / First and second Word lines N1, N2 first and second input / output nodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/092 29/786 9056-4M H01L 29/78 311 C

Claims (6)

[Claims] 1. A first and a second diffusion layers formed on a substrate or an underlayer with a predetermined space therebetween, and a first gate insulating film formed between the first and second diffusion layers. A first MOS transistor of a first conductivity type having a first gate electrode, and an interlayer insulating film connected to the first and second diffusion layers, respectively, and above the first gate electrode. And the third and fourth diffusion layers formed on the first gate electrode, and the third and fourth diffusion layers and the second gate near the third and fourth diffusion layers on the first gate electrode. A second MOS transistor of a second conductivity type, which is electrically insulated by an insulating film and has a second gate electrode formed by being insulated by the first gate electrode and the interlayer insulating film. A semiconductor element characterized by. 2. The first and second diffusion layers are formed on the single crystal substrate, and the third and fourth diffusion layers are formed on a single crystal or polycrystal semiconductor film. The semiconductor element according to claim 1. 3. A data holding unit having an input / output node for holding data, and a parallel connection between a bit line and the input / output node, based on complementary potentials of the first and second word lines. First M of the first conductivity type, each of which is gated
A memory cell comprising an OS transistor and a transfer gate having a second MOS transistor of the second conductivity type, wherein the transfer gate is composed of the semiconductor element according to claim 1 or 2. . 4. The memory cell according to claim 3, wherein the data holding unit is composed of a flip-flop or a MOS capacitor. 5. A first inverter composed of a series circuit of a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type and a third MO of the first conductivity type.
A second inverter formed by a series circuit of an S-transistor and a fourth MOS transistor of the second conductivity type is connected between the first and second input / output nodes by a data holding section, and a complementary first and second data holding section. It is connected in parallel between the second bit line of the first and second bit lines and the first input / output node, and is gate-controlled based on the complementary potentials of the first and second word lines, respectively. A first transfer gate having a fifth MOS transistor of a first conductivity type and a sixth MOS transistor of a second conductivity type, and a first transfer gate connected in parallel between the first bit line and the second input / output node. A seventh MO of the first conductivity type which is connected and is gate-controlled based on the potentials of the first and second word lines, respectively.
A memory cell comprising an S transistor and a second transfer gate having an eighth MOS transistor of a second conductivity type, wherein the first MOS transistor, the third MOS transistor, the fifth MOS transistor and the seventh MOS transistor are provided. Are formed on substantially the same plane with a predetermined distance therebetween, and the second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are substantially separated with the predetermined distance. Formed on the same plane, the first and second MOS transistors, the third and fourth MOS transistors, and the fifth
And a sixth MOS transistor, and the seventh and eighth MO transistors
A memory cell having a stacked structure in which S transistors are vertically opposed to each other with an insulating film interposed therebetween. 6. A semiconductor memory device comprising the memory cell according to claim 3, 4 or 5, and a sense amplifier for detecting and amplifying a potential difference between the first and second bit lines.