JPH0765041A - Signal delay evaluating method - Google Patents

Abstract

PURPOSE:To provide a static signal delay evaluating method for the design data on a digital logic circuit and especially for the design data mixed with a design level. CONSTITUTION:A signal delay evaluating routine selection program 600 is prepared for selection of a delay calculating method in response to the design level of the design data on each evaluating object section defined in the evaluating object section data 507 prior to a signal delay evaluating routine group 1700 of a signal delay evaluation system 500. Then the delay calculating method to be applied is changed for each evaluating object section. Thus it is possible to evaluate the signal delay with no consciousness of the design level and against an optional evaluating object section of the design data mixed, with a design level by selecting a delay calculating method corresponding to the design level for each evaluating object section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static signal delay evaluation method in a design process of a digital circuit, and more specifically, to a design target at a desired design level when partial design data of a desired design level are mixed. The present invention relates to a signal delay evaluation method for an evaluation target section.

[0002]

2. Description of the Related Art As a conventional static signal delay evaluation method for design data of a digital logic circuit, for example, as shown in Nikkei Electronics September 28, 1992, pages 211 to 217, Methods for single level data at each design level after completion of logic design, after layout design, and after wiring design are known and put to practical use.

Further, for example, IEEE / International Confer
ence on Computer Design: VLSI in Computers 1992 Proceedings 468-471 `` Delay Prediction for Technology-
A signal intended for design data at a single register transfer level, that is, RT level, in which a latch in a digital circuit is clearly defined and the function of a combinational circuit is expressed by a functional expression such as a Boolean expression, such as “Independent Logic Equations”. Lazy evaluation methods are also known.

[0004]

In a top-down design method in which each level of method, function, logic, and layout is refined in order, signal delay, area, etc. for a plurality of design candidates at any level of design. A planning technology that evaluates the above items and selects multiple candidates is indispensable for shortening the design period and improving the design quality.

When a plurality of design candidates are selected in this planning, a part of the design circuit is subjected to prior design and detailing in order to improve the evaluation accuracy, and as a result, design levels of the target design data are mixed.

FIG. 1 shows an example of design data in which design levels are mixed. The logic circuit 100 to be designed is composed of four partial circuits. The design of the partial circuit 110 is completed up to the register transfer level (RT level) in which the latch in the design circuit described above is clearly shown and the combinational circuit is described by a functional expression such as a Boolean expression. Partial circuit 12
0 is gate level design data for which detailed logic design has been completed. The partial circuit 130 is design data at a level where the wiring design is completed, and is a so-called hard macro partial circuit. In the partial circuit 140, the design of the entire partial circuit is completed up to the RT level, but a part thereof is further expanded to the gate logic. This is because the delay circuit or the like of the partial circuit 140 is critical.
This is the situation that occurs when the preceding design is performed. As described above, the design data of the design target circuit 100 is a collection of partial circuit data having three different design levels, and the design levels are mixed.

However, since the conventional signal delay evaluation method is intended for the design data of a single level, it is impossible to handle the design data in which the above design levels are mixed. For example, when evaluating the signal delay for the design circuit 100 shown in FIG. 1, it is not possible to apply the conventional signal delay evaluation method because the design level of the target design data is not uniform, and the signal delay It is necessary to manually specify a program that realizes the delay evaluation method according to the design level for each evaluation target section. For example, a gate level signal delay evaluation method is applied to the delay evaluation target section in the partial circuit 120, and a wiring design end level signal delay evaluation method is applied to the delay evaluation target section in the partial circuit 130. It is necessary to apply.

Further, even when the evaluation target section extends over the design data of a plurality of design levels, the conventional signal delay evaluation method cannot perform accurate evaluation. This will be described with reference to the examples shown in FIGS. 2, 3, and 4.

FIG. 2 shows an example of an evaluation target section extending between design data of the gate level partial circuit 201 and the RT level partial circuit 202. Here, the evaluation target section is a path whose start point is the latch 210 and whose end point is the latch 211. In the case of this example, the gate level within the target section,
There are two different design data of RT level, and the conventional signal delay evaluation method for gate level or RT level cannot evaluate with sufficient accuracy. For example, when the gate-level signal delay evaluation method is applied, the latch 210 changes the gate G
Gate section G2 can be evaluated for the second section
Since there is no specific element information in the section from to latch 211, it cannot be evaluated. On the contrary, when the RT-level signal delay calculation method is applied, the calculation is possible, but it is not possible to evaluate the section belonging to the sub-circuit 201 whose design is detailed, with sufficient accuracy, and therefore the method should be applied to planning. I can't.

Also in the example of FIG. 3, the gate level partial circuit 30 is provided.
In this example, the design data of the partial circuit 302 of 1 and the RT level are mixed. The evaluation target section has the latch 310 existing in the partial circuit 301 as a start point and the latch 311 as an end point.
Further, there is a fan-out signal 313 whose end point is the latch 312 in the partial circuit 302 from the gate G1 in the middle of the evaluation target section. In the case of this example, since the input side of the fanout signal 313 is the functional expression 314 such as a Boolean expression, the input gate of the fanout signal 313 on the side of the partial circuit 302 cannot be specified. Therefore, the design information such as the input terminal capacitance of the input gate of the fan-out signal necessary when applying the gate-level delay evaluation method to the evaluation target section having the latch 310 as the starting point and the latch 311 as the ending point cannot be obtained. , The gate level delay evaluation method cannot be applied to this section.

FIG. 4 shows an example in which, of the partial circuits 401 whose design is completed up to the RT level, the partial circuit 402 is further predesigned up to the gate level. The evaluation target section is a path in the predesigned partial circuit 402 up to the gate level where the latch 410 is the starting point and the latch 411 is the ending point. In the case of this example, it is possible to calculate the signal delay value for this evaluation target section by the conventional gate level delay evaluation method. However, here, for example, it is assumed that there is a logical path whose starting point is the latch 412 which is not expanded to the gate level and whose ending point is the latch 411 which is the end point of the evaluation target section. This route is still realized by functional expressions such as Boolean expressions. When this path is designed up to the gate level, signal merging always occurs in the path of the delay evaluation target section from the latch 410 to the latch 411. On the other hand, the delay evaluation value calculated previously does not consider this influence, and the evaluation accuracy is poor. The same applies when there is a logical path that has the latch 410 that is the start point of the evaluation target section as the start point and the latch 413 that has not been expanded to the gate level as the end point. That is, when this logical path is designed up to the gate level, a fanout signal is generated from the path of the delay evaluation target section. In the case of this example as well, the above-mentioned delay evaluation value does not take this effect into consideration, so the accuracy is poor and it cannot be used for planning.

As described above, in the conventional signal delay evaluation method for single-level design data, it is impossible to perform delay evaluation for design data having mixed design levels.

Therefore, an object of the present invention is to target design data in which arbitrary design levels coexist, and to enable signal delay evaluation of an arbitrary evaluation target section without the designer being aware of the design levels. To provide an evaluation method.

[0014]

According to the present invention, prior to a concrete delay calculation, a process for selecting a delay calculation method according to the design level of each given evaluation target section is provided. Next, the signal delay evaluation value is calculated for each evaluation target section by the delay calculation method selected by this selection processing. This enables signal delay evaluation for design data having different design levels for each evaluation target section.

Further, for design data in which design levels are mixed in the evaluation target section, processing for supplementing design information necessary for delay calculation from the input design data, or delay for a certain level By providing a process of correcting the evaluation value calculated by the calculation method in consideration of design information of another design level, the delay evaluation can be performed.

[0016]

In the signal delay evaluation method of the present invention, prior to specific delay calculation, design data in which design levels are mixed is analyzed, and a delay calculation method corresponding to the design level is selected for each evaluation target section, In addition, when the design information necessary for the selected delay calculation method cannot be obtained from the design data, the signal delay evaluation can be performed on the design data in which arbitrary design levels are mixed by supplementing appropriately.

[0017]

FIG. 5 shows the configuration of a signal delay evaluation system which is an embodiment of the present invention.

The signal delay evaluation system 500 includes a CPU 5
01, output device 502, keyboard 503, main memory 50
4 and an auxiliary storage device 505.

The auxiliary storage device 505 stores the design data 50.
6, evaluation target section data 507, technology data 5
08 and evaluation result data 509 are stored. Of these, design data 506 and evaluation target section data 50
7 and technology data 508 are data groups that are input to this system, and evaluation result data 509 are output data.

The design data 506 is data that stores the designed result of the design target, and is the design target circuit 1 of FIG.
As shown in the example of 00, when the design data of the partial circuits having different design levels are mixed, or when the partial circuit 1 of FIG.
In some cases, like 40, design data of a plurality of levels may be mixed in the same partial circuit. It should be noted that the design data 506 has a single design level within a partial circuit that constitutes the design target circuit, as in the example of the design target circuit 100 in FIG. 1. Further, partial design data for each partial circuit is, for example, EDIF (Electorical) which is a standard of IEEE.
(Design Interchange Format), an identifier representing the design level of the partial circuit is added to the beginning of the design data of each partial circuit. Alternatively, like the hardware description language VHDL (VHSIC Hardware Description Language), the design data of each partial circuit is expressed as a grammar element corresponding to the design level. That is, it is possible to easily know the design level of each partial circuit by checking the identifier of each design data or the grammar of the description. In the following description, it is assumed that the design data of each partial circuit is prefixed with an identifier indicating the design level of the partial circuit. The target design levels are the RT level, the gate level, and the layout and wiring design end level.

The evaluation target section data 507 is data defining a route for evaluating static signal delay. For each evaluation target section, its identification number, the starting and ending latch names, and the route between them are defined in a table format. The evaluation target route is expressed as follows at each level. First, at the RT level,
It is represented by a list having a latch and an interface signal as elements and having a logically related pair among them as a start point and an end point. Here, being logically related means
For example, in a functional expression such as one Boolean expression, it means an input and an output. This means that there will always be paths between them when the design is refined. The gate level and the wiring design end level are represented as generally known connection data of logic gates. In addition,
As for the wiring design end level, the path can be expressed as connection data of a logic gate like EDIF.

The technology data 508 is various constant data depending on the technology for realizing the design target circuit necessary for the signal delay calculation, such as the wiring width, the line resistance value, the input terminal capacitance of each gate, and the ON resistance value. . For example, it holds the value of each constant in the formulas shown on pages 211 to 217 of the September 28, 1992 issue of Nikkei Electronics.

The main memory 504 has a signal delay evaluation routine selection program 600 and a signal delay evaluation routine group 17.
00 is stored.

Signal delay evaluation routine selection program 60
0 is an evaluation that implements a signal delay evaluation method that is applied with design data 506 and evaluation target section data 507 as input and calculates a signal delay evaluation value for each evaluation target section defined in the evaluation target section data 507. The routine
It is selected from the signal delay evaluation routine group 1700.

The signal delay evaluation routine group 1700 is a group of routines for executing the signal delay evaluation method corresponding to the combination of the design levels when the design level of the evaluation target section and the design level of the evaluation target section are mixed. Has been realized. The evaluation routine selected by the signal delay evaluation routine selection program 600 is executed for each evaluation target section to calculate the signal delay evaluation value. Here, each routine calculates a signal delay evaluation value by different signal delay calculation formulas that use different parameters depending on the design level.

In the signal delay evaluation system 500, the signal delay evaluation routine selection program 600 is first executed by an instruction from the keyboard 503. The signal delay evaluation routine selection program 600 first sets the design data 50.
6, and the evaluation target section data 507 are stored in the auxiliary storage device 50.
Read from 5. Next, for each evaluation target section defined in the evaluation target section data 507, a signal delay evaluation routine to be applied is selected according to its design level. Finally, the evaluation routine in the previously selected signal delay evaluation routine group 1700 is executed for each evaluation target section. Each executed evaluation routine outputs the signal delay evaluation value to the evaluation result data 509 in the auxiliary storage device 505 or the display device 503.

As described above, the signal delay evaluation system 50
In 0, by providing the signal delay evaluation routine selection program 600 that selects the signal delay evaluation routine to be applied to each evaluation target section, special information is added even when the design data 506 includes design levels. Without, it enables signal delay evaluation.

FIG. 6 shows a processing flow of the signal delay evaluation routine selection program 600. In FIG. 6, a solid square indicates processing, a solid arrow indicates processing flow, a dotted square indicates data, and a dotted arrow indicates data flow.

Signal delay evaluation routine selection program 60
0 is a design level management data creation process 11 that inputs design data 506 and evaluation target section data 507 and outputs design level management data 700 expressing the design level of each evaluation target section defined in the evaluation target section data 507.
00, design data 506, evaluation target section data 50
7 and design level management data 700 as input, and delay evaluation routine selection data defining a delay evaluation routine to be executed to calculate a signal delay evaluation value for each evaluation target section defined in the evaluation target section data 507. The delay evaluation routine selection judgment processing 1200 that outputs 601 and the evaluation target section data 507 and the delay evaluation routine selection data 601 are input, and the signal delay evaluation is performed for each evaluation target section defined in the evaluation target section data 507. The routine group 1700 includes an evaluation routine call process 1300 that executes an evaluation routine realized in advance.

Signal delay evaluation routine selection program 60
In 0, first, design level management data creation processing 1100
Is the design level management data 70 expressing the design level of each evaluation target section defined in the evaluation target section data 507.
Create 0. Next, delay evaluation routine selection judgment processing 1
The reference numeral 200 refers to the design level information in the design level management data, selects a delay evaluation routine to be applied to the signal delay evaluation of each evaluation target section, and outputs it as delay evaluation routine selection data 601. Finally, the evaluation routine call process 1300 executes the evaluation routine defined in the delay calculation method selection data 601 for each evaluation target section.

Design level management data creation process 1100
Is the design data 506 and the evaluation target section data 50.
7, the design level between the start point and the end point of each evaluation target section defined in the evaluation target section data 507 is checked and registered in the design level management data 700. At the same time, a path search is performed from the start point in the signal flow direction and from the end point in the direction opposite to the signal flow, and all latches and interface signals connected to them in a logical path are searched, and further between them. The design level of the route is checked and registered in the design level management data 700. In this way, this processing checks the design level of the route of the evaluation target section and the route logically related to them, and actually applies the delay to the evaluation target section by the delay evaluation routine selection determination process 1200. The purpose is to create design level management data 700 that is referenced to select an evaluation routine.

Delay evaluation routine selection judgment processing 1200
Is the input of the evaluation target section data 507 and the design level management data 700, and for each evaluation target section defined in the evaluation target section data 507, the design of the corresponding section stored in the design level management data 700. With reference to the level information, a delay evaluation routine corresponding to the design level is selected and output as delay evaluation routine selection data 601. For example, when the design data of the corresponding section is the gate level design data, the delay evaluation routine for the gate level design data is performed, and when the target section in which the gate level and the RT level are mixed is used, the gate level is set. Select each delay evaluation routine that can handle mixed / RT level data. The created delay evaluation routine selection data 601 is a list showing the correspondence between the identification number of the evaluation target section and the identifier of the delay evaluation routine to be applied.

The evaluation routine call processing 1300 receives the evaluation target section data 507 and the delay evaluation routine selection data 601 as input, and delay evaluation routine selection data for each evaluation target section defined in the evaluation target section data 507. The evaluation routine applied to each evaluation target section defined in 601 is called to execute the signal delay evaluation.

FIG. 7 shows an example of the design level management data 700. As shown in the figure, the design level management data 70
0 can be represented by, for example, a well-known directed graph. Nodes indicated by circles in FIG. 7 represent facilities, and specifically represent latches and interface signals. The edge indicated by the arrow in FIG. 7 indicates that a logical path exists between the nodes connected to it. The direction of the arrow represents the direction of signal flow. Each edge has an attribute that represents the design level of the route represented by the edge, as indicated by the square in the figure. Although this attribute can be arbitrarily set according to the design process, for example, three levels of attribute B: RT level, attribute G: gate level, and attribute R: wiring design end level are set. This attribute is determined in accordance with the most detailed design level among the design levels of the design data in which the paths corresponding to the respective edges exist. It should be noted that these data are generally realized by a data structure that uses a structure and pointers that are used in a calculation process that handles a directed graph.

FIGS. 8, 9 and 10 show examples of design level management data.

Design level management data 800 shown in FIG.
Corresponds to the evaluation target section 200 shown in FIG.
The start point latch 210, the end point latch 211, and the interface signal 213 in FIG. 2 are the node 8 in FIG.
01, node 802, and node 803. Also,
Since a logical path via the interface signal 213 exists between the latch 210 and the latch 211,
An edge 804 and an edge 805 exist between the node 801 and the node 803, and between the node 803 and the node 802, respectively. Further, the directions of these edges are the directions from the node 801 to the node 803 and the node 803 to the node 802, respectively, in accordance with the flow of signals.
An edge 804 connecting the nodes 801 and 803 has an attribute G: a gate level attribute because the partial circuit 201 is gate level design data. The edge 805 connecting the nodes 803 and 802 has the attribute B: RT level attribute because the partial circuit 202 is the RT level design data.

FIG. 9 shows an evaluation target section 300 shown in FIG.
10 shows design level management data 900 for The latch 310, the latch 311, the latch 312, and the interface signal 313 in FIG. 3 are respectively the nodes 90 in FIG.
1, node 902, node 903, and node 904. The design level management data 90 corresponding to the logical path between the latch and the interface signal in FIG.
0 includes edge 905, edge 906, and edge 9
There is 07. The edge 905 connecting the nodes 901 and 902 and the edge 906 connecting the nodes 901 and 904 have the attribute G: the attribute of the gate level because the partial circuit 301 is the design data of the gate level. An edge 907 connecting the node 904 and the node 903 has an attribute B: RT level attribute because the partial circuit 302 is RT level design data.

FIG. 10 shows the evaluation target section 40 shown in FIG.
The design level management data 1000 for 0 is shown. Figure 4
The latch 410, the latch 411, the latch 412, and the latch 413 in the inside correspond to the node 1001, the node 1002, the node 1003, and the node 1004 in FIG. 10, respectively. Since a logical path which is an evaluation target section exists between the latch 410 and the latch 411, an edge 1005 exists between the node 1001 and the node 1002. The path from the latch 410 to the latch 411 is the partial circuit 40.
Since it is included in 2, it has both gate level and RT level design data. Therefore, the edge 1005 is an attribute G: which is the most detailed level among these design levels.
Has gate level attributes. Latch 412 and Latch 41
During 1 there is no gate level design data,
There is a logical path between them due to the functional expression in the RT-level design data, and therefore there is an edge connecting the nodes 1003 and 1004 in the design level management graph 1000. The attribute is attribute B: RT level. Similarly, since there is a logical path in the functional expression in the RT-level design data between the latch 410 and the latch 413, the nodes 1001 and 100
Edges also exist between 4. The attribute is also attribute B: RT level.

As described above, the design level management data 70
With 0, the design level of the design information corresponding to the route existing in the design data 506 can be simply expressed, and the delay evaluation routine selection determination process 1200 later
It can be easily referred to when selecting the lazy evaluation routine to be applied.

FIG. 11 shows a processing flow of the design level management data creation processing 1100. The design level management data creation process 1100 receives the design data 506 and the evaluation target section data 507 as input, and evaluates the evaluation target section data 50.
The node generation processing 1101 of the start point latch, the forward search processing 1102 from the start point latch, and the backward search processing 1103 from the end point latch are executed for all the evaluation target sections defined in FIG.

In the node generation processing 1101 of the starting point latch, the node corresponding to the starting point latch of the evaluation target section is registered. Note that new registration is not performed for latches that have already been registered.

Next, the forward search processing 110 from the starting point latch
Execute 2. The forward search process 1110 is a recursive process as shown in the figure, and takes a circuit element START as a starting point in the argument. Here, the circuit element is a constituent element of a logic circuit defined in the design data, such as a latch, an interface signal, or a logic element in gate level design data.

The forward search processing 1110 carries out the following processing for logical paths in the flow direction of all signals connected to the circuit element START given as an argument.

First, in process 1112, the circuit element NEXT connected to the logical path is searched. Here, the specific processing of this search processing differs depending on the design level of the design data. For example, for the design data at the gate level and the wiring design end level, the conventionally known search processing on the netlist is performed. However, for the design data at the RT level, the functional expression such as a Boolean expression is used. Search processing of. That is, when searching the circuit element B connected to a certain circuit element A, the input variable of each functional expression is searched, and the functional expression in which the circuit element A appears is found. When found, the output signal of the functional expression is the circuit element B connected to the circuit element A.

Next, in process 1113, the circuit element ST
Store the design level between ART and circuit element NEXT. This is uniquely determined by checking the identifier representing the design level of the partial circuit to which the design data referred to in the search process in process 1112 belongs.

Next, in process 1114, branch determination of the process flow according to the type of circuit element NEXT is performed. First, the circuit element
If NEXT is a latch, processing 1115 and processing 1
Execute 116. In process 1115, a node corresponding to the circuit element NEXT is generated, and an edge is generated between the nodes of the starting point latch that started the search process. In addition, when a node occurs, no new generation is performed for already registered nodes. The edge direction is from the node of the starting point latch to the node of the circuit element NEXT. Next, in process 1116, the edge attribute is determined. An attribute corresponding to the design level information stored in the previous processing 1113 is assigned to this. The allocation of this attribute is uniquely determined. This completes the search process for the logical path from the starting point latch.

Even when the circuit element NEXT is an interface signal, processing 1115 and processing 1116 are similarly executed to generate nodes and edges and determine edge attributes. In this case, the search process is not ended, and the process 1117 executes the forward search process starting from this circuit element NEXT.

If the circuit element NEXT is neither a latch nor an interface signal, the node and the edge are not generated, and the process 1118 continues the forward search process.

Subsequently, the design level management data creation processing 1100 performs backward search processing 1103 in the direction opposite to the signal flow from the end point latch of each evaluation target section. The backward search processing 1103 only changes the search direction of the forward search processing 1110 to the direction opposite to the signal flow, and description thereof will be omitted here.

The design level management data creation process 11 is performed by executing the above process for all evaluation target sections.
00 creates design level management data 700 expressing the design level of the evaluation target section.

FIG. 12 shows a processing flow of the delay evaluation routine selection judgment processing 1200. The delay evaluation routine selection determination process 1200 receives the evaluation target section data 507 and the design level management data 700 as input, selects a delay evaluation routine to be applied to each evaluation section, and sets the selected data as delay evaluation routine selection data 601. Output.

Delay evaluation routine selection judgment processing 1200
Performs the following processing for all evaluation target sections.

First, in process 1201, the attribute of the edge on the design level management data 700 corresponding to the evaluation target section is checked. Next, in process 1202, branch control of the process flow is performed based on the edge attribute. First, when the attributes of the edges forming the evaluation target section are not the same, the process proceeds to processing 1203. In this case, it means that the evaluation target section spans design data of a plurality of design levels. Here, in the process 1203, a delay evaluation routine that handles a mixed section corresponding to a combination of levels is selected, registered in the delay evaluation routine selection data 601, and the process for this evaluation target section is terminated. Also,
If the attributes of the edges are the same, the process proceeds to processing 1204.

In the process 1204, the attributes of all the edges connected to the nodes corresponding to the latches and interface signals existing on the evaluation target section are examined. Here, when the target edge is connected to the node of the interface signal, the target is the edge further ahead of the node.

Next, in step 1205, a judgment process is performed based on these edge attributes. Here, if all of these edge attributes match the attributes of the edge of the evaluation target section examined in the processing 1201, the processing proceeds to processing 1206. In this case, a delay evaluation routine for design data of a single design level of the attribute is selected for this evaluation target section and registered in the delay evaluation routine selection data 601. On the other hand, if the attributes of these edges are different from the attributes of the edges of the evaluation target section, it can be determined that the design levels are mixed in the evaluation target section.
At 207, a delay evaluation routine that handles a mixed section corresponding to the combination of the levels is selected, and the information is registered in the delay evaluation routine selection data 601.

Through the above processing, the delay evaluation routine selection judgment processing 1200 selects the delay evaluation method to be applied to each evaluation target section. Here, the delay evaluation routine selection determination process 1200 is characterized in that not only the section to be evaluated, but also the design level of the route other than the other sections to be evaluated, which are connected to this, are selected and the delay evaluation routine is selected. Is. As a result, for example, in the case of not only the example of FIG. 2 but also the examples shown in FIG. 3 and FIG.

FIG. 13 shows an evaluation routine call process 1300.
The processing flow of is shown.

The evaluation routine call process 1300 receives the evaluation target section data 507 and the delay evaluation routine selection data 601 as input, and sets the delay evaluation routine selection data 601 for each evaluation target section defined in the evaluation target section data 507. Defined signal delay evaluation routine group 170
During 0, call a pre-implemented evaluation routine.

In the evaluation routine call process 1300, first in process 1301, the evaluation target section data 507 is read into the main memory. Next, by the process 1302, the following process is executed for each evaluation target section defined in the evaluation target section data 507.

First, in process 1303, the delay evaluation routine selection data 601 for the relevant section is read. This data is the identification symbol of the evaluation routine applied to perform the delay evaluation of the relevant section.

Next, in process 1304, the signal delay evaluation routine group 1700 is caused to execute a corresponding routine among the signal evaluation routines previously realized according to the delay evaluation routine selection data.

Hereinafter, referring to FIGS. 14, 15 and 16,
The processing flow until the routine for executing the signal delay evaluation of this embodiment is called will be described in more detail with a specific example.

FIG. 14 shows an example 1400 of the delay evaluation target circuit and the delay evaluation target section used for the explanation. In this example,
A partial circuit 1401 whose gate level design is completed,
This is an example in which design data of two partial circuits having different design levels of the partial circuit 1402 whose RT level design has been completed are mixed. In addition, the evaluation target section of the signal delay is the latch 1
Between 403-latch 1404, latch 1404-latch 1
405, between latches 1405 and 1406, and between latches 1407 and 1408. These evaluation target sections are defined in the evaluation target section data 507.

First, the signal delay evaluation routine selection program 600 selects and calls a delay evaluation routine applied to signal delay evaluation for each evaluation target section.

First, design level management data creation processing 1
100 reads the design data 506 and the evaluation target section data 507 to create design level management data 1500. In the design level management data creation process 1100, first, the latch at the starting point of each signal delay evaluation section defined in the evaluation target section data 507 is assigned to the node of the graph. In this example, the latch 1403 is the node 1501.
Latch 1404 to node 1502 and latch 140
5 is the node 1503, and the latch 1407 is the node 150
5 respectively. Next, a route search is performed in the signal flow direction from the latch at the starting point of each signal delay evaluation target section, and if a latch or interface signal is reached midway and this is not registered, this is registered as a node. In the case of this example, the interface signal 1411 by the route search from the latch 1404, the latch 1406 by the route search from the latch 1405, the interface signal 1412 by the route search from the latch 1407, the latch 1408, and the latch 1409 correspond to the node 1507, respectively. , Node 1504, node 1508, node 1506, and node 1509. Further, in this search processing, an edge is generated between the nodes corresponding to the reached latch and interface signal. For example, since the latch 1404 is reached by the search process from the latch 1403, an edge is created between the node 1501 and the node 1502 in the direction from the node 1501 to the node 1502. Further, the search processing from the latch 1404 reaches the latch 1405 via the interface signal 1411, so that the corresponding edges from the node 1502 to the node 1507 and the corresponding node 1507 to the node 1503 are generated. Next, similarly, a route search is performed from the latch at the end point of each signal delay evaluation target section in the direction opposite to the signal flow, and node registration and edge creation processing is performed for the latch and interface signals that arrive during the search. . In the case of this example, the latch 14
The latch 1410 by the route search from 04 corresponds, and the node 1510 and the edge 1515 are created.

In the above route search processing, the design level management data creation processing 1100 simultaneously determines the attribute expressing the design level for each edge. In this example, the edge 1511, the edge 1512, the edge 15
Since the route information corresponding to 16 and the edge 1517 is obtained from the design data at the gate level in all the sections, the attribute of these edges is set to the attribute G: gate level from the identifier of the design data. Also, the edge 151
3, the edge 1514 and the edge 1518 have corresponding route information in the design data of the RT level, and therefore the attribute of these edges is the attribute B: RT level.

Next, the delay evaluation routine selection judgment processing 12
00 refers to the evaluation target section data 507 and the design level management data 1500, and selects a delay evaluation routine to be applied to perform delay evaluation of each evaluation target section for each design target section. FIG. 16 shows a selection result of the delay evaluation routine for the example 1400 of the delay evaluation target section shown in FIG.

First, for the section between the latch 1403 and the latch 1404, the delay evaluation routine selection judgment processing 1200.
Is the design level management data 1500 corresponding to this section.
Check the attribute of the edge 1511 of the. In this case, edge 1
The attribute of 511 is G: gate level. Further, the existence and attributes of other edges connected to the nodes 1501 and 1502 on the design level management data corresponding to the latches 1403 and 1404 are checked. In this case, there is an edge 1515 whose end point is the node 1502, and its attribute is G: gate level. Based on the above information, the delay evaluation routine selection determination process 1200 selects the delay evaluation routine targeting the gate level for this section.

For the section between the latch 1404 and the latch 1405, the delay evaluation routine selection judgment processing 1200
The attribute of the corresponding edge of the design level management data 1500 is checked. In this section, there are two, an edge 1512 having an attribute G: a gate level attribute and an edge 1513 having an attribute B: an RT level attribute. As a result, the delay evaluation routine selection determination process 1200 selects a delay evaluation routine for a section that spans design data having different design levels, since this section is data in which the gate level and the RT level are mixed.

For the section between the latch 1405 and the latch 1406, the delay evaluation routine selection judgment processing 1200
Similar processing is performed, and a delay evaluation routine for a single RT level design data is selected for this section.

The delay evaluation routine selection judgment processing 1200 also applies to the sections of the latches 1407 and 1408.
Similarly, the attribute of the corresponding edge on the design level management data 1500 is checked. In the case of this section, the corresponding node 15
The attribute of edge 1516 from 05 to node 1506 is
Although it is at the G: gate level, there is a path to the node 1509 via the node 1508, and its edge attribute changes from the G: gate level to the B: RT level. This means that there is a fanout signal to the RT level design data. Therefore, the delay evaluation routine selection determination process 1200 selects the delay evaluation routine for the section in which the gate level / RT level are mixed as the delay evaluation routine applied to this section.

As described above, the signal delay evaluation routine selection program 600 selects the delay evaluation routine to be applied to each target section for which delay evaluation is to be performed. The selected data is stored as delay evaluation routine selection data 601.

Next, the evaluation routine call process 1300 calls the previously selected delay evaluation routine for each evaluation target section to actually perform signal delay evaluation.

As described above, the delay evaluation system 5
00 performs delay evaluation on the evaluation target section 1400 in the design data in which the design levels are mixed as shown in FIG. According to the present embodiment, for design data in which design levels are mixed, for an arbitrary evaluation target section in the design data,
The delay evaluation is possible without adding information for designating the delay evaluation routine to be applied. The applied delay evaluation routine is selected for each evaluation target section according to its design level. Therefore, it is possible to perform an accurate evaluation within the information obtained from the given design data.

FIG. 17 shows a signal delay evaluation routine group 170.
0 shows a list of each evaluation routine realized. FIG. 17
Is an example of a delay evaluation routine realized by the signal delay evaluation routine group 1700 when design data of three stages of RT level, gate level, and wiring design end level is targeted.

The delay evaluation routines to be realized are roughly classified into two types. One is a lazy evaluation routine for design data of a single design level, and three routines are realized according to the design level (identifiers 1 to 3). On the other hand, the other is a delay evaluation routine for design data having mixed design levels (identifiers 4 to 8), which are further classified into two. One is a delay evaluation routine (identifiers 4 to 6) that targets sections where the evaluation target sections span different design levels as illustrated in FIGS. 2 and 3, and the other is
In the delay evaluation routine (identifiers 7 to 8), the evaluation target section as illustrated in FIG. 4 is single, and the section in which the design information that is logically related to the target section and has different design levels exists is used. is there. Also for these, a delay evaluation routine corresponding to a combination of mixed design levels is realized.

As described above, the signal delay evaluation routine group 1
In 700, the design level of the design data of the target evaluation target section is single / mixed, and when they are mixed, a delay evaluation routine corresponding to a combination of the design levels is realized in advance.

FIG. 18 shows a signal delay evaluation routine group 170.
The configuration of the delay evaluation routine for the section of 0 in which the route of the evaluation target section spans a plurality of design data having different design levels is shown.

The delay evaluation routine 1800 receives the design data 506 in which the design levels are mixed, the evaluation target section data 507, and the technology data 508. Here, the evaluation target section targeted by this routine is
Evaluation target sections 200 and 30 shown in FIGS. 2 and 3.
Like 0, it is an evaluation target section that spans design data of different design levels. In addition, this routine 1800
Is a signal delay evaluation result for the evaluation section defined in the evaluation section target data 507,
Or to the display device 502.

In the delay evaluation routine 1800, prior to the delay calculation, the evaluation target section is divided into a sub section having a uniform design level and a mixed sub section, and the conventional delay is applied to the uniform sub section. The delay evaluation value is calculated by the evaluation method, and the mixed sections are calculated by applying the delay calculation method for the design data at the highest level of detail by supplementing the design information as appropriate. The delay evaluation value of the target section is obtained by summing up the delay evaluation values of these partial sections.

The delay evaluation routine 1800 receives the design data 506 and the evaluation target section data 507 as input, and evaluates the evaluation target section defined in the evaluation target section data 507 designated by the previous evaluation routine call processing 1300. , A partial section division process 1900 that outputs a partial section that is divided according to the degree of mixing of design levels and partial section data 1806 that defines the design level, and design data 506, technology data 508, and partial section data 1806 as input , Partial section data 180
A single level partial section signal delay calculation process 1801 for calculating a delay evaluation value for a partial section having a single design level of design data among the partial sections defined in No. 6 and outputting it to the partial section delay data 1807; , Design data 506, technology data 508, and partial section data 180
6 is an input, the mixed level part which calculates the delay evaluation value for the partial section in which the design levels of the design data are mixed among the partial sections defined in the partial section data 1806 and outputs it to the partial section delay data 1807 The section signal delay calculation processing 1802, the evaluation target section data 507 and the partial section delay data 1807 are input, and the delay evaluation value of the corresponding evaluation target section is set to the delay evaluation value of the partial section stored in the partial section delay data 1807. The evaluation target section evaluation processing 1803 calculated from the evaluation result data 509 or output to the display device 502.

In the delay evaluation routine 1800, the sub-interval division processing 190 is first performed for the target evaluation target section.
It divides into 0 partial sections according to the design level and outputs partial section data 1806. Here, the partial section data 1806 is the design level management graph 700 shown in FIG.
It has the same data structure as, and is composed of edges having nodes, attributes, and directions. Here, the node is a circuit element that is the start point and the end point of the divided partial section. An edge represents a connection between circuit elements having a logical path, its direction represents a signal flow direction, and its attribute represents its design level. Next, for these sub-sections, the single-level sub-section signal delay calculation processing 1801 is performed for the sub-sections having the single design level, and the mixed-level sub-section signal delay is performed for the sub-sections having the mixed design levels. The calculation processing 1802 calculates the signal delay evaluation value of each partial section and outputs it to the partial section delay data 1807. Here, the partial section delay data 1807 is a list of signal delay calculation values of the partial sections constituting each evaluation target section. Finally, the evaluation target section evaluation processing 1803
However, the delay evaluation value of the entire evaluation target section is calculated from the previously calculated signal delay evaluation value of the partial section and output to the evaluation result data 509 or the display device 502.

The partial section division process 1900 receives the design data 506 and the evaluation target section data 507. Of the evaluation target sections defined in the evaluation target section data 507, each evaluation target section specified by the evaluation routine call processing 1300 is divided into a single design level partial section and a partial section in which the design levels are mixed. To do. Then, the data defining these partial sections is output as the partial section data 1806 together with the design level of the design data corresponding to each partial section.

Single-level partial interval signal delay calculation processing 18
01 is design data 506 and technology data 50
8 and the partial section data 1806 as input, and refer to the design data 506 and the technology data 507 for the partial section having the single design level of the corresponding design data among the partial sections defined in the partial section data 1806. The delay evaluation value is calculated by
Output to. Here, the sub-section targeted by this processing is
Since the design level is single, it is possible to apply the conventional delay calculation method as it is, for example, as shown on pages 211 to 217 of the September 28, 1992 issue of Nikkei Electronics.

Mixed Level Partial Section Signal Delay Calculation Processing 18
02 is design data 506 and technology data 50
7, and the partial section data 1806 as an input, among the partial sections defined in the partial section data 1806, for the partial section in which the design levels of the design data are mixed,
The signal delay evaluation value is calculated, and the partial interval delay data 18
It outputs to 07.

Mixed Level Partial Section Signal Delay Calculation Processing 18
02 is design data 506 and technology data 50
8 and the partial section data 1806 as input, the design information supplement processing 1804 that supplements the design information that is necessary for the delay calculation method that applies this subsection and that is lacking in the design data 506 and outputs it as the design information supplement data 2000.
And design data 506, partial section data 1806, technology data 508, and design information supplement data 20.
00 as an input, the signal delay evaluation value of the partial section in which the corresponding design levels are mixed is calculated, and the partial section delay data 180 is calculated.
7 to output the mixed level signal delay calculation processing 1805.

Mixed Level Partial Section Signal Delay Calculation Processing 18
02 is intended for delay evaluation of subsections in which design levels are mixed. At that time, in order to improve accuracy, a delay calculation method for design data at the most detailed level among the mixed design levels is targeted. Apply. However, with the design data 506 as it is, it is not possible to obtain all the information (parameters) necessary for applying the above method.
Therefore, the mixed level partial section signal delay calculation processing 1802
Then, prior to the delay calculation, the process of supplementing the design data with the missing parameters, that is, the design information supplement process 1
It is characterized by having 804.

The design information supplement process 1804 receives the design data 506, the partial section data 1806, and the technology data 508. First, the parameters required for the selected delay calculation method are listed. Next, the design data 506 is searched for the listed parameters, and it is checked whether there is a circuit element that determines the parameters. If the circuit element does not exist in the design data 506, the parameter is assumed to be an empirically determined value according to the evaluation target section and is output to the design information supplementary data 2000.

The mixed level signal delay calculation processing 1805
Design data 506, partial section data 1806, technology data 508, and design information supplement data 2000
Is input, and the delay evaluation value is calculated for the partial section in which each design level is mixed. At that time, design data 506
The design information necessary to calculate the delay included in the design supplement information 2000 and the design supplement information defined in the design information supplement data 2000 are used. The calculated delay evaluation value is the partial interval delay data 180.
7 is output. It should be noted that in this processing, conventionally known delay calculation methods targeting single-level design data are implemented according to each design level.

As described above, the mixed level partial section signal delay calculation processing 1802 evaluates the signal delay for the partial section in which the design levels of the design data are mixed among the partial sections defined in the partial section data 1807. Calculate the value.

The evaluation target section evaluation processing 1803 receives the evaluation target section data 507 and the partial section delay data 1807 as input, calculates the delay evaluation value of the corresponding evaluation target section defined in the evaluation target section data 507, and outputs the evaluation result. The data 509 or the display device 502 is output. here,
The evaluation target section evaluation processing 1803 calculates the sum of the signal evaluation values of the partial sections constituting the evaluation target section, and sets this as the delay evaluation value of the corresponding evaluation target section.

As described above, the delay evaluation routine 1800
Enables accurate delay evaluation for an evaluation target section that spans design data in which design levels are mixed.

FIG. 19 shows a processing flow of the partial section division processing 1900.

The partial section division processing 1900 receives the design data 506 and the evaluation target section data 507 as input,
Of each evaluation target section in the evaluation target section data 507,
The evaluation target section to which the delay evaluation routine 1800 is applied is divided into subsections according to whether the design levels are uniform or mixed, and the definition data and the design level of each subsection are output as the subsection data 1806. The partial section data 1806 is a list of logical elements at the start and end points of each partial section, and the design level of the partial section.

In the partial section division processing 1900, first, in the processing 1901, the evaluation target section is mechanically divided with the logical elements existing on the route as boundaries. Here, the logic element refers to a gate, an interface signal, a latch, an input / output signal for expressing a function, and the like. That is, in the processing 1901, for these logical elements existing on the route of the evaluation target section, the route is divided in the order in which the signals on the route flow without referring to the design level.

Next, by processing 1902, processing 1901
The design level of each divided section divided by is checked with reference to the design data 506. At that time, the design level is checked not only for the route of the evaluation target section but also for all the paths connected from the logical element of the starting point of each divided section. Specifically, the design level of each route is determined from an identifier expressing the design level of the design data in which the connected logical elements discovered by these route searches are defined.

Next, by processing 1903, processing 1901 is performed.
With respect to each of the divided sections divided by, continuous ones having the same design level are integrated. For example, when the division section A and the division section B are continuous and the design levels are the same, the division section A-B including A and B is set as one division section.

Finally, the process 1904 is followed by the process 190.
The divided section that is not integrated by 3 is recognized as a target partial section, that is, a divided section by uniform / mixed design levels, and is output as partial section data 1806.

As described above, the partial interval division processing 19
00 divides the route of the evaluation target section into a single section having a design level and a partial section having a mixture of design levels.

FIG. 20 shows the types of design information (parameters) supplemented in the design information supplement processing 1804. As shown in the figure, the parameters to be supplemented differ depending on the combination of the design levels of the design data in the adjacent sections and their arrangements. The parameters required for the calculation formula are supplemented. Further, in the figure, "upstream" and "downstream" mean that the adjacent sections are on the source side and the sink side with respect to the signal flow direction. In the case of the present example, when the upstream is at the RT level and the downstream is at the gate level, the parameter indicating the driving capability of the output unit of the design data at the RT level is driven when the upstream is at the RT level and the downstream is at the wiring design end level. Capacity and virtual wiring length, gate level is upstream and RT is downstream
In the case of the level, the capacitance of the input terminal is the gate level in the upstream and the wiring design end level in the downstream, and the virtual wiring length is the input terminal capacitance in the case where the upstream is the wiring design end level and the downstream is the RT level. When the virtual wiring length is the wiring design end level on the upstream side and the gate level on the downstream side, the virtual wiring lengths are supplemented.

The value of the supplemented parameter is not always a fixed value but variable for each evaluation target section. Of these, the input terminal capacitance is a value proportional to the number of the signal referred to in the RT level functional representation. As for the wiring length, if the rough layout is determined, the virtual wiring length is calculated from the position information.

As described above, by using this supplementary information, it is possible to accurately evaluate the signal delay corresponding to each evaluation target section.

The processing flow of the delay evaluation routine 1800 will be described below in more detail with reference to the examples of FIGS. 21 and 23.

FIG. 21 shows an example 2 of the evaluation target section shown in FIG.
00 is again shown. Here, the partial circuit 201
Is gate level design data, and the partial circuit 202 is RT level design data. The start point of the evaluation target section is a latch 210 and the end point is a latch 211, which are logically connected via an interface signal 213. This evaluation target section spans design data in which gate level design data and RT level design data are mixed, and is an evaluation target section of the delay evaluation routine 1800.

First, the partial section division processing 1900 divides the main evaluation section into a single-level partial section and a mixed-level partial section according to the design level. First, processing 1901
As a result, the main evaluation section is
It is divided into four sections of 1, 2112, 2113, and 2114. Next, in processing 1902 and processing 1902, the design level of each divided section is checked, and the same divided section is integrated. In the case of this example, finally, as shown in FIG. 20, it is divided into three partial sections 2101, 2102, and 2103. Of these, the partial section 210
1 and 2103 are the gate level and R, respectively.
The T level is a single design level partial section, and the partial section 2102 is a mixed section of the gate level and the RT level.

Next, the single level partial section signal delay calculation processing 1801 executes the preceding partial sections 2101 and 2103.
The delay evaluation value of is calculated. In this case, the partial section 2101
For, the gate level delay calculation method is
At 103, the RT level delay calculation method is executed. Note that these calculation methods are conventionally known methods. These calculated values are stored in the partial interval delay data 1807.

Subsequently, the mixed level partial section signal delay calculation processing 1802 calculates the delay evaluation value of the preceding partial section 2102. First, by the design information supplement processing 1804,
Design information necessary for the delay calculation method for evaluating this section and not obtained from the design data 506 is supplemented. In this example, the gate level delay calculation method, which is the most detailed level, is applied to the partial section 2102. When this is applied to this section, the sink element of the interface signal 213 in the partial circuit 202 is applied. Input terminal capacitance is required. However, in the design data 506, in the design data of the partial circuit 202, the interface signal 21
3 only appears in the functional expression 212 such as a Boolean expression, and the element is not specified. Therefore, the design information supplement process 18
As shown in FIG. 22, 04 is an interface signal 2
Assuming the capacitance of the virtual element, specifically, the capacitance of the input terminal, as the 13 sink elements, the information is used as the design information supplement data 200.
Output to 0. Incidentally, this virtual element is empirically assigned with a frequently used element as an input element of the interface signal. Further, another functional expression having the interface signal 213 as an input is also searched and a virtual element proportional to the number is assigned. Next, the mixed level signal delay calculation processing 1805 executes the design data 506 and the partial section data 180.
6, the technology data 508 and the design information supplementary data 2000 are referred to, and the delay evaluation value of the partial section is calculated. In the case of only the design data 506 for this partial section 2102, the gate level delay calculation method cannot be applied, but it is applied by using the virtual sink element information of the interface signal 213 defined in the design information supplementary data. It will be possible. The calculated delay evaluation value of the partial section is output to the partial section delay data 1807.

Finally, the evaluation target section evaluation processing 1803
However, the delay evaluation values of each partial section are summed up and output to the evaluation result data 509 or the display device 502 as the delay evaluation value of the evaluation target section.

As described above, this delay evaluation routine 1800
Is the design data 5 for the section where the design levels are mixed.
By appropriately supplementing the design information which cannot be obtained from 06, the evaluation by the delay evaluation method at the most detailed level becomes possible.

Next, an example of the evaluation target section shown in FIG. 23 will be described. The example of FIG. 23 is the same as the example shown in FIG. Here, the partial circuit 301 is gate level design data, and the partial circuit 302 is RT level design data. The start point of the evaluation target section is the latch 310, and the end point is the latch 311.

In the case of this example, both the latch 310 at the start point and the latch 311 at the end point of the evaluation target section are present in the partial circuit 301, and both of them include gate level design data. However, in this section, the fan-out signal of the gate G1 is connected to the latch 312 in the partial circuit 302, which is at the RT level, via the interface signal 313. Therefore, when performing the delay evaluation of this evaluation target section, it is not possible to apply the delay calculation method for the single design data at the gate level, and it is necessary to apply the delay calculation method for mixed gate level / RT level. I won't. That is, this evaluation target section is the delay evaluation routine 1800.
Be subject to.

First, as in the case of the example of FIG. 21, the partial section division processing 1900 divides the main evaluation target section into partial sections according to the degree of mixing of the design levels. In this case, FIG.
As shown in FIG.
It is divided into three sub-sections 03. Here, the partial sections 2301 and 2303 are partial sections on a single gate level design data, and the partial section 2302 is a partial section in which the gate level and the RT level are mixed.

Next, partial sections 2301 and 2303
For the single-level partial interval signal delay calculation processing 180
1 calculates each delay evaluation value. Here, the calculation method applied is a delay evaluation method for a single gate level. The calculation result for each partial section is stored in the partial section delay data 1807.

For the partial section 2302, the delay evaluation value is calculated by the mixed level partial section signal delay calculation processing 1802. First, the design information replenishment process 1804 replenishes design information that is insufficient in applying the gate-level delay calculation method. Also in this example, since the input capacitance of the sink element of the interface signal 313 is required, the design information supplement process 1804 allocates a virtual element as the sink element of the interface signal 313. Finally, the mixed level signal delay calculation processing 1805 refers to the design data 506, the technology data 508, and the design information supplementary data 2000 by the gate level delay calculation method, and then the main section section 230.
The delay evaluation value of 2 is calculated, and the partial interval delay data 1807 is calculated.
Output to.

Finally, the evaluation target section evaluation processing 1803
Calculates the total of the delay evaluation values of these three partial sections and outputs the result to the evaluation result data 509 or the display device 502. With the above processing flow, the delay evaluation value of the evaluation target section shown in FIG. 23 is calculated.

As described above, the delay evaluation routine 180
According to 0, the evaluation target section in which the design levels are mixed is divided into a single design level partial section and the mixed design level partial section, and the evaluation is performed. By adopting the delay calculation method of the detail level and supplementing the lacking design information as appropriate, it becomes possible to perform accurate signal delay evaluation. When replenishing, not the fixed value but the replenishment data according to the situation of the evaluation target section is adopted, so that the accuracy can be improved.

FIG. 24 shows the configuration of the second delay evaluation routine 2400 for the evaluation target section that spans a plurality of design data of different design levels according to the present invention.

The delay evaluation routine 2400 receives the design data 506 having mixed design levels, the evaluation target section data 507, and the technology data 508. Here, among the sections defined in the evaluation target section data 507, the sections targeted by this routine are different designs for the same design target circuit, like the evaluation target section 400 shown in FIG. This is an evaluation target section in the target circuit in which the level design data exists. Further, the routine 2400 outputs the signal delay evaluation result for the evaluation section defined in the evaluation section target data 507 to the evaluation result data 509 or the display device 502.

The delay evaluation routine 2400 corresponds to the routines of the identifiers 7 and 8 in FIG. 17, but the design levels to be evaluated are the gate level and the wiring design end level in the evaluation target section, and others. Only when the design data of is at the RT level.

The delay evaluation routine 2400 receives the design data 506, the evaluation target section data 507, and the technology data 508 as input, and outputs only the design data at the most detailed level for each evaluation target section for which this routine is called. A single-level signal delay calculation process 2401 for calculating a delay evaluation value by reference and outputting it as basic delay value data 2402, design data 506, evaluation target section data 507, technology data 508, and basic delay value data 2402. Is input, and basic delay value data 2402 is calculated for each evaluation target section using design data not used in the previous single-level signal delay calculation processing 2401.
The signal delay value correction processing 2500 is performed to perform correction on the basic delay value stored in, and output the result to the evaluation result data 509 or the display device 502.

In the delay evaluation routine 2400, for each evaluation target section defined in the evaluation target section data 507, the single level signal delay calculation processing 2401 first designs part of the design data of each evaluation target section. A signal delay value is calculated using the data and output as basic delay value data 2402. This basic delay value is a delay evaluation value calculated using only the data at the most detailed design level among the data in the design data 506 corresponding to each evaluation target section. Next, the signal delay value correction processing 2500 corrects the basic delay value stored in the basic delay value data 2402 using the design data in the design data 506 that was not referenced when calculating the basic delay value. The corrected delay evaluation value is output to the evaluation result data 509 or the display device 502.

The single level signal delay calculation processing 2401 is
Using the design data 506, the evaluation target section data 507, and the technology data 508 as input, the design data at the most detailed level is used for each evaluation target section to which the delay evaluation routine 2400 in the evaluation target section data 507 is applied. Then, a signal delay value is calculated, and this is output as basic delay value data 2402. This process is a conventionally known lazy evaluation method for single-level design data. Specifically, for example, Nikkei Electronics 1992
It is a delay evaluation method targeted at the gate level or the wiring design end level shown on September 28, pages 211 to 217. Note that the calculated signal delay value is the design data 506.
The evaluation accuracy at this stage is not good because only a part of the relevant data in the above is used. Therefore, it is necessary to correct this signal delay value.

The basic delay value correction processing 2500 receives the design data 506, the evaluation target section data 507, the technology data 508, and the basic delay value data 2402 as input, and the basic delay value calculation processing 2401 calculates the basic delay value. Of the corresponding design data in the design data 506, the delay value is corrected using the design data not referred to by the previous single-level signal delay calculation processing 2401, and the correction value is evaluated result data 509, Alternatively, it is output to the display device 502. Here, the design level of the design data not referred to is the RT level.

FIG. 25 shows a processing flow of the basic delay value correction processing 2500. In the basic delay value correction processing 2500, R
The correction is performed in consideration of fan-in and fan-out logically related to the evaluation target section on the T-level design data.

First, in process 2501, the number of other latches whose sink is the end point latch of the evaluation target section is counted in the design data at the RT level. In particular,
In the RT-level design data, the functional expression in which the end-point latch of the evaluation target section is output is searched, and the number of latches that are the input is counted.

Next, in process 2502, the number of other latches whose source is the starting point latch of the evaluation target section is counted in the RT level design data. In particular,
In the RT-level design data, the functional expression in which the starting point latch of the evaluation target section is an input is searched, and the number of latches that are the output is counted.

Based on the above number, in step 2503, the basic delay value 2402 is corrected. Specifically, as shown in the figure, processing 2501 and processing 250
Add a value proportional to the value obtained by 2. This process occurs when the part that has not been refined is refined for the partially refined evaluation target section,
It is nothing but the consideration of fan-in and fan-out.

Finally, in process 2504, the corrected value is output to the evaluation result data 509 or the display device 502.

Hereinafter, the processing flow of the delay evaluation system 2400 will be described in more detail with reference to the example of FIG.

FIG. 26 shows an example 4 of the evaluation target section shown in FIG.
00 is again shown. Here, the partial circuit 401
Is design data at the RT level. Furthermore, the partial circuit 4
A part of the circuit 402 of 01 is designed up to the gate level. That is, the partial circuit 402 has different design data of two design levels of the RT level and the gate level. Further, the evaluation target section in which the signal delay evaluation is performed is a section in which the latch 410 is the starting point and the latch 411 is the ending point. Since this section is included in the partial circuit 402, its route exists in the gate-level design data. Further, as shown in FIG. 24, a logical path starting from the latch 412 not included in the partial circuit 402 and ending at the latch 411 and a latch 413 starting from the latch 410 and not included in the partial circuit 402 as the ending point. There is a logical route to do. These logical paths are
In the RT level design data for the partial circuit 401,
For example, it is expressed by a functional expression such as a Boolean expression. In the case of this example, even if the delay evaluation method for design data of a single gate level is applied to the delay evaluation of the evaluation target section, the fan-in element from the latch 412, the latch 41
The fanout factor to 3 cannot be considered. This is because, for example, considering a fan-in signal from the latch 412, when this signal is designed up to the gate level, the signal is always in the path from the latch 410 to the latch 411 to be evaluated by a logical element such as a selector. Connected. However, it is impossible to specify the location of the connection at this point in time, and the influence of the fan-in signal on the signal delay of the path from the latch 410 to the latch 411 is reflected by the gate-level delay calculation formula. I can't let you do it. Further, regarding the fan-out element to the latch 413, it is not possible to specify the place where the signal specifically branches, so the influence thereof cannot be similarly considered.

On the other hand, the delay evaluation routine 240
At 0, first, the single level signal delay calculation processing 2401
The basic delay value of this evaluation target section is calculated by the delay evaluation method for the gate level. In this processing, of the data in the design data 506, only the gate-level design information is referenced.

Next, the signal delay value correction processing 2500 corrects the basic value calculated previously. In the case of this example, RT for the basic delay value based on the gate level design data
Correction is performed based on the level design information. First process 25
By 01, the number 2601 of other latches with the latch 411 as a sink is counted in the RT level design data of the partial circuit 401. In this case, the latch 412 is the relevant latch. Next, the process 2502 searches for another latch whose source is the latch 410 and counts the number 2602. In this case, the latch 413
Is applicable. The above count numbers 2601 and 2602
25, the basic delay value previously calculated by the single level signal delay calculation processing 2401 is corrected by the processing 2503 by the correction equation shown in FIG.

As described above, the delay evaluation routine 240
According to 0, it is possible to perform the delay evaluation with high accuracy while considering the design data of each design level in the evaluation target section when the design data of a plurality of design levels exist for the same circuit. To do.

[0134]

According to the signal delay evaluation method of the present invention, it is possible to evaluate the signal delay of an arbitrary evaluation target section for design data in which arbitrary design levels are mixed, without being aware of the design levels. it can. In addition, it is possible to accurately evaluate even the evaluation target section that spans the design data in which the design levels are mixed, by supplementing the insufficient design information. Therefore, especially in the top-down design method, the planning for selecting a plurality of design candidates can be easily performed, and the design period can be shortened and the design quality can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of design data mixed with design levels targeted by a signal delay evaluation method of the present invention.

FIG. 2 is a first exemplary diagram of a signal delay evaluation target section targeted by the present invention.

FIG. 3 is a second exemplary diagram of a signal delay evaluation target section targeted by the present invention.

FIG. 4 is a third exemplary diagram of a signal delay evaluation target section targeted by the present invention.

FIG. 5 is a configuration diagram of a system for implementing the signal delay evaluation method of the present invention.

FIG. 6 is a flowchart of a signal delay evaluation routine selection program according to the present invention.

FIG. 7 is an explanatory diagram of design level management data according to the present invention.

FIG. 8 is a first exemplary diagram of design level management data according to the present invention.

FIG. 9 is a second exemplary diagram of design level management data according to the present invention.

FIG. 10 is a third design level management data according to the present invention.
It is an illustration figure of.

FIG. 11 is a flowchart of a design level management data creation process according to the present invention.

FIG. 12 is a flowchart of a delay evaluation routine selection determination process according to the present invention.

FIG. 13 is a flowchart of an evaluation routine call process according to the present invention.

FIG. 14 is a view showing an example of delay evaluation target circuits and sections.

15 is a view showing an example of design level management data for the evaluation target section shown in FIG.

16 is a view showing an example of a delay evaluation routine selection result for the evaluation target section shown in FIG.

FIG. 17 is an explanatory diagram of a signal delay evaluation routine group according to the present invention.

FIG. 18 is an explanatory diagram showing a first implementation of a delay evaluation routine according to the present invention.

FIG. 19 is an explanatory diagram of a partial section division process according to the present invention.

FIG. 20 is an explanatory diagram of design information supplementary data according to the present invention.

FIG. 21 is an explanatory diagram of a signal delay evaluation method of the present invention for the evaluation target section shown in FIG.

22 is an exemplary diagram of design information supplementation according to the present invention for the evaluation target section shown in FIG. 21. FIG.

23 is an explanatory diagram of a signal delay evaluation method of the present invention with respect to the evaluation target section shown in FIG.

FIG. 24 is an explanatory diagram showing a second implementation of the delay evaluation routine according to the present invention.

FIG. 25 is a flowchart of signal delay value correction processing according to the present invention.

FIG. 26 is an explanatory diagram of a signal delay evaluation method of the present invention for the evaluation target section shown in FIG.

[Explanation of symbols]

500 ... Signal delay evaluation system, 506 ... Design data in which design levels are mixed, 507 ... Evaluation target section data, 5
08 ... Technology data, 509 ... Evaluation result data,
600 ... Signal delay evaluation routine selection program, 601
... delay evaluation routine selection data, 700 ... design level management data, 1100 ... design level management data creation processing,
1200 ... Delay evaluation routine selection judgment processing 1300 ...
Evaluation routine call processing, 1700 ... Signal delay evaluation routine group.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsuguo Shimizu 1-280 Higashi-Kengikubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (21)

[Claims] 1. A computer system having a processing device and a storage device, comprising (a) a digital logic circuit,
A user who stores design data composed of a plurality of partial design data representing a plurality of partial circuits designed at different design levels in the storage device, and (b) specifies a section in which the signal delay in the logic circuit should be calculated. In response to the designated section data, the design level of the section designated by the section data is discriminated from the design data, and (c) as a result of the discrimination, the designated section has a single design level. When it is determined to have, based on the design data for the section,
A signal delay evaluation method for calculating a signal delay time of the section according to a design procedure in advance corresponding to the design level. 2. The signal delay evaluation method according to claim 1, wherein the plurality of delay time calculation methods include a delay time calculation method corresponding to a register transfer level, a gate level, and a hard macro design level, respectively. (D) As a result of the judgment, when it is judged that the designated section is composed of a plurality of partial sections having different design levels, based on the design data regarding each partial section, and the part thereof. The signal delay time of the partial section is calculated according to the calculation procedure determined by the design level of the section, and (e) the signal delay time of the specified section is calculated from the signal delay time calculated for each partial section. The signal delay evaluation method according to claim 1, which is calculated. 4. A computer system having a processing device and a storage device, comprising (a) a digital logic circuit,
A user who stores design data composed of a plurality of partial design data representing a plurality of partial circuits designed at different design levels in the storage device, and (b) specifies a section in which the signal delay in the logic circuit should be calculated. In response to the specified section data, and when the section specified by the section data has a plurality of partial sections having different design levels, based on the design data for each partial section, and
The signal delay time of the partial section is calculated according to the calculation procedure determined by the design level of the partial section, and (c)
The signal delay time of the specified section is calculated from the signal delay time calculated for each sub section, and in the step (b), any one of the specific sub sections is adjacent to the sub section. When a subsection whose design level is higher than that of the subsection, the at least one parameter required by the calculation procedure determined by the particular design level of the particular subsection is generated, and the particular subsection is generated. A signal delay evaluation method for calculating a signal delay time of the specific sub-interval based on the design data and the generated parameter according to the above-described calculation procedure defined corresponding to the specific design level. 5. The generated parameter includes a parameter to be given by the design data of the adjacent partial section when the adjacent partial section has the design level of the specific partial section. Signal delay evaluation method. 6. The generated parameter is a parameter relating to a load of the adjacent partial section to the specific partial circuit when the adjacent partial section is connected to an output side of the specific partial section. 6. The signal delay evaluation method according to claim 5, which includes. 7. The generated parameter, when the specific sub-section is a gate level section, the load of the adjacent sub-section includes a parameter regarding a load capacitance for the specific sub-circuit. 6. The signal delay evaluation method according to item 6. 8. The generated parameter is a parameter relating to the drive capability of the adjacent partial section with respect to the specific partial circuit, when the adjacent partial section is connected to the input side of the specific partial section. 6. The signal delay evaluation method according to claim 5, including. 9. A computer system having a processing device and a storage device, comprising: (a) a digital logic circuit,
A user who stores design data composed of a plurality of partial design data representing a plurality of partial circuits designed at different design levels in the storage device, and (b) specifies a section in which the signal delay in the logic circuit should be calculated. In response to the designated section data, and when the section has one design level, it is connected to one output side of a plurality of functional elements included in the designated section, and is connected to the designated section. Other sections including other functional elements that do not belong are extracted from the design data,
(C) When the design level of the other section is lower in design level than the design level of the designated section, a parameter of a type predetermined by the specific design level is used for the other section. A signal that is generated from design data and that calculates the signal delay time based on the generated parameters and design data related to the specified section and by the calculation procedure determined by the design level of the specified section. Lazy evaluation method. 10. The signal according to claim 9, wherein the generated parameter includes a parameter to be given by design data of the other section when the other section has a design level of the specific subsection. Lazy evaluation method. 11. The signal delay evaluation method according to claim 10, wherein the generated parameter includes a parameter relating to a load of the other section with respect to the specific partial circuit. 12. The signal delay according to claim 11, wherein when the specific sub-section is a gate-level section, the other load includes a parameter regarding a load capacitance for the sub-circuit. Evaluation methods. 13. A computer system having a processing device and a storage device, the design comprising: (a) a plurality of partial design data which constitute a digital logic circuit and represent a plurality of partial circuits designed at different design levels. Data is stored in the storage device, and (b) a plurality of sections are responsive to user-specified section data specifying a section in which the signal delay in the logic circuit is to be calculated, and the sections have different design levels. , Which is connected to the output side of one of the functional elements included in each partial section and includes another functional element that does not belong to the specified section, When the design level of the other section extracted from the design data and extracted for any one of the subsections has a lower design detail than the design level of the subsection, the identification A parameter of a type predetermined by a design level is generated from design data regarding the other section, and (d) is determined based on the design data regarding each of the plurality of subsections and by the design level of the subsection. The signal delay time of the partial section is calculated according to the calculated calculation procedure, (e) the signal delay time of the specified section is calculated from the signal delay time calculated for each partial section, and (f) The signal delay time of the designated section is calculated from the signal delay time calculated for each partial section, and in step (d) above, the signal delay time of any of the partial sections is determined by the step (b). Is extracted based on the parameters generated in step (c) and the design data for the partial section, and The signal delay evaluation method for calculating the signal delay time of the partial section according to the calculation procedure determined by the design level of the partial section. 14. The signal according to claim 13, wherein the generated parameter includes a parameter to be given by design data of the other section when the other section has a design level of the specific subsection. Lazy evaluation method. 15. The signal delay evaluation method according to claim 14, wherein the generated parameter includes a parameter relating to a load of the other section with respect to the specific partial circuit. 16. The signal delay according to claim 15, wherein the generated parameter includes a parameter relating to a load capacitance for the partial circuit when the specific sub-section is a gate level section. Evaluation methods. 17. A computer system having a processing device and a storage device, the design comprising: (a) a plurality of partial design data which constitute a digital logic circuit and represent a plurality of partial circuits designed at different design levels. Storing data in the storage device, and (b) in response to user-specified section data specifying a section in which the signal delay in the logic circuit is to be calculated, and when the section has one design level. , Other sections that should be connected to the functional elements included in the specified section, but are not determined to be connected to the input terminal of which functional element or the output terminal of which functional element, It is detected whether or not there is, based on the design data, and (c) based on the design data regarding the designated section and determined by the design level of the designated section. The signal delay time is calculated by a calculation procedure, and (d) when the other section is detected, the signal delay time calculated for the section is connected to the other section and the designated section. A signal delay evaluation method that corrects based on a relationship. 18. The signal delay evaluation method according to claim 17, wherein the connection relation includes the number of signal lines connected between the other section and the designated section. 19. A computer system having a processing device and a storage device, the design comprising: (a) a plurality of partial design data which constitute a digital logic circuit and represent a plurality of partial circuits designed at different design levels. Storing data in the storage device, and (b) in response to user-specified section data specifying a section for calculating a signal delay in the logic circuit, and sections specified by the section data are mutually When having a plurality of sub-sections having different design levels, they should be connected to the functional elements included in each sub-section, but connected to the input end of any functional element or the output end of any functional element. Whether or not there is another section whose power is not determined is detected based on the design data, and (c) based on the design data regarding each partial section, and The signal delay time of the partial section is calculated in accordance with the calculation procedure determined by the design level between them, and (d) when the other section is detected with respect to any partial section, it is calculated with respect to the partial section. The signal delay time is corrected based on the connection relationship between the other section and the partial section, and (e) the specified value is calculated from the signal delay time calculated for each partial section or the corrected signal delay time. A signal delay evaluation method for calculating a signal delay time in a section. 20. The signal delay evaluation method according to claim 19, wherein the connection relation includes the number of signal lines connected between the other section and each partial section. 21. In a computer system having a processing device and a storage device, (a) a design which comprises a plurality of partial design data which constitute a digital logic circuit and represent a plurality of partial circuits designed at different design levels. Storing the data in the storage device, and (b) responding to user-specified section data specifying a path for calculating a signal delay in the logic circuit, the section specified by the section data is divided into a plurality of partial sections. And (c) combining a plurality of sub-sections adjacent to each other and having the same design level into one new sub-section among the plurality of sub-sections, and (d) obtaining a plurality of sub-sections obtained after the combining processing. The signal delay time in each of the divided sections is calculated according to the calculation procedure determined depending on the design level of the partial section and based on the design data of the partial section, and (e) each partial section. The signal delay time of the specified section is calculated on the basis of the signal delay time calculated with respect to, and in the step (d), the design level of any one of the specific sub sections is When the design level is a specific design level that is more detailed than the adjacent subsections on the input side or the output side, there is a step of generating a parameter of the type determined by the particular design level, and the signal of the particular subsection is generated. A signal delay evaluation method for calculating a delay time on the basis of design data for a partial section and parameters generated for the specific partial section and by a specific calculation procedure determined by the specific design level.