JPH0763180B2 - FPN automatic correction method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infrared imaging device using a focal plane array sensor, and more particularly to a fixed pattern noise (FP) of image data due to pixel-to-pixel variation in sensor characteristics.
N) regarding the automatic removal method.

[0002]

2. Description of the Related Art An image pickup device using a focal plane array sensor has unevenness in the background, and it is necessary to remove the FPN contained in the image signal in order to improve the image quality. The cause of the FPN of this image data is that the sensor operating temperature (cooling temperature) fluctuates or the incident infrared light (especially the background that is uniformly incident on the surface is caused by the variation in the characteristics of each pixel of the focal plane array sensor). This is because the output of each pixel changes non-uniformly due to the fluctuation of (infrared light). This variation in element characteristics can be divided into variation in leak current and variation in element sensitivity for each element. To correct the variation in sensitivity, a correction coefficient is multiplied for each pixel output to determine the output change with respect to the incident light amount. Must be uniform.

The level of realization of this variation in sensitivity differs depending on the material used for the sensor, etc., and in the case of a sensor with relatively little variation, the circuit configuration and FPN removal scanning can be realized by only one-point correction, that is, correction by subtraction. ing. That is, FPN data unique to each sensor is acquired and stored in a memory under uniform infrared input conditions, and the stored FPN data is subtracted from the input image data to obtain FPN-removed image data. There is. Also, in the case of a sensor with a larger sensitivity variation or when more accurate correction is required, it is necessary to completely correct the fluctuation of the infrared incident light amount due to a large change in ambient temperature or a change in subject background temperature. Therefore, for this purpose, in addition to the correction by the subtraction described above, the variation of the sensitivity variation (tilt) is generally corrected. For example, a method of performing tilt correction by multiplication and offset correction by subtraction, or calculating a difference that should be corrected for sensitivity correction by multiplying gain correction data and fluctuating incident light quantity, and subtracting from the original data to correct tilt variation. (Japanese Patent Laid-Open No. 2-10707)
4). In any case, the two-point correction is performed using the gain (tilt) information for each element to be written. In this case, the gain correction data is generally a two-point correction method because it is necessary to obtain output data at two different incident light amounts that are uniform in the plane and obtain the information from the difference. Therefore, the data acquisition operation and the calculation process of data creation must be complicated.

FIG. 2 is a diagram showing an example of the configuration of a conventional FPN automatic correction system which has been recently disclosed in order to avoid the difficulty of the two-point correction (Japanese Patent Laid-Open No. 4-79485). However, in this figure, those not related to the essence of the invention such as the D / A converter are omitted, and the reference numerals are changed in relation to the reference numerals in the present invention. This device has a subtractor 2,
Base unevenness (FPN) data memory 4, variable gain amplifier 7, difference calculators 8 and 9, binarization circuits 10 and 11,
An exclusive OR gate 12 and an up / down pulse separation circuit (a combination of 14B and 14C) that separates an input into an up component and a down component for each (bit) clock signal, and an up component and a down component separated for each bit clock. It is composed of an up / down counter 15 which counts and outputs the difference output to the variable gain amplifier 7. With such a configuration, the number of in-phase bits of the outputs of the two binarization circuits 10 and 11 (both outputs are "1"). The output of the variable gain amplifier circuit 7 is controlled for each bit clock so that the difference between the "or" and "0") and the number of opposite-phase bits (both outputs are "1" and "0") is zero.

[0005]

Although it is certain that the conventional FPN elimination method described above has a simpler configuration than before, it cannot be said that the control of the variable gain amplifier is performed sufficiently stably. It was Then, as a result of the examination, it is controlled to the output of the variable gain amplifier 7 because a portion which should be called a “pulse accumulating circuit” composed of the up / down pulse separation circuit (14B + 14C) and the up / down counter 15 operates for each bit clock. Since the output changes with each clock, it cannot be said that it is always constant when considered as one frame. More specifically, in this method, the outputs of the difference calculators 8 and 9 are included in either the increase or the decrease when the difference is zero. In some cases, it will not always be constant. Therefore, it is not preferable when the stability of the output image signal is particularly important. If the ternary method is used instead of the binary method, this problem should be solved.
This makes the circuit very complicated and is not preferable from another aspect.

Therefore, the present invention is to obtain a stable output image signal without performing ternarization by the above-mentioned conventional method and perform the optimum correction of the FPN.

[0007]

According to the present invention, the determination of the number of in-phase bits and the number of out-of-phase bits is performed by utilizing the fact that the total number of bits in one frame is fixed. The number of bits is counted and accumulated, the number of bits in one frame is discriminated, and the up / down counter is updated according to information indicating whether the number of bits is greater than or less than 1/2 of the total number of bits. .

That is, according to the present invention, an FP used in an infrared imaging device using a focal plane sensor
A method for automatically correcting N, including a memory for storing FPN data included in input image data, and an FPN data generation circuit for reading the stored data in synchronization with the input image signal to generate correction data. , A variable gain amplifier controlled by a control signal and capable of setting an arbitrary multiplication factor with respect to the output of the FPN data generating circuit, and an output image signal is generated by subtracting the output of the variable gain amplifier from the input image signal. A subtracter, the output of the subtractor and the F
Two difference calculators that detect an increase / decrease in the output of the PN data generation circuit from the previous pixel data in time series, and two binarization circuits that binarize the detected increase / decrease value in accordance with the increase / decrease. And FPN automatic control having means for taking an exclusive OR of the outputs of the two binarization circuits, and pulse accumulating means for generating a control signal for controlling the multiplication factor setting of the variable gain amplifier from the output of the exclusive OR. In the system, the pulse accumulating means counts the number of times the exclusive OR output is positive or negative within one frame period, and based on the result of counting, the output that goes up or down every frame is changed as the control signal. FPN having U / D counter for sending to gain amplifier
An automatic correction method can be obtained.

More specifically, the pulse accumulating means compares a counter means for counting the number of times the exclusive OR output is positive or negative within one frame period with an output of the counter means with a set value. And a U / D counter that sends an output that goes up or down for each frame according to the level of the output of the comparator to the variable gain amplifier as the control signal.

[0010]

1 is a block diagram of an FPN automatic correction system according to an embodiment of the present invention. As the FPN data, FPN data from which random fluctuations have been removed by frame integration and the like in the state where uniform infrared light is incident in advance is acquired and stored in the FPN data memory 4, and each of the input image signals 1 is input by the FPN data generation circuit 5. The level is automatically adjusted by the variable gain amplifier 7 whose gain is read in synchronization with the pixel output and whose gain is controlled by the control signal 6, and subtracted from the input image signal 1 by the subtractor 2 to obtain the output image signal 3. .

The control signal 6 is obtained as follows. That is, when the output of the FPN data generation circuit 5 is input to the difference calculator 8 and the output of the output image signal 3 is input to the difference calculator 9, the image data is converted into time series data in the scan order by these circuits. The increase / decrease in the value with respect to the previous pixel data is detected based on the difference from the immediately previous pixel data. Then, the detected values are input to the binarization circuits 10 and 11, respectively, and binarized. When there is no increase or change, "positive",
In the case of decrease, the value is “negative” (or inverse logic). Further, an exclusive OR circuit (EX-OR) 12 takes an exclusive OR of both outputs, and when both data match, an output which becomes "negative" is obtained. This output is accumulated for each pixel by the counter 13 within one frame period, and the comparator 14 determines which of the "positive" number and the "negative" number is larger. Depending on the determination result, the up / down counter (U / D counter) 15 is up or down for each frame.
N (for example, DOWN when the number of “positive” is large, UP when the number of “negative” is large, etc.). As a result, when there is residual FPN in the output image signal 3 due to lack of subtraction gain, FP
Since the N data and the output image signal include the same fixed pattern, the outputs of the binarization circuits 10 and 11 have the same logic, and as a result, the counter 13 and the comparator 14 determine that the number of "negative" is large, and U / D counter 15 is U
P. In the opposite case, DOWN is performed. The output value of the U / D counter 15 is the control signal 6. Counter 1
3, the comparator 14 and the U / D counter 15 should also be called a pulse accumulating circuit indicated by 16 in total, and the internal configuration of this circuit is a feature of the present invention.

By adding the control signal 6 thus obtained to the variable gain amplifier 7 and setting the gain, the value of the U / D counter 15 is increased and the gain of the variable gain amplifier 7 is increased. , Is automatically controlled so that the FPN component included in the output image signal 3 is minimized by operating in the same manner for each frame.

In the above circuit, the case where the input and output image signals are all digital signals has been described. However, when these are analog syngonos, a D / A converter is provided on the FPN data generating circuit 5 side of the variable gain amplifier 7. An A / D converter may be inserted at the branch point of the signal path to the output image signal 3 and the difference calculator 9.

[0014]

As described above, according to the present invention, the counter 13 in which the pulse accumulating circuit operates by the frame clock is used.
With the comparator 14 and the U / D counter 15, the update is performed according to the difference result for each frame, so that the control to the variable gain amplifier 7 becomes constant within one frame, and a more uniform correction effect is obtained. You can get it.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input image signal 2 Subtractor 3 Output image signal 4 Base unevenness (FPN) data memory 5 FPN data generation circuit 6 Control signal 7 Variable gain amplifier 8 Difference calculator 9 Difference calculator 10 Binarization circuit 11 Binarization circuit 12 EX-OR (exclusive OR circuit) 13 counter 14 comparators 14B, 14C EX-OR 15 U / D counter (up / down counter)

Claims (2)

[Claims] 1. A method for automatically correcting an FPN used in an infrared imaging device using a focal plane sensor, comprising: a memory for storing FPN data included in input image data; and the input of the stored data. An FPN data generation circuit that reads out in synchronization with an image signal to generate correction data, and is controlled by a control signal.
A variable gain amplifier in which an arbitrary multiplication factor can be set with respect to the output of the data generation circuit, a subtractor that subtracts the output of the variable gain amplifier from the input image signal to generate an output image signal, and a subtractor of this subtracter Two difference calculators for detecting an increase / decrease of the output and the output of the FPN data generation circuit with respect to the previous pixel data in a time series, and two difference calculators for binarizing the detected increase / decrease value corresponding to the increase / decrease. A binarizing circuit, means for taking an exclusive OR of the outputs of the two binarizing circuits, and pulse accumulating means for generating a control signal for controlling the multiplication factor setting of the variable gain amplifier from the output of the exclusive OR. In the FPN automatic control method, the pulse accumulating unit counts the number of times the exclusive OR output is positive or negative within one frame period, based on the result of counting, An FPN automatic correction method, comprising means for sending an output that goes down or down as the control signal to the variable gain amplifier. 2. A means for sending an output up or down for each frame to the variable gain amplifier as the control signal based on a result of counting the number of times the exclusive OR output is positive or negative within the one frame period. The pulse accumulating means having a counter means for counting the number of times the exclusive OR output is positive or negative in one frame period, a comparator for comparing the output of the counter means with a set value, and an output of the comparator. 2. The FPN automatic device according to claim 1, wherein the FPN automatic means is a pulse accumulating unit having a U / D counter which outputs an output that is up or down for each frame depending on a level to the variable gain amplifier as the control signal. Correction method.