JPH0761031B2 - Digital automatic hybrid circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an automatic hybrid circuit, more specifically, a bidirectional signal line (two lines) and a unidirectional signal line used in a transmission system for telephone voice and the like. It relates to a circuit that removes a wraparound signal component generated from a conversion section with (4 lines),
The present invention relates to an automatic hybrid circuit suitable for stabilizing characteristics when converted to I.

[Background of the Invention]

Japanese Patent Application No. 56-59697 (Japanese Patent Application Laid-Open No. 57-174941) discloses an automatic hybrid circuit which replaces the conventional 4-wire and 2-wire converter using a hybrid transformer and responds to impedance fluctuations on the 2-wire side. As described above, an automatic hybrid circuit using an analog method using a switch capacitor has been proposed. In the automatic hybrid circuit, since a plurality of balanced filters are required according to the fluctuation of the line impedance on the two-wire side, conventionally, a coefficient group of a plurality of filters has been realized by switching capacitors. However, in this case, it is difficult to realize a desired filter characteristic in a small size and stably due to the characteristic variation of the operational amplifier and the manufacturing variation of the capacitor. Further, an operational amplifier and a voltage comparator are also required in the decision circuit for selecting the optimum filter, but in order to improve the sensitivity of the decision circuit, the offset and dead band width of the operational amplifier and the voltage comparator itself are set. Must be small. Furthermore, since the output of the filter circuit becomes a noise source for the signal to be transmitted from the 2nd wire side to the 4th wire side, in order to prevent the characteristics of the transmitter from deteriorating, the S / N ratio and power supply noise immunity (PSRR) characteristics must be improved. Therefore, in the above automatic hybrid circuit, by increasing the absolute value of the capacitor and the driving force of the operational amplifier,
I tried to suppress the effects of S noise, clock feedthrough, stray capacitance, etc. However, as a result, the chip size and power consumption increase. Also, regarding the applicability of the micro LSI manufacturing process, not only the S / N characteristics deteriorate due to the reduction of the dynamic range due to the reduction of the withstand voltage of the device, but also the PSRR, the MOS noise countermeasure, the offset and the dead zone are reduced. As a countermeasure, the MOS size cannot be reduced, and it is difficult to take advantage of the fine process.

[Object of the Invention]

An object of the present invention is to solve the above-mentioned drawbacks and to provide a digital automatic hybrid circuit to which a fine LSI process can be applied.

[Outline of Invention]

In order to achieve the above object, the present invention arranges a digital filter having a variable transfer function between the 4-wire digital signal input / output lines, and compares the output signal level of the filter with the signal level of the 4-wire digital signal output line. However, at the same time as selecting a filter that is most suitable for the transfer characteristics on the 2-wire side, the presence or absence of an input signal from the 2-wire type is detected, and the operation of the above-mentioned comparison determination is controlled accordingly.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a digital automatic hybrid circuit according to the present invention. In the figure, 4-wire digital signal input line 101, 4-wire digital signal output line 1
02, a 2-wire 4-wire connection point 115 is formed between the terminal and the 2-wire signal line to which the telephone 111 is connected. The input signal of the 4-wire digital signal input line 101 is supplied to the 2-wire side via the D / A converter 108, the terminating impedance 110, and the coupling point 115. At the same time, the input signals of the 4-wire digital signal input line 101 are connected in parallel to a plurality of balanced filter circuits (112-1 to 112-N).
Is supplied to. 4 lines analog signal input line 1 from junction point 115
The signal supplied via 16 is supplied to the subtractors 103 and 104 through the A / D converter 109.

The first input terminal of the subtractor 103 has a switch group (113-1 to 11-3
113-N) through the balanced filter circuits (112-1 to 11-11).
2-N), and the first input terminal of the subtractor 104 is also connected to the filter circuit via the other switch groups (114-1 to 114-N). The outputs of the two subtraction circuits are applied to the decision circuit 105 and drive the switch groups so as to perform the operation described below. The output 102 of the subtractor 103 is finally supplied to the transmission line as a 4-line digital output signal of the hybrid circuit.

Now, in the above-mentioned configuration, 2 from the 2 line-4 line connecting point 115
The impedance viewed from the line side is Z _L , the 4-wire digital input signal voltage is V _IN , the transfer functions of the D / A converter 108 and A / D converter 109 are HD _{/ A} , _{HA / D} , and 4-wire, respectively. The output of the A / D converter 109 when V _out ′ and V _out ′ are input to the analog voltage which is generated at the 2-wire-4 wire connection point 115 by the digital signal input and becomes the 4-wire analog signal input V _out V _out = H _{A / D} · V _out ′. Therefore, if a voltage equal to the above voltage V _out is separately generated and subtracted at the 4-wire digital signal output side, an undesired wraparound component from the 4-wire digital input signal does not occur at the 4-wire digital signal output line side. It will be.

So, to make the voltage of V _out for correction, It is sufficient to provide a circuit (filter) having 4 lines between the 4-line digital signal input / output lines. Here, W represents a frequency. The balanced filter circuits 112-1 to 112-N are digital circuits having these transfer functions and correspond to N kinds of two-wire side impedances. The selection of the circuit having the optimum characteristics among these plural filters is performed as follows. First 113 of the switch group (113-1 to 113-N, 114-1 to 114-N)
-1 and 114-2 are closed, and filter circuits 112-1 and 112-
Select 2. These output signals are subtracted from the output signal of the A / D converter 109 using subtractors 103 and 104, respectively,
The determination circuit 105 determines the magnitude of the average voltage of the output voltage. In this case, the filter circuit with the lower average voltage suppresses the sneak signal more.

Therefore, when the average voltage of the output of the subtractor 103 is lower, the switch 113-1 is turned on, the switch 114-2 is turned off, and the switch 114-3 is turned on instead to perform the next comparison. .
On the other hand, when the average voltage of the output of the subtractor 104 is low, the switch 113-1 is turned off, 113-2 is turned on instead, 114-
2 is turned off and 114-3 is turned on instead, and the following comparison is performed.

As described above, the switch group (113-1 to 113-N) is used as a subtractor.
103 A balanced filter circuit is selected so that the average voltage of the output signal is low, and the switch group (114-1 to 114-N)
If the filter circuits are shifted one by one and compared, the optimum filter can be selected by N-1 comparison operations even in the worst case.

The speaker recognition circuit 106 detects the call signal level from the near-end speaker (the speaker talking on the telephone 111) and stops the operation of the determination circuit 105 when it is higher than the 4-wire digital input level. is there. This is the signal from the near-end speaker,
This is because if the 4-wire digital signal input is present at the same time, the signal from the 4-wire input side and the signal from the 2-wire side overlap with the judging circuit, and the judging circuit malfunctions. That is, since the determination circuit 105 compares the voltage average values of the two inputs, it can be configured to rectify the two inputs, obtain an absolute value, integrate the difference between them, and determine whether the integrated value is positive or negative. on the other hand,
A signal from the 2 wire side is A, 4 from the 4 wire digital signal input
Let B be the sneak into the line digital signal output, and C and D be the two filter outputs connected to the first input terminals of the two subtractors 103 and 104. Is | A + B−C | − | A + B−D |, and therefore this does not generally equal the value | B−C | − | B−D | desired to be compared, which causes a malfunction. A block 107 is a timing generation circuit that supplies a timing signal necessary for the determination circuit, the filter circuit, the speaker recognition circuit, etc., but the wiring is not shown for the sake of simplicity.

FIG. 2 shows an embodiment of the speaker recognition circuit.
Reference numeral 101 is a 4-line digital signal input, and 102 is a 4-line digital signal output. If the signal from the near-end speaker is small,
The signal appearing in the 4-wire digital signal output is mainly the already-suppressed wraparound component from the 4-wire digital signal input, and its voltage average value is small compared to the 4-wire digital signal input level. However, when a near-end talker signal is present and its level is equal to or higher than the 4-wire digital signal input level, this voltage appears at the 4-wire digital signal output, so the voltage average value is the voltage of the 4-wire digital signal input. It will be larger than the average value. Therefore, comparing the voltage average values of the 4-wire digital signal input and 4-wire digital signal output,
Near-end speakers can be detected. In FIG. 2, 20
Reference numeral 3,204 is a rectifier, and the difference between the outputs is taken by a subtractor 205, an adder 206, a shift register 207, an attenuator 210.
After being integrated by the integrator configured by, the speaker recognition can be performed according to the above-described principle by determining whether the sign is positive or negative. Here, the attenuators 209 and 210 are for adjusting the sensitivity.

FIG. 3 shows an embodiment of the decision circuit. 301,
302 is the output of each of the subtracters 103 and 104 in FIG. 1, and 303 is the output of the speaker recognition circuit. Input signals 301 and 302 are rectifier 3 respectively
After passing through 04 and 305, the level difference is detected by the subtractor 306, and then integrated by the integrating circuit composed of the adder 307 and the shift register 308. The first digital comparator 309 is high when the output (V ₁ ) of the integrator circuit is V ₁ > V _TH1 or V ₁ <−V _TH1 with respect to two threshold values (+ V _TH1 , −V _TH1 ). The level (hereinafter "H") is output. Second digital comparator 311
Outputs "H" only when the output of the counter 310 is larger than the threshold value V _TH2 after a predetermined time even when the output of the first comparator is "L". Also, the third digital comparator 313 outputs "H" only when the output of the adder 307 is larger than the threshold value V _TH3 . The output of the OR circuit 312 of the detection circuit 314 is “H”.
Control signal 3 depending on the output of digital comparator 313
16,317 are generated, and the switch group (113-1 to 113- of FIG. 1 is generated.
N, 114-1 to 114-N). That is, the outputs 316 and 317 of the detection circuit 314 are the switches 113-1 and 114 shown in FIG.
-2 is on, and when the output of the comparator 313 is "H", the switches 113-1 and 114-3 are turned on. Conversely, when the output of the comparator 313 is "L" Switch 1
It is output so that 13-2 and 114-3 are turned on. At this time, at the same time, the output signal 315 causes the register 308 and the counter 31 to
The contents of 0 are reset and the next integration and counting is started. However, at this time, when the output of the speaker recognition circuit is “H”, that is, when the call signal from the near-end speaker is present, the detection circuit 314 determines how the outputs of the OR circuit 312 and the comparator 313 are output. Nevertheless, the current state (according to the above example, only the switch groups 113-1 and 114-2 in FIG. 1 are turned on) is maintained. In the above, three thresholds are used for the following purposes. First, V _TH2 is a value that determines the maximum time required for comparison and determination of a pair of balanced filter circuits. However, depending on the combination of the filter circuits, the output of the subtractor 306 in FIG. 3 may become large, and at this time, the comparison determination time can be shortened by V _TH1 . V _TH3 is a value for giving judgment circuit hysteresis. That is,
If the line condition on the two-wire side is a property near the middle of the two filter properties that are happening to be compared, no difference will occur in the determination result, so the two filter circuits are alternately or irregularly selected and switched. As a result, noise may be generated and output at each switching.
However, if a relatively large difference does not occur by providing the third threshold value, it is possible to prevent the unnecessary noise generation by keeping the switching state up to the previous time. Although the rectifiers 304 and 305 are used in the embodiment shown in FIG. 3, as means for improving the sensitivity,
These may be replaced with a two-shaped circuit.

FIG. 4 shows another embodiment of the decision circuit. Rectifier 4 with high-pass filters 418 and 419 that remove the AC induction component and pass only the audio signal.
It is added before the 04,405. In practical use, this may cause a 50/60 Hz AC induction component to be superimposed on the 2-wire-4 wire coupling point 115 and 4-wire analog input signal of FIG. 1, and as a result, the speaker recognition circuit and the determination circuit. Is to prevent the malfunction. In this case, the input 102 of the speaker recognition circuit shown in FIG. 2 becomes the output signal 420 shown in FIG.

FIG. 5 shows an example of the construction of the balanced filter circuit. 501 is an input, 502 is an output, 503 is an adder, 504, 505 and 507 are shift registers, 506 is a multiplier, 509-1 to 509-2, 510-1 to 51
0-4,511-1 to 511-2, 513-1 to 513-5, 514 are switches. Since this operation is described in detail in Japanese Patent Application No. 58-217715, its explanation is omitted here. Where multiplier 50
The coefficients (a ₁ , a ₂ , b ₁ , b ₂ ) input to 6 are N kinds (for example, (a _1-1 , a _2-1 , b _1-1 , b _2-1 ) to (a _{1- N} , a _2-N , b _1-N , b _2-N ) prepared and each coefficient described above (FIG. 3 or 4)
N types of filter circuits are realized by switching according to the output of. Therefore, in order to facilitate the explanation of the circuit operation in the embodiment shown in FIG. 1, an example in which the filter circuits are arranged in multiple parallels is shown. However, in actuality, as shown in FIG. By switching, it is possible to perform the same function as the plurality of filters in FIG.

An embodiment of a hybrid circuit using the filter shown in FIG. 5 is shown in FIG. Only parts different from the embodiment shown in FIG. 1 will be described. Filter 612-1,6
Reference numeral 12-2 is a filter in which each coefficient shown in FIG. 5 is variable according to a control signal from the judgment circuit 605. The outputs of this filter are switches 613-1 to 613-2, 614-1 to 6-6.
It is connected to the subtracters 603 and 604 via 14-2. If the filters 612-1 to 612-2 have N kinds of characteristics (H _{1 to} H _N ) according to the control signal, the operation of this hybrid circuit is as follows.

(1) Switches 613-1 to 613-2 are turned on, 614-1 to 614
-2 is turned off, and the characteristics of the filter 612-1 are set to H _i , 612-2
Compare the characteristics of as H _j .

(2) When the return loss of the filter 612-1 is better, the characteristics of the filter 612-1 are set as H _{j + 1} and compared.

(3) When the return loss of the filter 612-2 is better, the switches 613-1 to 613-2 are turned off, and the switches 614-1 to 614 are turned off.
-2 is turned on so that the subtractor 603 connected to the 4-wire output 602 is connected to a filter having a good return loss. Further, the characteristics of the filter 612-1 are set to H _{j + 1} for comparison.

(4) Switches 613-1 to 613-2 are off, 614-1 to 614
Similarly, when the comparison is performed with -2 turned on, the optimum filter can be finally selected by controlling the subtracter 603 so that a filter having a good return loss is connected.

When the characteristics of the filter are switched, the transient response of the filter may become noise.
Since the filter to which a sufficient amount of time has passed after the characteristics are constantly switched is connected to 603, noise due to a transient response can be suppressed.

〔The invention's effect〕

According to the present invention, since the automatic hybrid circuit can be expressed by a digital circuit, the S / N ratio and PSR which are problems in the past are
Not only can R be easily improved, it is also stable with respect to manufacturing variations and aging. Further, since it can be easily applied to a fine process, the chip area can be reduced and the power consumption can be reduced.

[Brief description of drawings]

1 and 6 are block diagrams of an embodiment of a digital automatic hybrid circuit according to the present invention, FIG. 2 is a block diagram of an embodiment of a speaker recognition circuit, and FIGS. 3 and 4 are a judgment circuit. FIG. 5 is a configuration diagram of an embodiment, and FIG. 5 is a configuration diagram of an embodiment of the filter circuit. 101: 4-line digital signal input line, 102: 4-line digital signal output line, 103, 104 ... Subtractor, 105 ... Judgment circuit, 106 ... Speaker recognition circuit, 107 ... Timing generation circuit, 108 ... D / A converter, 109 ... A / D converter, 110 ... Termination impedance, 111 ... Telephone, 112 ... Filter circuit, 113, 114 ... Switch group, 115 ... Junction point, 203, 204
...... Rectifier, 205 …… Subtractor, 206 …… Adder, 207 ……
Shift register, 209, 210 ... Attenuator, 304, 305 ...
… Rectifier, 308 …… Shift register, 310 …… Counter,
309,311,313 …… Digital comparator, 314 …… Detection circuit,
418,419 …… High-pass filter.

Claims (2)

[Claims] 1. A D / A converter for converting a digital signal input from a 4-line digital signal input line into an analog signal and outputting the analog signal to a first 4-line analog signal line, and a second 4-line analog. An A / D converter for converting an analog signal input from a signal line into a digital signal; a coupling circuit for coupling the first and second four-wire analog signal lines to a two-wire line; A filter group connected to the 4-wire digital signal input line, a selection means for selecting two filters from the filter group, and one selected filter output from the output of the A / D converter. Subtraction, a first subtractor for outputting to the 4-wire digital signal output line, a second subtractor for subtracting the output of the other selected filter from the output of the A / D converter, and one end Output of the first subtractor Side first high-pass filter, a second high-pass filter one end of which is connected to the output side of the second subtractor, the first and second high-pass filter For comparing the output signals from the other ends of the wave filters and controlling the selecting means so as to minimize the amount of signal sneak from the 4-wire digital signal input line to the 4-wire digital signal output line. From the judgment circuit and the absolute value of the output signal of the first high-pass filter,
A speaker that integrates a value obtained by subtracting the absolute value of the input signal from the line digital signal input line, suppresses the operation of the determination circuit when the integrated output is positive, and holds the filter at that time. And a recognition circuit, wherein the determination circuit has an absolute value of each output of the first and second high-pass filters or 2
A first integrator that receives the difference of the power values, a counter that is driven by a clock with a predetermined cycle, and the absolute value of the output of the first integrator is the first threshold value (V _TH1 ).
When the above is reached, or when the output of the counter reaches or exceeds the second threshold value (V _TH2 ), the magnitude relation between the output of the first integrator and the third threshold value (V _TH3 ). In response to the,
Means for generating a control signal to be supplied to the filter selecting means and resetting the counter, and a digital automatic hybrid circuit. 2. The digital automatic hybrid circuit according to claim 1, wherein the filter group comprises a variable coefficient filter circuit in which a combination of coefficients is changed by an output of the judgment circuit.