JPH0758711B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0758711B2 JPH0758711B2 JP31958892A JP31958892A JPH0758711B2 JP H0758711 B2 JPH0758711 B2 JP H0758711B2 JP 31958892 A JP31958892 A JP 31958892A JP 31958892 A JP31958892 A JP 31958892A JP H0758711 B2 JPH0758711 B2 JP H0758711B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- barrier pad
- wiring
- barrier
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半田を用いて半導体チ
ップをケース又は基板に電気的に接続させる半導体装置
（以下、クリップチップという）の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device (hereinafter referred to as a clip chip) for electrically connecting a semiconductor chip to a case or a substrate by using solder.
【０００２】[0002]
【従来の技術】従来のクリップチップにおける半田と配
線コンタクトの位置関係は、半田と配線材料（Ａｌ，Ａ
ｕ等）との反応を抑制するバリアパッド（Ｎｉ，Ｃｕ
等）を挾んだ状態にある。さらに、半田領域と配線コン
タクト領域とは、同一の領域にあった。2. Description of the Related Art The positional relationship between solder and wiring contacts in a conventional clip chip is as follows.
barrier pad (Ni, Cu) that suppresses the reaction with
Etc.) is in a state of being sandwiched. Further, the solder area and the wiring contact area were in the same area.
【０００３】したがって、半田と配線との間の距離は、
バリアパッドの膜厚と同一であった。Therefore, the distance between the solder and the wiring is
It was the same as the film thickness of the barrier pad.
【０００４】例えば、Ｎｉからなるバリアパッドの厚さ
が５μｍであった場合には、半導体チップの使用時の温
度が１２０℃であれば、約２．５年を経過した時点でＮ
ｉのバリアパッドと半田は溶融してしまう。一方、半導
体チップの使用時の温度が７０℃であれば、４００年程
度の耐久性がある。したがって、使用温度１２０℃の集
積回路であれば、４０年の耐久性を得るためには、Ｎｉ
からなるバリアパッドの厚さは、８０μｍとなる。For example, when the thickness of the barrier pad made of Ni is 5 μm, if the temperature when the semiconductor chip is in use is 120 ° C., N is reached after about 2.5 years have passed.
The i barrier pad and the solder melt. On the other hand, if the semiconductor chip is used at a temperature of 70 ° C., it has durability of about 400 years. Therefore, in the case of an integrated circuit with a working temperature of 120 ° C, in order to obtain 40-year durability, Ni
The thickness of the barrier pad made of is 80 μm.
【０００５】[0005]
【発明が解決しようとする課題】現在、半田に対するバ
リアパッドとしては、前述のようにＮｉ，Ｃｕ等の金属
が主に使用されているが、そのバリア性は不完全であ
り、熱と時間によってバリアパッドは、半田に侵食され
ていく。At present, metals such as Ni and Cu are mainly used as a barrier pad against solder as described above, but the barrier property is incomplete and it depends on heat and time. The barrier pad is eroded by the solder.
【０００６】したがって、従来の構造では、半田を形成
した後の温度及び耐用時間を考え、信頼性上問題がない
ようにバリアパッドの厚さを厚くする必要がある。Therefore, in the conventional structure, it is necessary to increase the thickness of the barrier pad in consideration of the temperature and the service life after forming the solder so that there is no problem in reliability.
【０００７】しかし、例えばＮｉはめっきすると、スト
レスが入りやすく、５μｍ以上の厚さでは、下層との間
に剥がれが生じてしまい、使用温度を低くすることで信
頼性を確保する必要があった。However, for example, when Ni is plated, stress is likely to occur, and when the thickness is 5 μm or more, peeling occurs between the Ni and the lower layer, and it is necessary to secure reliability by lowering the operating temperature. .
【０００８】また、バリアパッドの形成時にピンポール
（バリアパッドの厚さが極所的に非常に薄くなる）がで
きると、その部分から半田が浸透し、信頼性が低下する
という問題があった。Further, if a pin pole (the thickness of the barrier pad is extremely thin locally) is formed at the time of forming the barrier pad, there is a problem that solder penetrates from that portion and reliability is lowered.
【０００９】また、バリアパッドの形成後、チップの電
気的探針チェックによる加圧でバリアパッドにキズ及び
クラックが入った時にも、同じように半田の浸透を起こ
し、信頼性が低下するという問題があった。Also, after the barrier pad is formed, even if the barrier pad is scratched or cracked due to the pressure applied by the electrical probe check of the chip, the solder similarly penetrates and the reliability is lowered. was there.
【００１０】以上のような問題は、配線にＡｕを用いた
場合、特に顕著となり、半田とＡｕが体積膨張すること
により、配線上の絶縁物を押し上げて絶縁物にクラック
を生じさせ信頼性が低下する。The above problem becomes particularly noticeable when Au is used for the wiring, and the volume expansion of the solder and Au pushes up the insulating material on the wiring to cause cracks in the insulating material, resulting in a high reliability. descend.
【００１１】本発明の目的は、配線と半田との反応を防
止するバリアパッドの耐熱性，信頼性を向上させた半導
体装置の構造を提供することにある。An object of the present invention is to provide a structure of a semiconductor device in which the heat resistance and reliability of a barrier pad for preventing the reaction between wiring and solder are improved.
【００１２】[0012]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路装置は、半田を用いて
半導体チップをケース又は基板に電気的に接続し、半田
と半導体チップの配線層間にバリア金属で形成されるバ
リアパッドを有する半導体集積回路装置であって、バリ
アパッドは、相互に導通した配線コンタクト領域と半田
領域とを有し、配線コンタクト領域は、半導体チップの
配線層に接続され、半田領域は、半田が融着されるもの
であり、配線コンタクト領域と半田領域とは、導通を保
ったまま横方向に距離をあけて設けられたものである。In order to achieve the above object, a semiconductor integrated circuit device according to the present invention uses a solder to electrically connect a semiconductor chip to a case or a substrate, and A semiconductor integrated circuit device having a barrier pad formed of a barrier metal in the barrier pad, the barrier pad having a wiring contact region and a solder region which are electrically connected to each other, and the wiring contact region is connected to a wiring layer of a semiconductor chip. The solder region is where the solder is fused, and the wiring contact region and the solder region are provided with a distance in the lateral direction while maintaining electrical continuity.
【００１３】[0013]
【作用】バリアパッドに設けられる配線コンタクト領域
と半田形成領域とを離して設けられている。このため、
両領域間の距離を調整することにより、バリアパッドの
厚さが厚くなったと同じ耐熱性を得ることが可能とな
る。Function: The wiring contact region provided on the barrier pad is separated from the solder formation region. For this reason,
By adjusting the distance between both regions, it is possible to obtain the same heat resistance as the thickness of the barrier pad is increased.
【００１４】[0014]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【００１５】（実施例１）図１（ａ）は、本発明の実施
例１を示す平面図、（ｂ）は（ａ）のＡ−Ａ’線断面図
である。(Embodiment 1) FIG. 1A is a plan view showing Embodiment 1 of the present invention, and FIG. 1B is a sectional view taken along the line AA 'of FIG.
【００１６】図１において、バリア金属で形成されるバ
リアパッド３は絶縁膜６上に形成され、しかも配線１と
のコンタクト領域から横方向に延びてポリイミド７から
露出した領域には、酸化防止のための金パッド４が形成
されている。半田は、金パッド４上に形成させる。金パ
ッド４は、半田を熱融着させると、半田中に溶融してし
まい、半田付けした後、金パット４はなくなり、半田と
バリアパッド３とが融着する。In FIG. 1, a barrier pad 3 made of a barrier metal is formed on the insulating film 6, and a region extending laterally from a contact region with the wiring 1 and exposed from the polyimide 7 is provided with an antioxidation property. The gold pad 4 for forming is formed. The solder is formed on the gold pad 4. The gold pad 4 is melted in the solder when the solder is heat-sealed, and after soldering, the gold pad 4 disappears and the solder and the barrier pad 3 are melt-bonded.
【００１７】電解めっき用電極としてのめっき電極５
は、下層がＴｉとＷの合金（以後、ＴｉＷと称す）、上
層がＣｕとなる２層構造であり、ＴｉＷ及びＣｕが２０
０オングストロームの厚さでスパッターにより形成され
ている。Plating electrode 5 as electrode for electrolytic plating
Has a two-layer structure in which the lower layer is an alloy of Ti and W (hereinafter referred to as TiW) and the upper layer is Cu.
It is formed by sputtering with a thickness of 0 angstrom.
【００１８】ＴｉＷ，Ｃｕともに半田に対する反応は、
Ｎｉ程度であり、バリアパッドとしての性質は備えてい
る。しかしながら、ＴｉＷはめっき形成できず、Ｃｕは
カバーとして使用するポリイミド７との密着性が悪いた
め、ＴｉＷとＣｕは、薄くしか形成できず、厚いバリア
パッドは、Ｎｉが主体となる。The reaction of both TiW and Cu with respect to solder is
It is about Ni and has a property as a barrier pad. However, since TiW cannot be formed by plating and Cu has poor adhesion to the polyimide 7 used as the cover, TiW and Cu can be formed only thinly, and a thick barrier pad is mainly made of Ni.
【００１９】本発明では、図１のようにバリアパッド３
は、配線１に接続される配線コンタクト２と、半田が熱
融着される金パッド４（半田形成領域）とは、横方向に
距離ｌだけ離れており、距離ｌは、必要な耐熱温度及び
集積回路の耐用年数から自由に設定でき、バリアパッド
３の厚さも、電気抵抗のみを考えて使用時に問題となら
ない程度の厚みとすれば良い。ここでは、距離ｌを２７
μｍとし、バリアパッド３の厚みを５μｍとしている。In the present invention, as shown in FIG. 1, the barrier pad 3
Is laterally separated from the wiring contact 2 connected to the wiring 1 and the gold pad 4 (solder forming region) on which the solder is heat-sealed, and the distance 1 is the required heat resistant temperature and It can be set freely depending on the service life of the integrated circuit, and the thickness of the barrier pad 3 may be set to a thickness that does not pose a problem in use in consideration of only electric resistance. Here, the distance l is 27
The barrier pad 3 has a thickness of 5 μm.
【００２０】これにより、バリアパッド３のバリア性
は、集積チップが１２０℃の使用温度でも、半田が配線
コンタクト２まで達するのに１３年以上かかることにな
る。As a result, the barrier property of the barrier pad 3 requires 13 years or more for the solder to reach the wiring contact 2 even when the integrated chip is used at a temperature of 120 ° C.
【００２１】また、配線コンタクト１上に半田を熱融着
しないため、バリアパッド３を形成する時にピンホール
が生じても、このピンホールを通して半田が配線１まで
浸透することはない。また、バリアパッド３の形成後、
半導体チップの電気的探針チェックによる加圧でバリア
パッド３にキズ及びクラックが入った時にも、半田の浸
透を起こさない。Further, since the solder is not thermally fused onto the wiring contact 1, even if a pinhole is formed when the barrier pad 3 is formed, the solder does not penetrate to the wiring 1 through the pinhole. In addition, after forming the barrier pad 3,
Even if the barrier pad 3 is damaged or cracked by the pressure applied by the electrical probe check of the semiconductor chip, the penetration of the solder does not occur.
【００２２】（実施例２）図２は、本発明の実施例２を
示す平面図である。図２において、バリアパッド３は、
ポリイミド７の下部に設けられるが、理解易りやすくす
るため、実線で示してある。(Embodiment 2) FIG. 2 is a plan view showing Embodiment 2 of the present invention. In FIG. 2, the barrier pad 3 is
Although it is provided below the polyimide 7, it is shown by a solid line for easy understanding.
【００２３】本実施例では、バリアパッド３は、配線１
上を通過し、同電位とすべき３本の配線１とコンタクト
している。In this embodiment, the barrier pad 3 is the wiring 1
It passes over and is in contact with three wirings 1 that should be at the same potential.
【００２４】本実施例では、バリアパッド３の金パッド
４と配線コンタクト２とが離れて設けられ、バリアパッ
ド３が配線層と同様に横方向に長さをもつ構造であるた
め、バリアパッド３による電位降下が集積回路上問題と
ならない限り、バリアパッド３を配線層として使用する
ことができ、設計の自由度を大幅に向上させることがで
きるという利点を有する。In this embodiment, the gold pad 4 of the barrier pad 3 and the wiring contact 2 are provided separately from each other, and the barrier pad 3 has a lateral length similar to the wiring layer. The barrier pad 3 can be used as a wiring layer as long as the potential drop due to (1) does not pose a problem in the integrated circuit, and the degree of freedom in design can be greatly improved.
【００２５】[0025]
【発明の効果】以上説明したように本発明は、バリアパ
ッドの配線コンタクト領域と、半田を形成する領域とが
横方向に離して設けてあるため、バリア金属としてのバ
リアパッドの厚みを厚くしたと同様に耐熱性を得ること
ができる。As described above, according to the present invention, since the wiring contact region of the barrier pad and the region for forming the solder are provided laterally separated from each other, the thickness of the barrier pad as the barrier metal is increased. Heat resistance can be obtained in the same manner as in.
【００２６】さらに、バリアパッド形成時のピンホール
及びＰ／Ｗによるバリアパッドのキズ，クラックは、バ
リアパッドの表面に対し垂直に入るため、配線コンタク
トと半田形成領域がずれていると、半田の浸透を起こさ
ず、信頼性が高くなる。Further, pinholes and scratches and cracks on the barrier pad due to P / W at the time of forming the barrier pad enter perpendicularly to the surface of the barrier pad. It does not penetrate and is highly reliable.
【図１】（ａ）は本発明の実施例１を示す平面図、
（ｂ）は（ａ）のＡ−Ａ’線断面図である。1A is a plan view showing a first embodiment of the present invention, FIG.
(B) is a sectional view taken along the line AA ′ of (a).
【図２】本発明の実施例２を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.
１ 配線 ２ 配線コンタクト ３ バリアパッド ４ 金パッド ５ めっき電極 1 Wiring 2 Wiring contact 3 Barrier pad 4 Gold pad 5 Plating electrode
Claims (1)
基板に電気的に接続し、半田と半導体チップの配線層間
にバリア金属で形成されるバリアパッドを有する半導体
集積回路装置であって、 バリアパッドは、相互に導通した配線コンタクト領域と
半田領域とを有し、 配線コンタクト領域は、半導体チップの配線層に接続さ
れ、半田領域は、半田が融着されるものであり、 配線コンタクト領域と半田領域とは、導通を保ったまま
横方向に距離をあけて設けられたものであることを特徴
とする半導体集積回路装置。1. A semiconductor integrated circuit device comprising: a semiconductor chip electrically connected to a case or a substrate using solder; and a barrier pad formed of a barrier metal between wiring layers of the solder and the semiconductor chip. Has a wiring contact region and a solder region which are electrically connected to each other, the wiring contact region is connected to the wiring layer of the semiconductor chip, and the solder region is a region where the solder is fused. A region is a semiconductor integrated circuit device characterized in that it is provided with a distance in the lateral direction while maintaining electrical continuity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31958892A JPH0758711B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31958892A JPH0758711B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06168947A JPH06168947A (en) | 1994-06-14 |
| JPH0758711B2 true JPH0758711B2 (en) | 1995-06-21 |
Family
ID=18111947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31958892A Expired - Fee Related JPH0758711B2 (en) | 1992-11-30 | 1992-11-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758711B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100438256B1 (en) * | 1995-12-18 | 2004-08-25 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and manufacturing method |
| JP5424747B2 (en) | 2009-07-06 | 2014-02-26 | ラピスセミコンダクタ株式会社 | Semiconductor device |
-
1992
- 1992-11-30 JP JP31958892A patent/JPH0758711B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06168947A (en) | 1994-06-14 |
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