JPH0757485A - Erasing method for semiconductor memory - Google Patents
Erasing method for semiconductor memoryInfo
- Publication number
- JPH0757485A JPH0757485A JP20501293A JP20501293A JPH0757485A JP H0757485 A JPH0757485 A JP H0757485A JP 20501293 A JP20501293 A JP 20501293A JP 20501293 A JP20501293 A JP 20501293A JP H0757485 A JPH0757485 A JP H0757485A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- terminal
- erasing
- cell
- source terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体記憶装置特にス
タック型電気的一括消去型ＥＥＰＲＯＭの消去方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of erasing a semiconductor memory device, particularly a stack type electrical collective erasing type EEPROM.
【０００２】[0002]
【従来の技術】従来の、スタック型電気的一括消去型Ｅ
ＥＰＲＯＭの消去方法について、図２を用いて説明す
る。まず全セルあるいは任意のセクターを一括して過剰
消去状態にするためにソース端子に高電圧を印加し、も
しくは、ゲート端子に高電圧を、またソース端子に低電
圧をそれぞれ印加して消去した後、次に過剰消去でばら
ついたセルのしきい値電圧を収束させるために、ドレイ
ン端子あるいはソース端子に電源電圧程度のストレス電
圧を印加するという方法が報告されている。2. Description of the Related Art A conventional stack type electrical collective erasing type E
A method of erasing the EPROM will be described with reference to FIG. First, a high voltage is applied to the source terminal to erase all cells or an arbitrary sector at once in an over-erased state, or a high voltage is applied to the gate terminal and a low voltage is applied to the source terminal. Then, in order to converge the threshold voltage of a cell which has varied due to overerasure, a method of applying a stress voltage of about the power supply voltage to the drain terminal or the source terminal has been reported.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、前記従
来の消去方法では、消去後のしきい値電圧は収束するも
のの、消去時にメモリセルに与えるダメージが大きい。
また、書き込み消去サイクルを繰り返すにつれて次第に
メモリセル特性が劣化していき、読み出し時のセル電流
が小さくなっていく。同時に、ゲート電圧０Ｖ時のソー
ス・ドレイン間のリーク電流が増大し、低電圧での読み
出し特性に支障をきたす。However, in the conventional erasing method, although the threshold voltage after erasing converges, the damage to the memory cell during erasing is large.
Further, as the write / erase cycle is repeated, the memory cell characteristics gradually deteriorate, and the cell current at the time of reading becomes smaller. At the same time, the leak current between the source and the drain when the gate voltage is 0 V increases, and the read characteristic at low voltage is hindered.
【０００４】本発明は、上記課題を解決するもので、消
去後のしきい値電圧の収束性を保ちつつ、書き込み消去
サイクル時の特性劣化も防ぐことができる消去方法を提
供することを目的とする。An object of the present invention is to solve the above problems and to provide an erasing method capable of preventing the deterioration of characteristics during a write / erase cycle while maintaining the convergence of the threshold voltage after erasing. To do.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するために、本発明の半導体記憶装置は、ソース端子に
高電圧を印加し、もしくは、ゲート端子に高電圧を、ま
たソース端子に低電圧をそれぞれ印加して、過剰消去状
態にした後、ドレインあるいは前記ソース端子に電源電
圧程度の電圧を印加し、その後前記ゲート端子に所定の
電圧を印加する。To achieve the above object, the present invention provides a semiconductor memory device of the present invention in which a high voltage is applied to a source terminal, or a high voltage is applied to a gate terminal and a source terminal is applied. After a low voltage is applied to each of them to make an over-erased state, a voltage of about the power supply voltage is applied to the drain or the source terminal, and then a predetermined voltage is applied to the gate terminal.
【０００６】[0006]
【作用】本発明は、上記した消去方法を採用することに
より、過剰消去後、ドレインまたはソースに電圧を印加
して、しきい値電圧を収束させたときに発生する、トン
ネル酸化膜中への正孔のトラップを防ぎ、書き込み消去
サイクルを繰り返した後もセルの読み出し特性の劣化を
最小限に抑えることができる。According to the present invention, by adopting the above-mentioned erasing method, after the excessive erasing, a voltage is applied to the drain or the source to converge the threshold voltage, which is generated in the tunnel oxide film. It is possible to prevent holes from being trapped and minimize deterioration of the read characteristics of the cell even after repeating the write / erase cycle.
【０００７】[0007]
【実施例】以下本発明の一実施例について図面を参照し
ながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【０００８】図１は、本発明の第一の実施例の消去シー
ケンスを示したものである。この消去シーケンスについ
て、順を追って説明する。まず、全セルあるいは任意の
セクターを一括して過剰消去状態にするために、ソース
端子に約１２Ｖを印加し、ゲート端子、および基板端子
を接地し、ドレイン端子をオープン状態にそれぞれ設定
する。あるいは、ゲート端子を約−１２Ｖに、ソース端
子を約５Ｖに、基板端子を接地電位にそれぞれ保持し、
ドレイン端子をオープン状態に設定して約１秒間消去す
る。次に、過剰消去でばらついたセルのしきい値電圧を
収束させるために、ドレイン端子に約５Ｖを印加し、ソ
ース端子、ゲート端子、および基板端子を接地するか、
もしくはソース端子に約５Ｖを印加し、ドレイン端子、
ゲート端子、および基板端子を接地するかして約０.１
秒程度ドレインあるいはソースストレスを印加する。そ
して最後に、ゲート端子に約１０Ｖ（収束後のセルのし
きい値電圧が上昇しない程度の電圧）を印加し、ソー
ス、ドレイン、および基板端子を接地して約１×１０-3
秒程度のゲートストレスを印加する。FIG. 1 shows an erase sequence according to the first embodiment of the present invention. This erase sequence will be described step by step. First, about 12 V is applied to the source terminal, the gate terminal and the substrate terminal are grounded, and the drain terminal is set to an open state in order to collectively bring all cells or arbitrary sectors into an over-erased state. Alternatively, the gate terminal is kept at about -12V, the source terminal is kept at about 5V, and the substrate terminal is kept at the ground potential.
Set the drain terminal to the open state and erase for about 1 second. Next, about 5 V is applied to the drain terminal and the source terminal, the gate terminal, and the substrate terminal are grounded in order to converge the threshold voltage of the cell that has varied due to over-erasing.
Or, apply about 5V to the source terminal, drain terminal,
Approximately 0.1 by grounding the gate terminal and board terminal
Apply drain or source stress for about 2 seconds. Finally, about 10 V (a voltage that does not increase the threshold voltage of the cell after convergence) is applied to the gate terminal and the source, drain, and substrate terminals are grounded to about 1 × 10 −3.
Apply gate stress for about 2 seconds.
【０００９】[0009]
【発明の効果】本発明の消去法によれば、過剰消去後セ
ルのしきい値電圧をドレインあるいはソースにストレス
を印加することによって収束させた後、新たにゲートに
ストレスを印加することによって、トンネル酸化膜中に
トラップされた正孔を放出させることによってセルの読
み出し特性の劣化（読み出し電流の減少やゲート０Ｖ時
のソース・ドレイン間リーク電流の増大）を防ぐことが
できる。According to the erasing method of the present invention, after the threshold voltage of the cell after overerasing is converged by applying stress to the drain or source, stress is newly applied to the gate. By releasing the holes trapped in the tunnel oxide film, deterioration of read characteristics of the cell (reduction of read current and increase of source / drain leak current at 0V gate) can be prevented.
【図１】本発明の第一の実施例の消去シーケンスを示す
図FIG. 1 is a diagram showing an erase sequence according to a first embodiment of the present invention.
【図２】従来の消去シーケンスを示す図FIG. 2 is a diagram showing a conventional erase sequence.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/788 29/792 Ｈ０１Ｌ 29/78 ３７１ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371
Claims (1)
Ｍの消去シーケンスにおいて、まずソース端子に高電圧
を印加し、もしくは、ゲート端子に高電圧を、またソー
ス端子に低電圧をそれぞれ印加して、過剰消去状態にし
た後、ドレインあるいは前記ソース端子に電源電圧程度
の電圧を印加し、その後前記ゲート端子に所定の電圧を
印加することを特徴とする半導体記憶装置の消去方法。1. A stack type electrical collective erase type EEPRO
In the erase sequence of M, first, a high voltage is applied to the source terminal, or a high voltage is applied to the gate terminal and a low voltage is applied to the source terminal to make an over-erased state, and then to the drain or the source terminal. A method for erasing a semiconductor memory device, comprising applying a voltage of about the power supply voltage and then applying a predetermined voltage to the gate terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20501293A JP3206236B2 (en) | 1993-08-19 | 1993-08-19 | Erase method for semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20501293A JP3206236B2 (en) | 1993-08-19 | 1993-08-19 | Erase method for semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0757485A true JPH0757485A (en) | 1995-03-03 |
| JP3206236B2 JP3206236B2 (en) | 2001-09-10 |
Family
ID=16499992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20501293A Expired - Fee Related JP3206236B2 (en) | 1993-08-19 | 1993-08-19 | Erase method for semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3206236B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844847A (en) * | 1995-12-08 | 1998-12-01 | Nec Corporation | Method and Nonvolatile semiconductor memory for repairing over-erased cells |
| US6559500B2 (en) | 2001-03-29 | 2003-05-06 | Fujitsu Limited | Non-volatile semiconductor memory and its driving method |
-
1993
- 1993-08-19 JP JP20501293A patent/JP3206236B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844847A (en) * | 1995-12-08 | 1998-12-01 | Nec Corporation | Method and Nonvolatile semiconductor memory for repairing over-erased cells |
| US6559500B2 (en) | 2001-03-29 | 2003-05-06 | Fujitsu Limited | Non-volatile semiconductor memory and its driving method |
| US6735127B2 (en) | 2001-03-29 | 2004-05-11 | Fujitsu Limited | Method for driving a semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3206236B2 (en) | 2001-09-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |