JPH0756870A - Data mapping method - Google Patents

Abstract

PURPOSE:To provide the data mapping method capable of a high-speed inter- processing element communication. CONSTITUTION:In the data mapping method for which data provided at a virtual PE are allocated to the memory of a physical processor while making the coordinate axis of the virtual PE corresponding to the desired coordinate axis of a physical PE respectively between physical processors P (p0, ..., pN-1) and virtual processors V (v0, ..., vM-1) numbered by the pairs of coordinate values, when the virtual PE with the coordinate value of vi in a direction (i) is made correspondent to the physical PE with the coordinate value of pj in a direction (j), the virtual PE with the coordinate value of vi+1 in the direction (i) is made correspondent to the physical PE with the coordinate value of pj-1, pj or pj+1 in the direction (j) and when the coordinate value of the virtual PE in the direction (j) is increased one by one, one partial column to increase a sequence prepared by the coordinate values of the correspondent physical PE in the direction (j) one by one and one partial colulmn to decrease it one by one are respectively contained at least.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data mapping method between a virtual processor and a physical processor in a parallel computer.

[0002]

2. Description of the Related Art If a distributed memory type massively parallel computer in which a large number of high speed processing devices are arranged and operated efficiently can be expected to dramatically improve performance in scientific and technological calculations. In order to obtain the maximum performance in the distributed memory parallel computer, it is necessary to divide the calculation and minimize the communication between processing elements (hereinafter abbreviated as PE). Therefore, it is important to select a method of arranging the data in the PE that is suitable for the structure of the program.

In the field of numerical calculation, the Fortran language is widely used, and in particular, the parallel extended Fortran language is considered for a parallel computer. Figure 9
Is an example of a program by such parallel Fortran. This program defines two one-dimensional arrays A and B having a length of 20, cyclically shifts the elements of A one by one to the right and stores them in B. FO on line 70 in the figure
The RALL statement means parallel execution, and the cyclic shift of the array A and the storage of the result in the array B are executed in parallel for each element. In parallel programming, the processing shown in FIG. 9 and processing similar thereto frequently appear, which is one of the basic processing patterns.

In order to embody parallel execution by the above program, a one-dimensional virtual processor array V of length 20
(i), (i = 0, 1, ..., 19) are defined, and the array data A and B are mapped to the virtual processor array. Here, the virtual processor is a set of each divided data when the data of the program is divided by introducing the communication distance. Therefore, reference to data belonging to the same virtual processor does not require communication, so there is no cost, but reference to data belonging to a different virtual processor may require communication, which is considered to be costly. In this case, the virtual processor V (i) has array data A (i) and array data B (i), (i = 0, 1,
..., 19) are made to correspond. In the program of FIG. 9, it is convenient to consider that one-dimensional virtual processors are connected in a ring shape, that is, one-dimensional torus connection.

As a method of assigning a virtual processor to a physical processor, a cyclic division method and a block division method have been conventionally known. FIG. 10 shows an example in which the above-mentioned 20 one-dimensional torus-connected virtual processors are cyclically divided into five one-dimensional physical processors P ′ (0) to P ′ (4). Due to this division, for example, the physical processor P '(0) causes the array data A (0), A (5), A (1)
0), A (15) and B (0), B (5), B (10), B (15)
Will have.

In FIG. 10, there is no problem if the physical processors are actually one-dimensional torus coupled, but if there is no direct coupling between the physical processors P '(4) and P' (0), then P '. Communication from (4) to P '(0) is on the way to P' (3),
This is done through P '(2) and P' (1). Therefore, in this case, communication between PEs takes time.

Here, the parallel Fortran shown in FIG. 9 is used.
The program has a global namespace. That is,
The array A and the array B are defined for the entire parallel computer, and the communication between PEs is represented as a data reference and is not described explicitly. In order to execute this program on each physical processor, it must be converted into a program for data on the local memory of the physical processor, that is, a program having a local name space.
In a program having a local namespace, communication with other PEs is performed by the send function send () and the receive function recv ().
To express it explicitly.

When the program of FIG. 9 is converted according to the data mapping by the cyclic division method, the program as shown in FIG. 11 can be directly executed by the physical PE. The array assigned to each physical PE is called a local array with respect to the original global array. In FIG. 11, the local array is represented by a and b.
In the case of the physical processor P '(0), the element a of the local array
[0], a [1], a [2], a [3], b [0], b [1], b
[2] and b [3] are the elements A (0) of the global array,
A (5), A (10), A (15), B (0), B (5), B (10), B
(15) corresponds.

In order to execute the program shown in FIG. 11, the program is copied to all physical PEs and the execution is started at the same time. Each physical PE obtains the processor number by the line 71 in the figure at the beginning of the execution of the program and stores it in the variable p. Subsequent processing is slightly different depending on the value of the processor number.

For example, line 72 in the figure is data transmission from physical processor P '(p) to P' (p + 1), and line 73 is
Data is received from P '(p-1) of the physical processor P' (p). In this case, if the memory bandwidth of the physical processor is sufficiently high, or if data is directly transmitted / received to / from a register in the processor, it is possible to perform data transmission and data reception at the same time. Therefore, in line 72
The send function of returns the control without waiting for the end of the transmission, and can start executing the recv function of the line 73 which is the next data reception. From the above, the execution time of the transmission and the reception is indicated by T ′ in FIG. The inter-processor communication time T'must be made as short as possible, but in the conventional example shown here, it cannot be made any shorter.

The conventional example described above is a one-dimensional case, but the same can be said when expanded to a multi-dimensional case. Also, it is convenient to assume that periodic boundary conditions often appear in scientific and engineering calculations, especially in the problem of solving partial differential equations in two-dimensional and three-dimensional regions, and therefore interprocessor communication occurs according to a two-dimensional or three-dimensional torus connection. Often good. Alternatively, the torus connection is convenient for speeding up global operations such as calculating the sum of all elements.

As a well-known parallel computer,
There is a parallel computer in which PEs are physically connected in a two-dimensional or three-dimensional lattice form. Such a grid-connected computer is easy to implement and has high expandability. FIG. 12 is an example of a two-dimensional grid-connected parallel computer. When a torus-coupled virtual processor on such a parallel computer is mapped by the conventional cyclic mapping or block mapping method, direct PE
Communication occurs between P '(0,0) and P' (0,3) with no connection between them, and such communication occurs on P '(0,1), P' (0 , 2)
Will be done through. Generally, the communication between PEs takes longer as the distance between PEs increases. If the communication distance is long, the communication path between them is occupied, and the possibility of waiting for other communication increases. Therefore, if all the PEs try to communicate with the adjacent PEs all at once along the virtual torus connection, the communication performance is suppressed by the communication path having a long distance.

In order to solve the above problem, it is conceivable to physically connect PEs by a torus network. This method is good when the execution program uses the whole of the torus-coupled processor, but normally this condition is not satisfied. One example thereof is a case where a multi-user is realized by spatially dividing a parallel computer composed of a large number of PEs and assigning each divided parallel computer to a user. FIG. 13 shows an example in which a parallel computer 131 and a parallel computer 132, which are spatially divided, are assigned to user A and user B on a two-dimensional torus-connected parallel computer. In this case, user A has P '
If (0,3) and P '(0,0) use a torus connection to communicate, the communication message will pass through the area of another user B. This is due to the fact that the messages of different users are mixed in addition to the problem of long communication distance.
There is a possibility that wrong message communication of other users may interfere with the operation of his / her correct program. Also, it is difficult to debug a program that messages from different users are mixed and influence each other. If P '(0,3) and P' (0,0) are communicated only within their own area, the situation is the same as in the case of the grid connection network described in FIG. Then, the communication performance deteriorates depending on the communication path due to the long communication path.

[0014]

As described above, the conventional data mapping method has a problem that the communication performance deteriorates due to the communication path having a long distance. The present invention has been made in view of the above problems, and an object thereof is to provide a data mapping method that enables high-speed communication between processing elements.

[0015]

According to the present invention, a plurality of physical processors P (p are numbered by a set of N coordinate values.
₀ , p ₁ , ..., p _N-1 ) and a plurality of virtual processors V (v ₀ , v ₁ , ..., v _M-1 ) numbered by a set of M coordinate values, A data mapping method for allocating the data of the virtual processor to the memory of the physical processor by associating the N coordinate axes of the virtual processor with a desired one of the M coordinate axes of the physical processor, i. When the virtual processor whose coordinate value in the direction is v _i is associated with the physical processor whose coordinate value in the j direction is p _j , the coordinate value in the i direction is v _i
The coordinate value in the j direction of the virtual processor that is +1 is p _j −
When the coordinate value in the i direction of the virtual processor is incremented by 1 while being associated with the physical processor being 1, p _j , or p _j +1, the corresponding sequence value of the coordinate value in the j direction of the physical processor is generated. It is characterized in that at least one subsequence increasing by one and at least one subsequence decreasing by one are included.

[0016]

According to the present invention, the physical processors P (p ₀ , p ₁ , ..., P) that are not torus-coupled so as to fold the torus-coupled virtual processors V (v ₀ , v ₁ , ..., V _M-1 ). _N-1 ) allows virtual processors adjacent to each other to be allocated to adjacent physical processors or the same physical processor.

Therefore, according to the data mapping method of the present invention, there is no end-to-end large-scale connection existing on the torus connection, and the rightward communication and the leftward communication are simultaneously performed by the cyclic shift communication. PE that can be executed
Higher inter-communication is possible.

Further, according to the present invention, since communication is performed only between adjacent physical processors, when a parallel computer is spatially divided and each divided parallel computer is assigned to a different user, each user It is possible to realize an independent torus network separated from other users.

Further, according to the data mapping method of the present invention, when a program in a global namespace in which data is divided corresponding to a virtual processor is converted into a program having a local namespace which can be executed by each physical processor, A new program optimizing opportunity that is not available in the conventional block division or cyclic division is obtained, and the communication speed between PEs can be further increased.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a physical PE 1 according to the present invention.
It is a block diagram of. As shown in FIG. 1, the physical processor 1 has a memory 2, a central processing unit (hereinafter abbreviated as CPU) 4, and a physical processor 2 for communicating with other physical PEs.
Two communication ports A and B are provided.

The communication port A is composed of an input port 11 and an output port 12, and similarly, the communication port B is composed of an input port 21 and an output port 22. Inside the physical PE 1, these input ports 11 and 21 and output port 1
2 and 22 are registers or high-speed memory 1
It is connected to 3,23,14,24. Therefore, the PE of this embodiment has four input / output ports 11, 12, 1.
It is possible to simultaneously operate 3 and 14 to transfer data.

FIG. 2 is a block diagram of a parallel computer in which the physical PEs 1 are one-dimensionally connected. That is, in the embodiment of the present invention, the physical PE 1 of FIG. 1 is connected in a one-dimensional manner as shown in FIG. The input port 11 and the output port 22 of the communication port A of one physical PE are connected to the output port 22 and the input port 21 of the communication port B of the adjacent physical PE, respectively. In this embodiment, as shown in the figure,
Processing elements P (0) and P located at both ends
(4) Do not connect directly to. Therefore, the physical P of FIG.
It is easy to combine a plurality of one-dimensional parallel computers configured by using E1 to expand to a larger one-dimensional parallel computer.

Next, referring to FIG. 3, according to the data mapping method of the present invention, 20 torus-coupled (loop-shaped) one-dimensional virtual processors are connected to one-dimensional physics consisting of five physical PEs. An example of allocation to a processor is shown.

As shown in FIG. 3, first, the virtual processor V
(0) is assigned to the physical processor P (0). Next, V (1) adjacent to the virtual processor V (0) is connected to the physical processor P.
(0) Assign to adjacent P (1). Similarly, V (2) ~ V
(4) is assigned to P (2) to P (4), respectively. In the present invention, the following five virtual processors V (5) -V
(9) is assigned to the physical processors P (4) to P (0) in a folded manner. Similarly, V (10) to V (1
4) is assigned to P (0) to P (4), and V (15) to V (19) is assigned to P (4) to P (0).

As a result, virtual processors adjacent to each other can be assigned to physical processors adjacent to each other or the same physical processor. In this case, all communication between the adjacent virtual processors is performed only by communication between the adjacent physical processors.

Further, according to the data mapping method of this embodiment, for example, elements a [0], a [1], a [2], a [3], b [0] of the local array of the physical processor P (0) are used. , B [1]
, B [2], b [3] are the elements A (0) of the global array.
, A (10), A (9), A (19), B (0), B (10), B (9)
, B (19) are made to correspond. The local arrays of other physical processors also correspond to different parts of the global array.

FIG. 4 corresponds to the mapping of FIG. 3 and converts the program by the parallel Fortran of FIG. 9 into the program of the physical PE. In order to execute the program of FIG. 9, the program of FIG. 4 is copied in advance to the memory of all PEs of FIG. 2, and the program is simultaneously operated in all physical PEs.

First, each physical PE obtains its own processor number by the line 31 in FIG. 4 at the beginning of execution of the program and stores it in the variable p. Subsequent processing is slightly different depending on the value of the processor number.

The case of P (1) to P (3) with the highest number of communications will be described. The line 32 in the figure indicates the physical processor P.
Data transmission from (p) to P (p + 1), line 33 is P
Data transmission from (p) to P (p + 1). In these two transmissions, the partner PE is the left PE and the right PE, respectively. Therefore, since the required communication ports are different, the two transmissions can be executed simultaneously by the PE described in FIG. Row 34 in the figure is P
Data is received from P (p + 1) of (p), line 35 is P
Data is received from (p) to P (p-1). These two data receptions can be performed simultaneously for the same reason.

Further, in the PE of the present invention described in FIG. 1,
Since the coupling between PEs is full duplex, sending and receiving can be done simultaneously, and the communications shown in rows 32-35 can all be done simultaneously.

Further, the sizes of the transmission data and the reception data according to this embodiment are half of those of the conventional example shown in FIG. Lines 72 and 7 of the program of FIG. 11 which is a conventional example
As shown in FIG. 3, in the conventional method, it was necessary to transmit the data of length 4 to the PE on the right side and receive the data of length 4 from the PE on the left side. On the other hand, in the program of FIG. 4 corresponding to the embodiment of the present invention, as shown in lines 32 to 35 in the drawing, the size of the data to be transmitted may be 2 which is half the size of the above-mentioned conventional example. PE on the right side and PE on the left side
To the PE on the right side and P on the left side.
Must be received from E. However, as described above, in the embodiment of the present invention, the transmission to the right side and the transmission to the left side can be executed simultaneously, and the reception from the right side and the reception from the left side can be executed simultaneously.

FIG. 5 is a flow chart showing the operation of the program of FIG. The communication shown in lines 32-35 in FIG. 4 corresponds to steps 47-50 in FIG. 5, respectively.
Corresponding to. In FIG. 5, first, the transmission to the left PE shown in step 47 is executed. And step 47
The control is returned without waiting for the end of execution of the step, and the transmission to the PE on the right side shown in step 48 is executed. Similarly, the reception from the left PE shown in step 49 is executed without waiting for the end of execution of step 48, and the reception from the right PE shown in step 50 is executed without waiting for the end of execution of step 49. . Therefore, each communication in steps 47 to 50
The execution time will overlap.

FIG. 8B shows step 47 in FIG.
It shows the execution time of the communication of ~ 50. These operate almost in parallel with their execution times overlapped, and the total communication time becomes T.

In this embodiment, the data size to be transferred is half that of the conventional example, but instead, the data must be transferred to both the left PE and the right PE. However, the transfer to the left PE and the transfer to the right PE can be executed simultaneously. Therefore, the transfer time can be shortened as compared with the conventional case.

As described above, the data communication time T according to the present embodiment is almost half the data transfer time T'according to the conventional example. 4 and 5, P (0) and P (0)
The processing contents and operation flow in (4) can be easily understood by those skilled in the art from the above description, and thus detailed description thereof has been omitted.

In the embodiment of the present invention described above, 2
Since 0 virtual processors were mapped to 5 physical processors, the mapping could be realized regularly as shown in FIG. However, the present invention is applicable to various numbers of virtual processors and physical processors. For example, the present invention can be applied to the case of mapping 17 torus-coupled virtual processors to 8 non-torus-coupled physical processors. An example of mapping in this case is shown in FIG. Also in this example, the adjacent virtual processors are mapped to the adjacent physical processors or the same physical processor.

Although the embodiment of the present invention described above is a case of a one-dimensional processor, the present invention is not limited to one-dimensional processor and can be applied to a multi-dimensional processor array.
FIG. 7 is an example of mapping a torus network of a two-dimensional virtual processor onto a two-dimensional lattice network of a physical processor. For example, virtual processor V (0,0),
V (0,5), V (5,0), V (5,5) are physical processors P
Virtual processors V (1,2), V assigned to (0,0)
(1,3), V (4,2), V (4,3) are the physical processors P (1,3)
Assigned to 2). As shown in FIG. 7, the adjacent virtual processors are also mapped to the adjacent physical processors or the same physical processor. That is, according to the embodiment of the present invention, a two-dimensional torus-coupled virtual processor is mapped to a non-torus two-dimensional lattice-coupled physical processor. Also, the same method can be applied to a three-dimensional torus.

As described above, according to the present invention, the virtual processor array which is multidimensionally torus-coupled is arranged on the physical processor array which is not torusally coupled and is multidimensionally grid-connected.
Mapping that preserves adjacency is possible. Therefore, according to the present invention, the PE-to-PE communication assuming the torus coupling can be executed at high speed regardless of the lattice network.

Here, the lattice network is easy to divide and expand, and it is a great advantage that the torus network of the virtual processor can be mapped to an arbitrary sublattice in the lattice network.

Furthermore, for example, when a physical processor is spatially divided and assigned to a plurality of users, a torus network can be constructed on a sublattice which is its own area without affecting the areas of other users. . Therefore, it is possible to separate users in data communication, and it is possible to realize a highly reliable programming and program execution environment.

In addition, according to the present invention, in a basic communication pattern that often appears in parallel programming, P
The data transfer time between E can be made faster than before.

[0042]

According to the present invention, it is possible to perform a mapping of a virtual processor array, which is multidimensionally torus-coupled, on a physical processor array, which is not torusally coupled but is multidimensionally lattice-coupled, while maintaining adjacency.

Therefore, according to the present invention, the PE-to-PE communication assuming the torus coupling can be executed at high speed regardless of the lattice network. Also, according to the present invention, in a basic communication pattern that often appears during parallel programming,
The data transfer time between PEs can be made faster than before. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a physical processing element according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a parallel computer according to an embodiment of the present invention.

FIG. 3 is a diagram showing a data mapping method according to an embodiment of the present invention.

FIG. 4 is a program of a physical processing element corresponding to the data mapping of FIG.

5 is a flowchart of the program shown in FIG.

FIG. 6 is a block diagram of the 17 virtual processors to which the present invention is applied.
For explaining how to map to one physical processor

FIG. 7 is a diagram for explaining an application of the present invention to a two-dimensional torus-coupled virtual processor.

FIG. 8 is a diagram for comparing data transfer times in an example of the present invention and a conventional example.

FIG. 9: Example of parallel Fortran program

FIG. 10 is a diagram showing an example of a conventional data mapping method.

11 is a physical PE program derived from the program of FIG. 9 corresponding to the conventional example of FIG.

FIG. 12 is a diagram showing an example of a conventional parallel computer having a simple grid-connected network.

FIG. 13 is a diagram showing an example of realizing multi-user by spatially dividing a conventional two-dimensional torus network.

[Explanation of symbols]

 1 ... Physical processor 2 ... Memory 4 ... Central processing unit 11,21 ... Input port 12,22 ... Output port 13,14,23,24 ... Register or high-speed memory P (0) to P (4) ... Physical processor V (0) to V (19) ... Virtual processor

Claims (1)

[Claims] 1. A plurality of physical processors P (p ₀ , p ₁ , ..., P _N-1 ) numbered with a set of N coordinate values, and a plurality of physical processors numbered with a set of M coordinate values. Virtual processors V (v
₀ , v ₁ , ..., V _M-1 ) between the virtual processors N
In the data mapping method of allocating the data of the virtual processor to the memory of the physical processor by associating each of the coordinate axes with a desired one of the M coordinate axes of the physical processor, the coordinate value in the i direction is When the virtual processor having v _i is associated with the physical processor having a coordinate value in the j direction of p _j , the virtual processor having a coordinate value in the i direction of v _i +1 has a coordinate value in the j direction of p _j −1. , P _j , or p _j +1 and the coordinate value of the virtual processor in the i direction is incremented by 1, the sequence of coordinate values of the corresponding physical processor in the j direction is: A data mapping method comprising at least one subsequence increasing by one and at least one subsequence decreasing by one.