JPH075601A - Camera check system - Google Patents

Abstract

PURPOSE:To irreducibly minimize the development of software dedicated in check and adjustment by enabling a certain part of a program mounted on a camera to use also for check and adjustment of the function of the camera. CONSTITUTION:This system is provided with the camera 33 having a central processing circuit 11 for performing a main processing for the camera 33 and a peripheral circuit connected to the central processing circuit 11, and a computer 30 capable of connecting to the central processing circuit 11 and provided with a command for executing the check and adjustment of the function of the camera through the central processing circuit 11. The command provided in the central processing circuit 11 and executing the check and adjustment of the function of the camera 33 has the function addressing and executing an optional subroutine such as the subroutine software for operating the central processing circuit 11 and the peripheral circuit by the computer 30.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a camera check system for checking and adjusting camera functions.

[0002]

2. Description of the Related Art Recently, along with the computerization of cameras, the adjustment of analog circuits, the light receiving level of light receiving elements,
Setting lens correction data, checking each circuit element, etc.
Due to various check adjustment processes, a large amount of checking software for the computer and the central processing circuit corresponding to each of these items is required.

As a result, the time required for developing the check adjusting software is increasing more and more, and the capacity of the check adjusting software is also increasing more and more.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to allow a part of a program installed in a camera to be used also for check adjustment of camera functions, thereby minimizing the development of check adjustment dedicated software.

[0005]

SUMMARY OF THE INVENTION The present invention is capable of connecting a camera having a central processing circuit for performing main processing of a camera and a peripheral circuit connected to the central processing circuit to the central processing circuit. A computer having a command for adjusting and checking the camera function via the computer, and a subroutine software for operating the central processing circuit and peripheral circuits in the command for checking and adjusting the camera function provided in the central processing circuit. It is characterized in that it has a function of addressing and executing an arbitrary subroutine from the computer.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to illustrated embodiments. FIG. 1A is a diagram showing a control block of this embodiment. The central processing circuit 11 includes an A / D converter 12,
Interval timer 13 and ROM 14a, RAM1
It is a microcomputer having 4b (hereinafter referred to as a microcomputer). In the central processing circuit 11, the BV detector 18 and the EEPROM 1 are connected via the analog signal A and the communication line B.
9 and the external data operation F20 are connected. The central processing circuit 11 further includes an oscillator 15, an LCD display 26,
The lens information input unit 27, the cartridge information input unit 28, the switch information input unit 29, the sequence control unit 32, the regulator 16, and the DC / DC converter 17 connected to the battery 21 are connected.

The external data operation F20 is connected to the central processing circuit 11 via a terminal group C connected to the communication line B. The external data operating unit 20 is a DTC 30.
And an interface 31 (FIG. 1B) connected to the terminal group C and the DTC 30. These DTC3
0 and the interface 31 are connected to each other via the communication terminal group D.

The battery 21 connects the main power supply to the system of the camera 33. In this embodiment, the camera 33 is described as a single-lens reflex camera, but the application of the present invention is not limited to the single-lens reflex camera, and any other camera having an electronic circuit can be applied. . The regulator 16 inputs the voltage of the battery 21 and outputs a constant voltage to the central processing circuit 11. DC /
The DC converter 17 inputs the battery voltage, inputs the power hold signal from the central processing circuit 11, and outputs power to the peripheral circuits. The BV detector 18 outputs the BV information designated by the control of the central processing circuit 11 to the central processing circuit 11. The oscillator 15 supplies high-speed and low-speed clock signals to the central processing circuit 11.

The LCD display 26 displays the LCD display data from the central processing circuit 11. Lens information input section 2
7 is the lens A depending on the type of lens attached.
Information such as / M, open aperture, minimum aperture, and focal length is output to the central processing circuit 11. Patrone information input section 2
Reference numeral 8 outputs information such as the presence or absence of a cartridge and the sensitivity of the film to the central processing circuit 11. Switch information input section 29
Is the central processing circuit 1 for the information of the mirror up switch, the mirror down switch, the film switch, the release switch, the photometric switch, the rewind switch, the back cover switch, the UP / DOWN switch and the mode setting switch.
Output to 1.

The sequence control unit 32 includes a central processing circuit 1.
The signal 1 controls the mirror, the exposure of the film and the winding of the film. EEPROM 19
Is connected to the central processing circuit 11 via a communication line B, and reads / writes EEPROM data. The external data operating unit 20 is connected to the central processing circuit 11 via the terminal group C, and adjusts the camera, checks the functions, changes the specifications, inputs photographing information, and the like via the central processing circuit 11.

A DTC (computer) 30 is a computer having software for performing a camera function check RAM, a set dump of EEPROM, and the like. DTC30 is EE
When it is desired to write data to the PROM 19 by software, the writing mode is set, and if the stack is OK at this time, writing can be surely performed.

The interface 31 and the DTC 30 are
The 16-bit signals communicate with each other, and the time sequence of this communication is shown in FIG. Among them, the interface 31 has a function of converting a signal taken in from the camera 33 into a 16-bit signal and communicating with the DTC 30. "PCTL" and "PFLAG" in the figure are control signals for performing a data handshake,
16-bit input / output is executed by O15-0 "and" DI15-0 ". Whether or not the code is a test code is determined by the combination of" CTL0 "and" CTL1 ".

When data is output from the DTC 30, D
TC30 sets I / O to "L (low)" and
Before lowering L, the transmission data of "DO15-0" is fixed. Next, the PCTL is turned off and a data input request is output to the central processing circuit 11 via the interface 31. When the central processing circuit 11 detects “L” of PCTL, the central processing circuit 11 inputs “DO15 to 0” via the interface 31. Then, since the central processing circuit 11 side has fetched the necessary data, the PF
Shut down LAG. When the DTC 30 detects that PFLAG has dropped through the interface 31, DTC 30
TC30 is a PCT to enable communication of the next data.
Start up L. When the central processing circuit 11 detects “H (high)” of PCTL via the interface 31,
The central processing circuit 11 activates PFLAG to permit communication from the next DTC 30. The DTC 30 and the central processing circuit 11 use PCTL and PFLAG to perform a handshake in this manner, and the DTC 30 outputs a command or data to the central processing circuit 11. The distinction between command and data is DTC.
30 outputs as test code communication when CTL0 is "H", and as data communication accompanying the test code when CTL0 is "L". Whether or not there is a test request from the DTC 30 side can be checked based on whether CTL1 is "H" or "L". If "H", "test request"
If “L”, it means “no test request”.

When inputting data to the DTC 30, the DT
The C30 sets the I / O to the "H" state and causes the PCTL to fall. PCTL via interval timer 31
When the central processing circuit 11 detects "L" of "1", the central processing circuit 11 side outputs data corresponding to the command at that time to "DI15-0" via the interface 31. Then, through the interface 31, PFLAG
"L" of (P flag) is output to the DTC 30 to instruct data input. After that, the same handshake as described above is executed to cause the DTC 30 side to read the data.

FIG. 3A shows the connection relationship between the DTC 30, the interface 31, and the camera 33. The interface 31 can be operated by a chip enable signal (DCE) from the camera 33. Interface 3
1 is CTL1 and “DO1” according to the signal from the camera 33 side.
A data switching block 34 for switching data such as 5-8 "and outputting it to the camera 33, a parallel data for converting parallel data from the DTC 30 into serial data in synchronization with a serial clock from the camera 33, and outputting the parallel data to the data switching block 34. / Serial conversion block 35, latch pulse generation block 36 for generating a latch pulse according to a serial clock for each byte from the camera 33, serial / parallel conversion block for converting a serial signal into a parallel signal and outputting it to each latch block 38, the upper 8 bits of the “DI15 to 0” serial signal output from the camera 33 are latched and output to the DTC 30.
A bit latch block 37, a lower 8 bit latch block 39 which similarly latches the lower 8 bits and outputs it to the DTC 30, and a PFLAG signal latch block which similarly latches the PFLAG serial signal output from the camera 33 and outputs the PFLAG signal to the DTC 30. Has 40.

The communication terminal group D connecting the interface 31 and the DTC 30 includes a terminal 41 (CTL1) and a terminal 42.
(DO15 to 8), terminal 43 (DO7 to 0), terminal 44
(CTLO, PCTL, I / O), terminal 45 (DI15
~ 8), terminal 46 (DI7-0), and terminal 47 (P
FLAG).

The terminal group C for connecting the camera 33 and the interface 31 includes a terminal 48 (SI) and a terminal 49 (DC
E), a terminal 50 (SCK), and a terminal 51 (SO). The terminal 48 (SI) is pulled up by the resistor 53 on the camera 33 side. These terminals 48-51
Is a terminal that the user normally does not use,
It is not exposed to the outside of the camera 33.

The terminal 48 (SI) is a terminal for outputting data to the camera 33 side according to the serial clock.
CTL1 is a test request at "H" (Fig. 2), and CT
When L1 is selected, the data switching block 3 is provided on the camera 33 side.
It is inverted at 4, and "L" is output to the SI terminal. By inputting "L" of CTL1 on the camera 33 side, it can be determined that there is a test request from the DTC 30 side. The terminal 49 (DCE) is a chip enable and is a signal for requesting the input / output of data from the camera 33 to the interface 31. A request is made with "L", and a signal is not outputted from the interface 31 with "H". Can be banned as Terminal 50 (SCK)
Is a terminal that supplies a serial clock for serial communication between the camera 33 and the DTC 30 to the interface 31. The terminal 51 (SO) is a terminal for outputting serial data from the camera 33 to the interface 31.

The parallel / serial conversion block 35 includes
It is connected to the terminals 42 to 44 and the terminals 49 and 50, and outputs the serial data to the data switching block 34 in synchronization with the serial clock when the chip is enabled. This data switching block 34 has a terminal 41
Also, the output of the block 35, which is connected to the terminals 49 and 50, switches between the output of the CTL1 and the parallel / serial converted outputs output from the terminals 42 to 44 in accordance with the serial clock, and the terminal 48 (SI). Output to. The data switching block 34 is normally open and selectively outputs CTL1 until a clock is output due to chip enable. The latch pulse generation block 36 is connected to the terminals 49, 50 and 51 and outputs a latch clock to the upper 8-bit latch block 37, the lower 8-bit latch block 39 and the PFLAG signal latch block 40. The serial / parallel conversion block 38 is connected to the terminals 49 to 51, converts 8-bit serial data into parallel data, and outputs the upper 8-bit latch block 37 and the lower 8-bit.
8 bit parallel data is output to the t latch block 39 and the PFLAG signal latch block 40. The latch blocks 38, 39 and 40 latch the parallel data from the serial / parallel conversion block 38 according to the latch signal output from the latch pulse generation block 36.

The upper 8-bit latch block 37 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and DI1 is connected to the terminal 45.
Output 5-8 data. The lower 8-bit latch block 39 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and outputs DI7-0 data to the terminal 46. The PFLAG signal latch block 40 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and outputs the PFLAG signal to the terminal 47.

FIG. 3B shows the timing of signals input and output from the above terminals. When the terminal 49 (DCE) is at "H", appropriate serial communication is performed and a knot cell (NOTSEL) state is set before the chip enable is applied. This knot cell is, so to speak, the central processing circuit 11
Is a preparatory stage for cutting the communication line between the EEPROM 19 and the BV detecting section 18 to allow the central processing circuit 11 to communicate with the external data operation F20. Next, the camera 33 sets the chip enable (DCE) to "L". Until the serial clock is output in this state, the level of the CTL1 signal of the DTC 30 can be checked by the level of the SI terminal. SI terminal is "L"
In case of, there is a TEST request from DTC 30 (CTL1
= 1), conversely, when the SI terminal is "H", DTC
There is no TEST request from 30.

Next, when serial communication is performed, in the first serial communication, data relating to PCTL (including data of I / O and CTLO) is output from the terminal 48 (SI) to the camera 33 side. For this first 8-bit serial communication, data relating to PFLAG, that is, data indicating whether or not the P flag is set is output from the camera 33 from the terminal 51 (SO). When the serial clock is continuously output, DO7-0 and terminal 51 are output to the terminal 48 (SI).
When the data of DI7-0 is output to (SO) and the serial clock is output continuously, DO1 is output to the terminal 48 (SI).
5 to 8 and terminals 51 (SO) serially communicate data of DI 15 to 8. The serial communication is effective 0 to 3 times in 8-bit units after the chip enable, and the chip enable can be turned off in the range to stop the communication.

The operation of the camera 33 and the DTC 30 of this embodiment will be described with reference to the flow charts shown in FIGS. Other than FIG. 21, the flowchart is on the camera side. 4 and 5 show a "VDD OFF loop", that is, a normal operation before the main power is turned on. First, the routine starting with the label "RESET" is entered. In step S1, the stack pointer is initialized,
In S2, "reset processing" such as RAM all clear, port input / output, output data setting and special register setting is executed, and the routine proceeds to the routine starting with the label "SW1CHK".

In S3, the VDD ON flag is cleared, and in S4, the stack pointer is reset, and S
In 5, the subroutine starting with the label "TEST" is called to execute the "TEST check process". S6
Then, it is determined whether or not there is a test request from the DTC 30, and if there is a request, the process proceeds to S7, and if not, the process proceeds to S8. S
In 8, the UP / DOWN switch and the mode setting switch are monitored, and "UP / DOWN processing" such as data change is executed. In S9, "LCD display process" for displaying the internal data set in the UP / DOWN process or the like.
To execute. In S10, it is determined whether or not the photometric switch is turned on. If it is turned on, the process proceeds to S7 and VDD is turned on.
Set the flag, otherwise proceed to S11. S1
In 1, it is determined whether or not the release switch is turned on. If it is turned on, the process proceeds to S7, and if not, the S12 is performed.
Proceed to. In S12, VDD is turned off and power hold is turned off, and in S13, timer interrupt permission is executed. In S14, "power down processing" is executed to enter the power down mode. After a predetermined time, a timer interrupt occurs, and "timer interrupt processing" is executed in S15. Power consumption is suppressed by powering down between S14 and S15. In S16, "timer interrupt prohibition" is executed, and the loop goes to the label "SW1CHK".

In S7, the VDD flag is set and S1 is set.
In step 7, VDD is turned on, power hold is turned on, and S
At 18, the "VDD stable time wait process" for waiting for the peripheral circuit reset time and BV stable time is executed. In S19, a subroutine starting with the label "TEST" is called to execute "VDD ON TEST processing", and in S20, a subroutine starting with the label "SIEEP" is continuously called to perform AE calculation and sequence control. The "EEPROM data input process" for inputting the EEPROM data for use in the RAM 14a is executed. S
In step 21, "lens check processing" is executed to input mount pin information, lens ROM information, etc.
Proceed to RT ".

The main routine is shown in FIGS. 6 and 7. First, enter the routine starting with the label "RESTART",
In S22, the interval timer is initialized and S23 is set.
Then, using this interval timer, a process of setting data so that the power hold timer is set to 10 seconds is executed, and the process proceeds to the label “VDD LP”. S24
Then, the mirror UP / DOWN processing is executed, the lens check processing is executed in S25, and the "BV
A / D conversion processing "is executed. In S27," Patrone information input processing "is executed to input and convert data such as film presence / absence and film sensitivity.
Based on the input data, "AE calculation processing" for obtaining TV value, AV value, etc. is executed. In S29, it is determined whether or not the test is permitted. If the test is permitted, the process proceeds to S30 to execute the "TEST process", and if not, the process jumps to S31.

At S31, L for the LCD display 26 is displayed.
The CD display processing is executed, and in S32, it is determined whether or not the release button is pressed. If the release button is pressed, the routine starts with the label "release processing". If not, the routine proceeds to S33. In S33, the time interval of the interval timer set in S22 is checked, the process returns to S32 until the set time elapses, and the process proceeds to S34 when the time elapses. In S34, a "power hold timer count process" is executed, and in S35, it is determined whether or not the count of the power hold timer is finished. For example, the operation returns to "VDD LP" and the processing is repeated.

Next, the "release process" will be described.
In S36, the analog signal of the BV detector 18 is output to the central processing circuit 11, and the A / D of the BV value immediately before the release is output.
Perform the conversion. In S37, AE calculation processing is executed,
In S38, mirror up processing is executed, and in S39,
Exposure control processing is executed, and in S40, mirror and film winding processing is executed. In S41, it is determined whether or not the end of the film has been detected. If detected, the process proceeds to S43, and if not, the process proceeds to S42. In S42, "FI
The subroutine starting with the label "LMCUP (Film Count Up)" is called to execute "Film Count Processing", and returns to the "RESTART" label. In S43, "Film Rewind Processing" is executed, S
At 44, a subroutine starting with a label "FILM CLR (film clear)" is called to execute "film number clear processing" and jump to "SW1CHK".

FIG. 8 and FIG. 9 are flow charts showing the writing of data to the EEPROM 19. "FI
The routine starting with the label "LM CUP" is for counting up, and the routine starting with the label "FILM CLR" is for clearing the number of films.
In S45, the number of films in the RAM is counted up, and in S46, the number of films is set in the buffer. In S47, the address pointer in which the number of films is written in the EEPROM 19 is set. In S48, the write (write) flag of the DTC 30 is cleared, not the writing of the DTC 30 but the normal camera mode is set by software, and the routine starts with the label "SOEEP".

"SOEEP" means E from the DTC 30 side.
This is a subroutine called when writing to the EPROM 19 or the like. In S50, a subroutine starting with the label "SIEEP" is called to check whether the same data is currently written in the EEPROM before starting writing, and "EEPRO" is called.
M data input processing "is executed to check the state of the EEPROM data. In S51 and S52, the lower byte and the upper byte are checked, and if both are the same, a return is made and no processing is executed. If the stack is OK, it is determined in S53 whether the stack has become too deep due to a runaway, etc. As a result, if the stack is OK, the process proceeds to S54, and it is determined that the stack is abnormally deep. In this case, the operation returns and writing is not executed.Here, the EEPROM 19 has a capacity of "1 word x 64" in units of 1 word. Since this 1 word is composed of the lower byte and the upper byte, the lower data In other words, whether the lower 8 bits are the same as the data to be written, the upper data, that is, the upper 8 bits are to be written. Whether the same or not as there data, are to determine the.

The stack area set on the RAM 14b of the camera 33 has a sufficient capacity during normal operation, but if there is no return due to runaway or the like and only calls are repeated, that area will be immediately released. It will be crushed. Therefore, even if the write subroutine is called in such a state, it is not known whether or not the write data is normally stored in the buffer. Therefore, in the case of NO in S53, the process is returned.

In S54, it is judged whether or not the "DTC30 write (write) mode" is set, and if it is this mode, S5 is set.
If the writing is not in the DTC 30 but in the normal camera mode, the process proceeds to S55. That is, in the "DTC write (write) mode", writing is possible to all addresses of the EEPROM 19.

At S55, the film address is checked. Here, "FILM CUP" or "FILM
Check if the same address as the EP address pointer for the number of films set when entering from "CLR" can be detected as it is. And if it comes from "FILMCUP", it should be equal. However, if you call "SOEEP" etc. to write to an address other than the number of films, you cannot write because the film addresses are not the same. To be done.

In step S56, EEPROM chip enable is executed, in step S57, write permission communication (mode and address) to the EEPROM 19 is executed, and in step S58.
Then, turn off the EEPROM chip enable and set S5
In 9, the EEPROM chip enable is executed, and S6 is executed.
At 0, EEPROM write start communication (mode and address) is executed. In S61, lower byte (lower 8 bits) data output communication is executed, in S62, lower byte (lower 8 bits) data output communication is executed, and S6
In 3, the write time of 15 ms is executed,
In S64, the EEPROM chip enable is turned off.
Then, in S65, the EEPROM chip enable is executed, in S66, the write inhibition code communication (mode and address) is executed, and in S67, the EEPROM chip enable is turned off and the process returns. "FILM
In CLR ", in S49, the number of films stored in the RAM 14a is cleared and the process jumps to S46.
Writing to the OM 19 is prohibited, and writing to the EEPROM 19 is also prohibited when an abnormal operation is detected.

A routine for reading data from the EEPROM 19 starting from the label "SIEEP" to the DTC 30 side will be described with reference to FIG. In S68, since other data such as the BV detection unit 18 and external devices exist in the communication line, the communication destination change mode is set to communicate with the EEPROM 19. In S69, the communication destination is E
Change to EPROM 19. In S70, the data communication mode is set, in S71, the EEPROM chip enable is executed, and in S72, the EEPROM read start communication (mode and address) is executed. The lower byte is input to the buffer in S73, the upper byte is input to the buffer in S74, and the EEPROM chip enable is turned off in S75.

The routine starting with the label "TEST" will be described with reference to FIGS. In S76, the PH request flag is set as the initial setting because there is no power hold request from the DTC 30. In S77, the test switch is input, and in S78, it is determined whether or not there is a test request, and if so, the process proceeds to S79, otherwise returns. In S79, it is determined whether or not the DTC error has already been detected. The DTC error is set, for example, when the DTC 30 outputs when a test code must be input next.

If a DTC error is determined in S79, the process jumps to S85, and if not, the process proceeds to S80. S80
Then, unless you output "1" to PFLAG, DTC
Since PCTL cannot be shut down from the 30 side,
First, "1" is output to PFLAG, and then the PCTL input process is executed in S81. In S82, PCT
It is determined whether L becomes "0", that is, whether there is a request from the DTC 30 side. If "0", the process proceeds to S83. If not, the RAM monitor is executed.
Proceed to S85.

At S83, VDD is checked to see whether the power-down loop or the main loop is present.
It is determined whether or not the flag is turned on. As a result,
If the power down loop is set, the DTC power hold flag is set in S84 so that the power is automatically set after returning, and S85 to S85 are set.
The RAM is monitored at 87 and the process returns. In other words, in S85, the sampling permission / prohibition bit is determined, and if it is determined to be valid, the process proceeds to S86 to input the monitor RAM address
The RAM data of the body for that address is set in the buffer. In S87, 16-bit data output processing is executed, and the data in the buffer is the lower 8 bits (DI7-
0) is output.

If it is determined that the power is already turned on, the DTC communication mode is switched to, PCTL is input, and waits until PCTL becomes "0 (low)" (S88).
~ S90), when it becomes low, the process proceeds to S91. In S91, it is determined whether CTLO has been set to "1", and "1" is set.
If so, the process proceeds to S92, and if not, the process returns. In S92, a test switch input process is executed, and S
At 93, it is determined whether or not there is a test request. If there is a test request, proceed to S94, otherwise return.

In S94, the input process of the DTC code is executed. If the lower part of the DTC code is the test code "FE", the process exits by return. (S
94-S96). When the lower order of the test code is neither "FE" nor "FF", the registration code is further determined. The test table shown in FIG. 13 includes “SUBC
HK ”,“ RAMDUMP ”,“ RAMSET ”,“ E ”
Codes of "EPDUMP" and "EEPSET" are registered. In case of other test codes, "D"
The routine starts with the label "TC ERR". In this routine, "0" is output to PFLAG in S99, and the DTC30 error flag is set in S100. That is, the handshake after that is disabled. Exit to the power-down "SW1CHK" routine.

In S101, it is determined whether the test code is OK. That is, for example, as shown in FIG. 21, the data output in the case of the test code has a higher order of "1".
0 "and lower order are set to" 00 "to" 04 ",
I am checking this upper "10". If it is OK, the process proceeds to S102, the subroutine address for the test code is set in the pointer, and the test subroutine is executed in S103. If the test code is not OK in S101, the process proceeds to "DTC ERR".

In FIG. 14, "HANDOUT", "HAN"
The routines starting with the label "DIN" are shown. These routines are subroutines for actually inputting and outputting 16-bit data. First, "HAND OUT"
In the routine starting with the label of
Data is input, the process proceeds to S105, and it is determined whether or not PCTL is "0". If "0", the process proceeds to S106. If not, the process returns to S104. In S106, I / O data is input. In S107, it is determined whether or not the DTC 30 is in the input mode based on the input I / O data. If the DTC 30 is in the input mode, the process proceeds to S108.
Go to the routine starting with the label. In S108, 16
Bit data output processing is executed, and in S109, PF
"0" is output to LAG, and PCTL is input in S110. In S111, it is determined whether the PCTL has become "1" based on the input PCTL data. If "1", the process proceeds to S112. If not, the process returns to S110.
Repeat PCTL input. In S112, "1" is output to PFLAG and the process returns.

In the routine starting with the label "HAND IN", the PCTL data input process is executed in S113, and the PCTL data is input in S114.
It is determined whether TL is "0", and if "0", S
115, otherwise, return to S113, PCT
Repeat L input. In S115, it is determined whether the DTC is in the output mode based on the input I / O data. If the DTC is in the output mode, the process proceeds to S116.
R ”is executed. In S116, an input process of DTC30 data is executed, in S117, an echo back process is executed, and the process proceeds to S109.

Referring to FIG. 15, the routine starting with the label "TEST PCTL" will be described. This routine
If there is a test request when PCTL falls, the process returns to S88 of the main loop, and if there is no test request, the process returns to continue the processing of the dependent data. In S118,
The DTC serial mode is executed, and in S119, the PCT
L data is input, and it is determined in S12 whether PCTL has become "0". If "0", the process proceeds to S121, and if not, the process returns to S119. In S121, it is determined whether or not a test request is issued. If a test request is issued, the process proceeds to S122, and if not, the process returns.
In S122, one level of the stack is cut and the process returns.

Referring to FIG. 16, the subroutine starting with the label "RAMDUMP" will be described. This routine
This is for outputting all the data written in the RAM 14b and is executed by the output of the test code "1" from the DTC 30 shown in FIG. In S123, the DTC data is input and processed, and in S124, the DTC data is input.
The start address of the RAM output to 30 is set in the RAM address pointer, the upper data of the DTC data is cleared in S125, and the PCTL input process is executed in S126. In S127, it is determined whether the PCTL has become "0" based on the input PCTL. If "0", the process proceeds to S128. If not, the process returns to S126.
Repeat PCTL input. In S128, it is determined whether or not the next test code is output. If the test code is a test code, the process returns. If not, the process proceeds to S129 to continue the RAM dump. In S129, the RAM data is prepared in the buffer, and in S130, "HANDOUT" is called to output the RAM data to the DTC 30, and S131
Then, the process from S126 is repeated with the RAM address pointer + 1.

Referring to FIG. 17, the subroutine starting with the label "EEPDUNP" will be described. This routine
This is for outputting the data written in the EEPROM 19, and is executed by the output of the test code "3" from the DTC 30 shown in FIG. In S132,
Input processing of DTC data is executed, and in S133, DT
The start address of the EEPROM 19 output to C30 is set in the EEPROM address pointer. S13
In 4, call the "SIEEP" subroutine,
Input processing of EEPROM data is executed. In S135, the DTC communication mode is set, and in S136, the PCT is set.
L input processing is executed, and in S137, the input PCTL
Judge whether PCTL is "0" from the data,
If "0", the process proceeds to S138, and if not, S13.
Repeat 6 In S138, the output of the next test code is determined. If the test code is output, the process returns, and if not, the process proceeds to S139. In S139, "HANDOU
T "is called to output the EEPROM data to the DTC 30, the" EEPROM address pointer + 1 "is set in S140, and the process returns to S134 to repeat the EEPROM dump determination.

Referring to FIG. 18, the routine starting with the label "EEPSET" will be described. This routine is
It is a routine for executing writing to the ROM 19,
It is executed by the output of the test code "4" from the DTC 30 shown in FIG. In S141, input processing of DTC data is executed, and in S142, when the EEPROM write mode is entered, the EEPROM from the DTC 30 is first read.
The M write start address is fetched and set in the EEPROM address pointer in the RAM 14b. S14
In 3, the DTC communication mode is set, and in S144, PTC is set.
Perform CTL input processing.

In S145, it is determined whether PCTL is "0" or not according to the input PCTL data.
146, otherwise return to S144, PCT
Repeat L input. In S146, it is determined whether or not the next test code is output. If there is a test code, the process returns, and if not, the process proceeds to S147. In S147, "HANDIN" is called to execute DTC data input processing, in S148, data is set in the EEPROM write buffer, and in S177, a DTC write (write) flag for writing to an arbitrary address is set. To do. In step S149, a subroutine starting with the label "SOEEP" is called to execute the EEPROM writing process. In step S178, the DTC write (write) flag is cleared, and in step S150, "EEPRO" is set.
The M address pointer + 1 "is executed, and the process returns to S143. That is, the process is performed so that the flag is set only when the EEPROM writing process is executed. When the number of films is usually counted, the DTC writing mode is not set. Be sure to clear the flag so that you can see that,
It is determined whether the TC write mode is set or not, and if the DTC write mode is not set, only the film address is written.

Referring to FIG. 19, the routine starting with the label "RAM SET" will be described. This routine
This is a routine for executing writing to M14b, which is executed by the output of the test code "2" from the DTC 30 shown in FIG. In S151, input processing of DTC data is executed, and in S152, the start address of the RAM input from the DTC 30 is set in the RAM address pointer. In S153, PCTL input processing is executed, and in S154, PCTL data is input according to the input PCTL data.
It is determined whether TL is "0", and if "0", S
155, otherwise return to S153, PCT
Repeat L input. In S155, the output of the next test code is determined, and if there is a test code, the process returns, and if not, the process proceeds to S156. In S156, DTC data input processing is executed, and in S157, the DTC data is stored in the RAM designated by the address pointer in the RAM 14b.
The data is set, and the "RAM address pointer + 1" is set in S158, the flow returns to S153, and the RAM setting is repeated.

Referring to FIG. 20, the routine starting with the label "SUBCHK" will be described. This routine is based on a large number of subroutine data stored on the camera 33 side.
21 is a routine for executing a subroutine corresponding to the subroutine address issued from the DTC 30 side.
The test code "0" is output from the DTC 30 shown in FIG. In step S159, the subroutine address is input from the DTC 30 and stored in the RAM 14b.
At 0, the code input from the DTC 30 is used as a subroutine address to execute the call, and the process returns.

The control routine of the basic software "DTC SOFT" on the DTC 30 side will be described with reference to FIG.
This routine causes the camera 33 side to execute various operations based on the set test code, and the RAM 14b.
To the EEPROM, writing to the EEPROM 19, and the like. First, in S161, initial setting of the array dimension, data, etc. is performed, in S162, data display setting processing is executed, and in S163, test code input processing is executed. In S164, the input test code is determined, and if the test code is "0", the process proceeds to S165, and if the test code is "1", S16.
6 proceeds to S167 if "2", proceeds to S168 if "3", and proceeds to S169 if "4".

In step S165, a test code and a subroutine address are issued to the camera 33 side so that the DTC 30 can check the camera function.
This is a case where a plurality of preset subroutines are executed. The subroutines referred to here are all those that normally operate when the user operates the camera, and also appear in FIGS. 4 to 10. First, in order to output the first test code to the camera 33 side, in order to set a bear capable of outputting the test code, set CTL1 = 1 and CTL0 = 0 (see FIG. 2) and output the test code “1000H”. . After that, CTL1 = 0 and CTL1 = 1 are set to enter the subordinate data communication state. The subordinate data corresponding to the test code 1000H is a subroutine address that specifies an address in which a subroutine corresponding to the camera function to be checked is stored and is output. Based on this, the corresponding subroutine of the camera is executed. If it is necessary to set the data in the RAM before executing the subroutine, 100 described below will be used.
It can be set by the test code of 2H, and when the data is set in the RAM after the execution of the subroutine, it can be input to the DTC 30 by the RAM dump of 1001H which will be described later. Therefore, various check adjustments can be easily performed in combination with the execution of other subroutine addresses. According to this,
The software for operating the camera is made into a subroutine and stored, and by simply outputting and executing the address of the subroutine required for check adjustment, check adjustment can be performed easily and reliably. It is not necessary to install special software created for adjustment on the camera side, and the ROM memory capacity can be greatly saved.

Here, an actual example in which an arbitrary subroutine is executed from the DTC 30 side to check the reliability of the lens communication data in a short time will be shown. Normally, the camera communicates with the lens about once every 200 mS, so by executing this communication from the DTC 30, continuous communication becomes possible, and the test time is halved.
It can be shortened to about 0. The test list is shown below.

Further, in S166, a RAM is issued by a command.
This is a case where all the data in 14b is fetched to the DTC 30 side. First, the test code “1001H” is output to the camera 33 side, and the start address (= RAM address 0) is output. By continuously executing data input, all the data in the RAM 14b can be fetched from the RAM 14b to the DTC 30 side. S167
Is a case of writing data to the RAM 14b by a command. First, the test code "1002H" is output to the camera 33 side, and the start address is output. Continuously, I want to set the data in order from the start address
By outputting the AM data, the data can be written in the RAM 14b. S168 is a case where all the data in the EEPROM 19 is fetched to the DTC 30 side by a command. First, test code “1003H”
Is output to the camera 33 side, and the start address (= EEP
The address 0 of the ROM 19) is output. By continuously executing data input, all the data in the EEPROM 19 is transferred from the EEPROM 19 to the DTC3.
It can be captured on the 0 side. S169 is a case where data is written in the EEPROM 19 by a command. First, the test code “1004H” is output to the camera 33 side, and the start address is output. Continuously, EEPROM which wants to set in order from the data of the start address
By outputting the data, the data can be written in the EEPROM 19.

FIG. 22 shows a control routine which starts with the label "SIOSUB". In S170, the address communication mode is set, in S171, the output processing of the address is executed, and in S172, the data communication mode is set,
In S173, data input / output processing is executed.

FIG. 23 shows a routine starting with the label "NOTSEL". In S174, the address communication mode is set, in S175, the output process of the NOTSEL address is executed, and in S176, the data communication mode is set.

[0057]

As described above, according to the present invention,
Software for executing normal camera operations has been made into a subroutine so that it can also be used as software for checking and adjusting camera functions, so software dedicated to checking and adjusting on the camera side is minimized, and the ROM on the camera side is compressed. Therefore, the ROM area that can be used as a camera can be increased accordingly. As a result, the quality of the product software can be improved, the development amount of the software can be reduced, and the product can be commercialized more quickly.

[Brief description of drawings]

FIG. 1A is a diagram schematically showing a control block of the present embodiment.

FIG. 1B is a diagram schematically showing a DTC and an interface.

FIG. 2 is a time sequence during communication between the DTC side and the camera side.

FIG. 3A is a block diagram showing a connection status of a DTC, an interface, and a camera.

FIG. 3B is a time sequence showing the timing of signals input to and output from the DTC, the interface, and the camera according to the embodiment.

FIG. 4 and FIG. 5 are flowcharts showing a routine that starts with a label “RESET” in the same embodiment.

6 and 7 are flowcharts showing a routine that starts with the label "RESTART" in the embodiment.

8 and 9 are flowcharts showing a routine that starts with the label "FILMCUP" in the embodiment.

FIG. 10 is a flowchart showing a routine that starts with a label of “SIEEP” of the embodiment.

FIG. 11 and FIG. 12 are flowcharts showing a routine that starts with the label “TEST” in the embodiment.

FIG. 13 is a diagram showing a “test code” of the same example.

FIGS. 14A and 14B are “HANDOUT” and “HAND” of the embodiment.
6 is a flowchart showing a routine starting with a label of “IN”.

FIG. 15 is a flowchart showing a routine that starts with a label “TESTPCTL” in the embodiment.

FIG. 16 is a flowchart showing a routine that starts with a label “RAMDUMP” in the embodiment.

FIG. 17 is a flowchart showing a routine that starts with a label “EEPDUMP” in the embodiment.

FIG. 18 is a flow chart showing a routine that starts with a label “EEPSET” in the embodiment.

FIG. 19 is a flowchart showing a routine that starts with a label “RAMSET” in the embodiment.

FIG. 20 is a flowchart showing a routine that starts with a label of “SUBCHK” in the same embodiment.

FIG. 21 is a computer flowchart showing a routine that starts with the label “DTCSOFT” of the embodiment.

FIG. 22 is a flow chart showing a routine that starts with a label of “SIOSUB” in the same embodiment.

FIG. 23 is a flow chart showing a routine that starts with the label “NOTSEL” of the embodiment.

[Explanation of symbols]

 11 Central Processing Circuit 12 A / D Converter Internal 13 Interval Timer 14b RAM 15 Oscillator 16 Regulator 17 DC / DC Converter 18 BV Detecting Section 19 EEPROM 20 Data Manipulating Section 21 Battery 26 LCD Display 27 Lens Information Input Section 28 Patrone Information Input unit 29 Switch information input unit 30 DTC (computer) 31 Interface 32 Sequence control unit 34 Data switching block 35 Parallel / serial conversion block 36 Latch pulse generation block 37 Upper 8 bit latch block 38 Serial / parallel conversion block 39 Lower 8 bit latch block 40 PFLAG signal latch block A communication line B communication line C terminal group D communication terminal group

[Procedure amendment]

[Submission date] November 27, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a camera check system for checking and adjusting camera functions.

[0002]

2. Description of the Related Art Recently, along with the computerization of cameras, various check adjustment processes such as adjustment of analog circuits, adjustment of light receiving level of light receiving elements, setting of correction data of lenses, check of each circuit element, etc. Therefore, a large amount of checking software for the computer and the central processing circuit according to each of these items is required.

As a result, the time required for developing the check adjusting software is increasing more and more, and the capacity of the check adjusting software is also increasing more and more.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to allow a part of a program installed in a camera to be used also for check adjustment of camera functions, thereby minimizing the development of check adjustment dedicated software.

[0005]

SUMMARY OF THE INVENTION The present invention is capable of connecting a camera having a central processing circuit for performing main processing of a camera and a peripheral circuit connected to the central processing circuit to the central processing circuit. A computer having a command for adjusting and checking the camera function via the computer, and a subroutine software for operating the central processing circuit and peripheral circuits in the command for checking and adjusting the camera function provided in the central processing circuit. It is characterized in that it has a function of addressing and executing an arbitrary subroutine from the computer.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to illustrated embodiments. FIG. 1A is a diagram showing a control block of this embodiment. The central processing circuit 11 includes an A / D converter 12,
Interval timer 13 and ROM 14a, RAM1
It is a microcomputer having 4b (hereinafter referred to as a microcomputer). In the central processing circuit 11, the BV detector 18 and the EEPROM 1 are connected via the analog signal A and the communication line B.
9 and the external data operating unit 20 are connected. The central processing circuit 11 further includes an oscillator 15, an LCD display 26,
The lens information input unit 27, the cartridge information input unit 28, the switch information input unit 29, the sequence control unit 32, the regulator 16, and the DC / DC converter 17 connected to the battery 21 are connected.

The external data operating section 20 is connected to the central processing circuit 11 via a terminal group C connected to the communication line B. The external data operating unit 20 is a DTC 30.
And an interface 31 (FIG. 1B) connected to the terminal group C and the DTC 30. These DTC3
0 and the interface 31 are connected to each other via the communication terminal group D.

The battery 21 supplies main power to the system of the camera 33. In this embodiment, the camera 33 is described as a single-lens reflex camera, but the application of the present invention is not limited to the single-lens reflex camera, and any other camera having an electronic circuit can be applied. . The regulator 16 inputs the voltage of the battery 21 and outputs a constant voltage to the central processing circuit 11. DC /
The DC converter 17 inputs the battery voltage, inputs the power hold signal from the central processing circuit 11, and outputs power to the peripheral circuits. The BV detector 18 outputs the BV information designated by the control of the central processing circuit 11 to the central processing circuit 11. The oscillator 15 supplies high-speed and low-speed clock signals to the central processing circuit 11.

The LCD display 26 displays the LCD display data from the central processing circuit 11. Lens information input section 2
7 is the lens A depending on the type of lens attached.
Information such as / M, open aperture, minimum aperture, and focal length is output to the central processing circuit 11. Patrone information input section 2
Reference numeral 8 outputs information such as the presence or absence of a cartridge and the sensitivity of the film to the central processing circuit 11. Switch information input section 29
Is the central processing circuit 1 for the information of the mirror up switch, the mirror down switch, the film switch, the release switch, the photometric switch, the rewind switch, the back cover switch, the UP / DOWN switch and the mode setting switch.
Output to 1.

The sequence control unit 32 includes a central processing circuit 1.
The signal 1 controls the mirror, the exposure of the film and the winding of the film. EEPROM 19
Is connected to the central processing circuit 11 via a communication line B, and reads / writes EEPROM data. The external data operating unit 20 is connected to the central processing circuit 11 via the terminal group C, and adjusts the camera, checks the functions, changes the specifications, inputs photographing information, and the like via the central processing circuit 11.

A DTC (computer) 30 is a computer having software for performing a camera function check RAM, a set dump of EEPROM, and the like. DTC30 is EE
When it is desired to write data to the PROM 19 by software, the writing mode is set, and if the stack is OK at this time, writing can be surely performed.

The interface 31 and the DTC 30 are
The 16-bit signals communicate with each other, and the time sequence of this communication is shown in FIG. Among them, the interface 31 has a function of converting a signal taken in from the camera 33 into a 16-bit signal and communicating with the DTC 30. "PCTL" and "PFLAG" in the figure are control signals for performing a data handshake,
16-bit input / output is executed by O15-0 "and" DI15-0 ". Whether or not the code is a test code is determined by the combination of" CTL0 "and" CTL1 ".

When data is output from the DTC 30, D
TC30 sets I / O to "L (low)" and
Before lowering L, the transmission data of "DO15-0" is fixed. Next, the PCTL is turned off and a data input request is output to the central processing circuit 11 via the interface 31. When the central processing circuit 11 detects “L” of PCTL, the central processing circuit 11 inputs “DO15 to 0” via the interface 31. Then, since the central processing circuit 11 side has fetched the necessary data, the PF
Shut down LAG. When the DTC 30 detects that PFLAG has dropped through the interface 31, DTC 30
TC30 is a PCT to enable communication of the next data.
Start up L. When the central processing circuit 11 detects “H (high)” of PCTL via the interface 31,
The central processing circuit 11 activates PFLAG to permit communication from the next DTC 30. The DTC 30 and the central processing circuit 11 use PCTL and PFLAG to perform a handshake in this manner, and the DTC 30 outputs a command or data to the central processing circuit 11. The distinction between command and data is DTC.
30 outputs as test code communication when CTL0 is "H", and as data communication accompanying the test code when CTL0 is "L". Whether or not there is a test request from the DTC 30 side can be checked based on whether CTL1 is "H" or "L". If "H", "test request"
If “L”, it means “no test request”.

When inputting data to the DTC 30, the DT
The C30 sets the I / O to the "H" state and causes the PCTL to fall. PCTL via interval timer 31
When the central processing circuit 11 detects "L" of "1", the central processing circuit 11 side outputs data corresponding to the command at that time to "DI15-0" via the interface 31. Then, through the interface 31, PFLAG
"L" of (P flag) is output to the DTC 30 to instruct data input. After that, the same handshake as described above is executed to cause the DTC 30 side to read the data.

FIG. 3A shows the connection relationship between the DTC 30, the interface 31, and the camera 33. The interface 31 can be operated by a chip enable signal (DCE) from the camera 33. Interface 3
1 is CTL1 and “DO1” according to the signal from the camera 33 side.
A data switching block 34 for switching data such as 5-8 "and outputting it to the camera 33, a parallel data for converting parallel data from the DTC 30 into serial data in synchronization with a serial clock from the camera 33, and outputting the parallel data to the data switching block 34. / Serial conversion block 35, latch pulse generation block 36 for generating a latch pulse according to a serial clock for each byte from the camera 33, serial / parallel conversion block for converting a serial signal into a parallel signal and outputting it to each latch block 38, the upper 8 bits of the “DI15 to 0” serial signal output from the camera 33 are latched and output to the DTC 30.
A bit latch block 37, a lower 8 bit latch block 39 which similarly latches the lower 8 bits and outputs it to the DTC 30, and a PFLAG signal latch block which similarly latches the PFLAG serial signal output from the camera 33 and outputs the PFLAG signal to the DTC 30. Has 40.

The communication terminal group D connecting the interface 31 and the DTC 30 includes a terminal 41 (CTL1) and a terminal 42.
(DO15 to 8), terminal 43 (DO7 to 0), terminal 44
(CTL0, PCTL, I / O), terminal 45 (DI15
~ 8), terminal 46 (DI7-0), and terminal 47 (P
FLAG).

The terminal group C for connecting the camera 33 and the interface 31 includes a terminal 48 (SI) and a terminal 49 (DC
E), a terminal 50 (SCK), and a terminal 51 (SO). The terminal 48 (SI) is pulled up by the resistor 53 on the camera 33 side. These terminals 48-51
Is a terminal that the user normally does not use,
It is not exposed to the outside of the camera 33.

The terminal 48 (SI) is a terminal for outputting data to the camera 33 side according to the serial clock.
CTL1 is a test request at "H" (Fig. 2), and CT
When L1 is selected, the data switching block 3 is provided on the camera 33 side.
It is inverted at 4, and "L" is output to the SI terminal. By inputting "L" of CTL1 on the camera 33 side, it can be determined that there is a test request from the DTC 30 side. The terminal 49 (DCE) is a chip enable and is a signal for requesting the input / output of data from the camera 33 to the interface 31. A request is made with "L", and a signal is not outputted from the interface 31 with "H". Can be banned as Terminal 50 (SCK)
Is a terminal that supplies a serial clock for serial communication between the camera 33 and the DTC 30 to the interface 31. The terminal 51 (SO) is a terminal for outputting serial data from the camera 33 to the interface 31.

The parallel / serial conversion block 35 includes
It is connected to the terminals 42 to 44 and the terminals 49 and 50, and outputs the serial data to the data switching block 34 in synchronization with the serial clock when the chip is enabled. This data switching block 34 has a terminal 41
Also, the output of the block 35, which is connected to the terminals 49 and 50, switches between the output of the CTL1 and the parallel / serial converted outputs output from the terminals 42 to 44 in accordance with the serial clock, and the terminal 48 (SI). Output to. The data switching block 34 is normally open and selectively outputs CTL1 until a clock is output due to chip enable. The latch pulse generation block 36 is connected to the terminals 49, 50 and 51 and outputs a latch clock to the upper 8-bit latch block 37, the lower 8-bit latch block 39 and the PFLAG signal latch block 40. The serial / parallel conversion block 38 is connected to the terminals 49 to 51, converts 8-bit serial data into parallel data, and outputs the upper 8-bit latch block 37 and the lower 8-bit.
8 bit parallel data is output to the t latch block 39 and the PFLAG signal latch block 40. The latch blocks 38, 39 and 40 latch the parallel data from the serial / parallel conversion block 38 according to the latch signal output from the latch pulse generation block 36.

The upper 8-bit latch block 37 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and DI1 is connected to the terminal 45.
Output 5-8 data. The lower 8-bit latch block 39 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and outputs DI7-0 data to the terminal 46. The PFLAG signal latch block 40 is connected to the outputs of the latch pulse generation block 36 and the serial / parallel conversion block 38, and outputs the PFLAG signal to the terminal 47.

FIG. 3B shows the timing of signals input and output from the above terminals. When the terminal 49 (DCE) is at "H", appropriate serial communication is performed and a knot cell (NOTSEL) state is set before the chip enable is applied. This knot cell is, so to speak, the central processing circuit 11
Is a preparatory stage for cutting the communication line between the EEPROM 19 and the BV detecting section 18 to allow the central processing circuit 11 and the external data operating section 20 to communicate with each other. Next, the camera 33 sets the chip enable (DCE) to "L". Until the serial clock is output in this state, the level of the CTL1 signal of the DTC 30 can be checked by the level of the SI terminal. SI terminal is "L"
In case of, there is a TEST request from DTC 30 (CTL1
= 1), conversely, when the SI terminal is "H", DTC
There is no TEST request from 30.

Next, when serial communication is performed, in the first serial communication, data relating to PCTL (including data of I / O and CTL0) is output from the terminal 48 (SI) to the camera 33 side. For this first 8-bit serial communication, data relating to PFLAG, that is, data indicating whether or not the P flag is set is output from the camera 33 from the terminal 51 (SO). When the serial clock is continuously output, DO7-0 and terminal 51 are output to the terminal 48 (SI).
When the data of DI7-0 is output to (SO) and the serial clock is output continuously, DO1 is output to the terminal 48 (SI).
5 to 8 and terminals 51 (SO) serially communicate data of DI 15 to 8. Serial communication is valid 0 to 3 times in 8-bit units after chip enable, and the communication can be stopped by turning off chip enable in the range within that range.

[0023] The flowchart shown in FIGS. 4 to 22, for explaining the operation of the camera 33 and DTC30 of this embodiment. 20 is a flowchart on the camera side except for FIG. 4 and 5 show the "VDD OFF loop", that is, the normal operation before the main power is turned on. First, "RES
The routine starts with the label "ET". Step S1
Then, the stack pointer is initialized, and in S2, "reset processing" such as RAM all clear, port input / output, output data setting and special register setting is executed, and the routine starts with the label "SW1CHK". move on.

In S3, the VDD ON flag is cleared, and in S4
Then, the stack pointer is reset, and in S5,
A subroutine starting with the label "TEST" is called to execute "TEST check processing". In S6, D
It is determined whether or not there is a test request from the TC 30, and if there is a request, the process proceeds to S7, and if not, the process proceeds to S8. In S8,
The UP / DOWN switch and the mode setting switch are monitored, and "UP / DOWN processing" such as data change is executed. In S9, "LCD display processing" for displaying the internal data set by the UP / DOWN processing or the like is executed. In S10, it is determined whether or not the photometric switch is turned on. If it is turned on, the process proceeds to S7 to set the VDD ON flag,
Otherwise, proceed to S11. In S11, it is determined whether or not the release switch is turned ON, and if it is turned ON, S7
If not, proceed to S12. In S12, V
Turn off DD and turn off power hold.
Execute timer interrupt enable. In S14, "power down processing" is executed to enter the power down mode. After a predetermined time, a timer interrupt occurs, and "timer interrupt processing" is executed in S15. Power consumption is suppressed by powering down between S14 and S15. S
In 16, the "timer interrupt disable" is executed and "SW1C
Loop to the label "HK".

In S7, the VDD flag is set and S1 is set.
In step 7, VDD is turned on to turn on the power hold and S1
In 8, the "VDD stable time wait process" for waiting for the peripheral circuit reset time and BV stable time is executed. In S19, a subroutine starting with the label "TEST" is called to execute "VDDON TEST processing", and S
In 20, the subroutine starting with the label of "SIEEP" is continuously called, and E for sequence calculation and sequence control is called.
"EEPR" for inputting EPROM data to RAM 14a
OM data input processing "is executed. In S21," lens check processing "for inputting mount pin information, lens ROM information, etc. is executed, and the flow advances to" RESTART ".

The main routine is shown in FIGS. 6 and 7. First, enter the routine starting with the label "RESTART",
In S22, the interval timer is initialized and S23 is set.
Then, using this interval timer, a process of setting data so that the power hold timer is set to 10 seconds is executed, and the process proceeds to the label “VDD LP”. S24
Then, the mirror UP / DOWN processing is executed, the lens check processing is executed in S25, and the "BV
A / D conversion processing "is executed. In S27," Patrone information input processing "is executed to input and convert data such as presence / absence of film and film sensitivity.
Based on the input data, "AE calculation processing" for obtaining TV value, AV value, etc. is executed. In S29, it is determined whether or not the test is permitted. If the test is permitted, the process proceeds to S30 to execute the "TEST process", and if not, the process jumps to S31.

At S31, L for the LCD display 26 is displayed.
The CD display processing is executed, and in S32, it is determined whether or not the release button is pressed. If the release button is pressed, the routine starts with the label "release processing". If not, the routine proceeds to S33. In S33, the time interval of the interval timer set in S22 is checked, the process returns to S32 until the set time elapses, and the process proceeds to S34 when the time elapses. In S34, a "power hold timer count process" is executed, and in S35, it is determined whether or not the count of the power hold timer is finished. For example, the operation returns to "VDD LP" and the processing is repeated.

Next, the "release process" will be described.
In S36, the analog signal of the BV detector 18 is output to the central processing circuit 11, and the A / D of the BV value immediately before the release is output.
Perform the conversion. In S37, AE calculation processing is executed,
In S38, mirror up processing is executed, and in S39,
Exposure control processing is executed, and in S40, mirror and film winding processing is executed. In S41, it is determined whether or not the end of the film has been detected. If detected, the process proceeds to S43, and if not, the process proceeds to S42. In S42, "FI
The subroutine starting with the label "LMCUP (Film Count Up)" is called to execute "Counting the number of films" and then returning to the label "RESTART." In S43, "Film rewinding" is executed
At 44, a subroutine starting with a label "FILM CLR (film clear)" is called to execute "film number clear processing" and jump to "SW1CHK".

FIG. 8 and FIG. 9 are flow charts showing the writing of data to the EEPROM 19. "FI
The routine starting with the label "LM CUP" is for counting up, and the routine starting with the label "FILM CLR" is for clearing the number of films.
In S45, the number of films in the RAM is counted up, and in S46, the number of films is set in the buffer. In S47, the address pointer in which the number of films is written in the EEPROM 19 is set. In S48, to clear the light (writing) flag of DTC30, rather than the writing of DTC30, the fact that writing in the normal camera mode software to set to the "SOE
Proceed to the routine beginning with the label "EP".

"SOEEP" means E from the DTC 30 side.
This is a subroutine called when writing to the EPROM 19 or the like. In S50, a subroutine starting with the label "SIEEP" is called to check whether the same data is currently written in the EEPROM before starting writing, and "EEPRO" is called.
M data input processing "is executed to check the state of the EEPROM data. In S51 and S52, the lower byte and the upper byte are checked, and if both are the same, a return is made and no processing is executed. If the stack is OK, it is determined in S53 whether the stack has become too deep due to a runaway, etc. As a result, if the stack is OK, the process proceeds to S54, and it is determined that the stack is abnormally deep. In this case, the operation returns and writing is not executed.Here, the EEPROM 19 has a capacity of "1 word x 64" in units of 1 word. Since this 1 word is composed of the lower byte and the upper byte, the lower data In other words, whether the lower 8 bits are the same as the data to be written, the upper data, that is, the upper 8 bits are to be written. Whether the same or not as there data, are to determine the.

The stack area set on the RAM 14b of the camera 33 has a sufficient capacity during normal operation, but if there is no return due to runaway or the like and only calls are repeated, that area will be immediately released. It will be crushed. Therefore, even if the write subroutine is called in such a state, it is not known whether or not the write data is normally stored in the buffer. Therefore, in the case of NO in S53, the process is returned.

In S54, it is judged whether or not the "DTC30 write (write) mode" is set, and if it is this mode, S5 is set.
If the writing is not in the DTC 30 but in the normal camera mode, the process proceeds to S55. That is, in the "DTC write (write) mode", writing is possible to all addresses of the EEPROM 19.

At S55, the film address is checked. Here, "FILM CUP" or "FILM
Check if the same address as the EP address pointer for the number of films set when entering from "CLR" can be detected as it is. And if it comes from "FILMCUP", it should be equal. However, if you call "SOEEP" etc. to write to an address other than the number of films, you cannot write because the film addresses are not the same. To be done.

In step S56, EEPROM chip enable is executed, in step S57, write permission communication (mode and address) to the EEPROM 19 is executed, and in step S58.
Then, turn off the EEPROM chip enable and set S59.
Now, execute the EEPROM chip enable, and execute S60
Then, the EEPROM write start communication (mode and address) is executed. In S61, the lower byte (lower 8
(Bit) data output communication is executed, and in S62, upper byte (upper 8 bits) data output communication is executed, and S63
Now, execute the write time wait of 15 mS and execute S6
In 4, the EEPROM chip enable is turned off and S6
In 5, the EEPROM chip enable is executed, and S6 is executed.
In step 6, write inhibit code communication (mode and address) is executed, and in step S67, the EEPROM chip enable is turned off and the process returns. In "FILM CLR", in S49, the number of films stored in the RAM 14a is cleared, and the process jumps to S46. Therefore, DT
During normal operation in the normal camera photographing mode not connected to C30, writing to the EEPROM 19 other than necessary is prohibited, and also when abnormal operation is detected, writing to the EEPROM 19 is prohibited.

A routine for reading data from the EEPROM 19 starting from the label "SIEEP" to the DTC 30 side will be described with reference to FIG. In S68, since other data such as the BV detection unit 18 and external devices exist in the communication line, the communication destination change mode is set to communicate with the EEPROM 19. In S69, the communication destination is E
Change to EPROM 19. In S70, the data communication mode is set, in S71, the EEPROM chip enable is executed, and in S72, the EEPROM read start communication (mode and address) is executed. The lower byte is input to the buffer in S73, the upper byte is input to the buffer in S74, and the EEPROM chip enable is turned off in S75.

The routine starting with the label "TEST" will be described with reference to FIGS. In S76, the PH request flag is set as the initial setting because there is no power hold request from the DTC 30. In S77, the test switch is input, and in S78, it is determined whether or not there is a test request, and if so, the process proceeds to S79, otherwise returns. In S79, it is determined whether or not the DTC error has already been detected. The DTC error is set, for example, when the DTC 30 outputs when a test code must be input next.

If a DTC error is determined in S79, the process jumps to S85, and if not, the process proceeds to S80. S80
Then, unless you output "1" to PFLAG, DTC
Since PCTL cannot be shut down from the 30 side,
First, "1" is output to PFLAG, and then the PCTL input process is executed in S81. In S82, PCT
It is determined whether L becomes "0", that is, whether there is a request from the DTC 30 side. If "0", the process proceeds to S83. If not, the RAM monitor is executed.
Proceed to S85.

At S83, VDD is checked to see whether the power-down loop or the main loop is present.
Judge whether the flag is ON. As a result, when it is determined that the power is in the power down loop, the DTC power hold flag is set in S84 so that the power is automatically set after returning, and S85 to S8 are set.
The RAM is monitored at 7 and the process returns. That is, S
At 85, the sampling permission / prohibition bit is judged. If the sampling permission / prohibition bit is determined to be valid, the process proceeds to S86, the monitor RAM address is input, and the RAM data of the body corresponding to the address is set in the buffer. In S87, 16-bit data output processing is executed, and the data in the buffer is the lower 8 bits (DI7-
0) is output.

If it is determined that the power is already turned on,
Switch to DTC communication mode, input PCTL,
Wait until PCTL becomes "0 (low)" (S88-S
90), when it goes low, proceed to S91. In S91, C
It is determined whether TL0 is set to "1". If it is set to "1", the process proceeds to S92, and if not, the process returns. S9
In 2, the test switch input process is executed, and in S93, it is determined whether or not there is a test request. If there is a test request, proceed to S94, otherwise return.

In S94, the input process of the DTC code is executed. If the lower part of the DTC code is the test code "FE", the process exits by return. (S
94-S96). When the lower order of the test code is neither "FE" nor "FF", the registration code is further determined. The test table shown in FIG. 13 includes “SUBC
HK ”,“ RAMDUMP ”,“ RAMSET ”,“ E ”
Codes of "EPDUMP" and "EEPSET" are registered. In case of other test codes, "D"
The routine starts with the label "TC ERR". In this routine, "0" is output to PFLAG in S99, and the DTC30 error flag is set in S100. That is, the handshake after that is disabled. Exit to the power-down "SW1CHK" routine.

In S101, it is determined whether the test code is OK. That is, data is output when the test code, for example, as shown in FIG. 20, the upper is "1
0 "and lower order are set to" 00 "to" 04 ",
I am checking this upper "10". If it is OK, the process proceeds to S102, the subroutine address for the test code is set in the pointer, and the test subroutine is executed in S103. If the test code is not OK in S101, the process proceeds to "DTC ERR".

In FIG. 14, "HANDOUT", "HAN"
The routines starting with the label "DIN" are shown. These routines are subroutines for actually inputting and outputting 16-bit data. First, "HAND OUT"
In the routine starting with the label of
Data is input, the process proceeds to S105, and it is determined whether or not PCTL is "0". If "0", the process proceeds to S106. If not, the process returns to S104. In S106, I / O data is input. In S107, it is determined whether or not the DTC 30 is in the input mode based on the input I / O data. If the DTC 30 is in the input mode, the process proceeds to S108.
Go to the routine starting with the label. In S108, 16
Bit data output processing is executed, and in S109, PF
"0" is output to LAG, and PCTL is input in S110. In S111, it is determined whether the PCTL has become "1" based on the input PCTL data. If "1", the process proceeds to S112. If not, the process returns to S110.
Repeat PCTL input. In S112, "1" is output to PFLAG and the process returns.

In the routine starting with the label "HAND IN", the PCTL data input process is executed in S113, and the PCTL data is input in S114.
It is determined whether TL is "0", and if "0", S
115, otherwise, return to S113, PCT
Repeat L input. In S115, it is determined whether the DTC is in the output mode based on the input I / O data. If the DTC is in the output mode, the process proceeds to S116.
R ”is executed. In S116, an input process of DTC30 data is executed, in S117, an echo back process is executed, and the process proceeds to S109.

Referring to FIG. 15 , the subroutine starting with the label "RAMDUMP" will be described. This routine
Is intended for outputting all the data written in the RAM 14b, it is executed by the output of the test code "1" from DTC30 shown in FIG. 20. In S123, the DTC data is input and processed, and in S124, the DTC data is input.
The start address of the RAM output to 30 is set in the RAM address pointer, the upper data of the DTC data is cleared in S125, and the PCTL input process is executed in S126. In S127, it is determined whether the PCTL has become "0" based on the input PCTL. If "0", the process proceeds to S128. If not, the process returns to S126.
Repeat PCTL input. In S128, it is determined whether or not the next test code is output. If the test code is a test code, the process returns. If not, the process proceeds to S129 to continue the RAM dump. In S129, the RAM data is prepared in the buffer, and in S130, "HANDOUT" is called to output the RAM data to the DTC 30, and S131
Then, the process from S126 is repeated with the RAM address pointer + 1.

With reference to FIG. 16 , the subroutine starting with the label "EEPDUNP" will be described. This routine
It is for outputting the data written in the EEPROM 19, is executed by the output of the test code "3" from DTC30 shown in FIG. 20. In S132,
Input processing of DTC data is executed, and in S133, DT
The start address of the EEPROM 19 output to C30 is set in the EEPROM address pointer. S13
In 4, call the "SIEEP" subroutine,
Input processing of EEPROM data is executed. In S135, the DTC communication mode is set, and in S136, the PCT is set.
L input processing is executed, and in S137, the input PCTL
Judge whether PCTL is "0" from the data,
If "0", the process proceeds to S138, and if not, S13.
Repeat 6 In S138, the output of the next test code is determined. If the test code is output, the process returns, and if not, the process proceeds to S139. In S139, "HANDOU
By calling "T", the EEPROM data is output to the DTC 30, the "EEPROM address pointer + 1" is set in S140, and the process returns to S134 to repeat the EEPROM dump processing.

[0046] According to FIG. 17, described the routine that begins with the label of "EEPSET". This routine is
It is a routine for executing writing to the ROM 19,
Is performed by the output of the test code "4" from DTC30 shown in FIG. 20. In S141, input processing of DTC data is executed, and in S142, when the EEPROM write mode is entered, the EEPROM from the DTC 30 is first read.
The M write start address is fetched and set in the EEPROM address pointer in the RAM 14b. S14
In 3, the DTC communication mode is set, and in S144, PTC is set.
Perform CTL input processing.

In S145, it is determined whether or not PCTL is "0" based on the input PCTL data. If "0", STL is executed.
146, otherwise return to S144, PCT
Repeat L input. In S146, it is determined whether or not the next test code is output. If there is a test code, the process returns, and if not, the process proceeds to S147. In S147, "HANDIN" is called to execute DTC data input processing, in S148, data is set in the EEPROM write buffer, and in S177, a DTC write (write) flag for writing to an arbitrary address is set. To do. In step S149, a subroutine starting with the label "SOEEP" is called to execute the EEPROM writing process. In step S178, the DTC write (write) flag is cleared, and in step S150, "EEPRO" is set.
The M address pointer + 1 "is executed, and the process returns to S143. That is, the process is performed so that the flag is set only when the EEPROM writing process is executed. When the number of films is usually counted, the DTC writing mode is not set. Be sure to clear the flag so that you can see that,
It is determined whether the TC write mode is set or not, and if the DTC write mode is not set, only the film address is written.

Referring to FIG. 18 , the routine starting with the label "RAM SET" will be described. This routine
This is a routine for executing writing to M14b.
Is performed by the output of the test code "2" from DTC30 shown in 20. In S151, input processing of DTC data is executed, and in S152, the start address of the RAM input from the DTC 30 is set in the RAM address pointer. In S153, PCTL input processing is executed, and in S154, PCTL data is input according to the input PCTL data.
It is determined whether TL is "0", and if "0", S
155, otherwise return to S153, PCT
Repeat L input. In S155, the output of the next test code is determined, and if there is a test code, the process returns, and if not, the process proceeds to S156. In S156, DTC data input processing is executed, and in S157, the DTC data is stored in the RAM designated by the address pointer in the RAM 14b.
The data is set, and the "RAM address pointer + 1" is set in S158, the flow returns to S153, and the RAM setting is repeated.

With reference to FIG. 19 , the routine starting with the label "SUBCHK" will be described. This routine is based on a large number of subroutine data stored on the camera 33 side.
20 is a routine for executing a subroutine corresponding to a subroutine address issued from the DTC 30 side.
The test code "0" is output from the DTC 30 shown in FIG. In step S159, the subroutine address is input from the DTC 30 and stored in the RAM 14b.
At 0, the code input from the DTC 30 is used as a subroutine address to execute the call, and the process returns.

Referring to FIG. 20 , the basic control routine of the DTC 30 side software "DTC SOFT" will be described.
This routine causes the camera 33 side to execute various operations based on the set test code, and the RAM 14b.
To the EEPROM, writing to the EEPROM 19, and the like. First, in S161, initial setting of the array dimension, data, etc. is performed, in S162, data display setting processing is executed, and in S163, test code input processing is executed. In S164, the input test code is determined, and if the test code is "0", the process proceeds to S165, and if the test code is "1", S16.
6 proceeds to S167 if "2", proceeds to S168 if "3", and proceeds to S169 if "4".

In step S165, a test code and a subroutine address are issued to the camera 33 side for checking the camera function by the DTC 30, and the camera 33 side
This is a case where a plurality of preset subroutines are executed. The subroutines referred to here are all those that normally operate when the user operates the camera, and also appear in FIGS. 4 to 10. First, in order to output the first test code to the camera 33 side, in order to set the state in which the test code can be output, CTL1 = 1 and CTL0 = 0 are set (see FIG. 2), and the test code “1000H” is output. After that, CTL1 = 0 and CTL1 = 1 are set to enter the subordinate data communication state. The subordinate data corresponding to the test code 1000H is a subroutine address that specifies an address in which a subroutine corresponding to the camera function to be checked is stored, and this is output. Based on this, the corresponding subroutine of the camera is executed. If it is necessary to set the data in the RAM before executing the subroutine, 100 described below will be used.
It can be set by the test code of 2H, and when the data is set in the RAM after the execution of the subroutine, it can be input to the DTC 30 by the RAM dump of 1001H which will be described later. Therefore, various check adjustments can be easily performed in combination with the execution of other subroutine addresses. According to this,
The software for operating the camera is made into a subroutine and stored, and by simply outputting and executing the address of the subroutine required for check adjustment, check adjustment can be performed easily and reliably. It is not necessary to install special software created for adjustment on the camera side, and the ROM memory capacity can be greatly saved.

Here, an actual example in which an arbitrary subroutine is executed from the DTC 30 side to check the reliability of the lens communication data in a short time will be shown. Normally, the camera communicates with the lens about once every 200 mS, so by executing this communication from the DTC 30, continuous communication becomes possible and the test time can be shortened to about 1/20. The test list (table
1) is shown.

[Table 1]

Further, in S166, the RAM is commanded.
This is a case where all the data in 14b is fetched to the DTC 30 side. First, the test code “1001H” is output to the camera 33 side, and the start address (= RAM address 0) is output. By continuously executing data input, all the data in the RAM 14b can be fetched from the RAM 14b to the DTC 30 side. S167
Is a case of writing data to the RAM 14b by a command. First, the test code "1002H" is output to the camera 33 side, and the start address is output. Continuously, I want to set the data in order from the start address
By outputting the AM data, the data can be written in the RAM 14b. S168 is a case where all the data in the EEPROM 19 is fetched to the DTC 30 side by a command. First, test code “1003H”
Is output to the camera 33 side, and the start address (= EEP
The address 0 of the ROM 19) is output. By continuously executing data input, all the data in the EEPROM 19 is transferred from the EEPROM 19 to the DTC3.
It can be captured on the 0 side. S169 is a case where data is written in the EEPROM 19 by a command. First, the test code “1004H” is output to the camera 33 side, and the start address is output. Continuously, EEPROM which wants to set in order from the data of the start address
By outputting the data, the data can be written in the EEPROM 19.

FIG. 21 shows a control routine starting with the label "SIOSUB". In S170, the address communication mode is set, in S171, the output processing of the address is executed, and in S172, the data communication mode is set,
In S173, data input / output processing is executed.

FIG. 22 shows a routine starting with the label "NOTSEL". In S174, the address communication mode is set, in S175, the output process of the NOTSEL address is executed, and in S176, the data communication mode is set.

[0056]

As described above, according to the present invention,
Software for executing normal camera operations has been made into a subroutine so that it can also be used as software for checking and adjusting camera functions, so software dedicated to checking and adjusting on the camera side is minimized, and the ROM on the camera side is compressed. Therefore, the ROM area that can be used as a camera can be increased accordingly. As a result, the quality of the product software can be improved, the development amount of the software can be reduced, and the product can be commercialized more quickly.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1A is a diagram schematically showing a control block of the present embodiment.

FIG. 1B is a diagram schematically showing a DTC and an interface.

FIG. 2 is a time sequence during communication between the DTC side and the camera side.

FIG. 3A is a block diagram showing a connection status of a DTC, an interface, and a camera.

FIG. 3B is a time sequence showing the timing of signals input to and output from the DTC, the interface, and the camera of the embodiment.

FIG. 4 and FIG. 5 are flowcharts showing a routine that starts with a label “RESET” in the same embodiment.

6 and 7 are flowcharts showing a routine that starts with the label "RESTART" in the embodiment.

8 and 9 are flowcharts showing a routine that starts with the label "FILMCUP" in the embodiment.

FIG. 10 is a flowchart showing a routine that starts with a label of “SIEEP” of the embodiment.

FIG. 11 and FIG. 12 are flowcharts showing a routine that starts with the label “TEST” in the embodiment.

FIG. 13 is a diagram showing a “test code” of the same example.

FIGS. 14A and 14B are “HANDOUT” and “HAND” of the embodiment.
6 is a flowchart showing a routine starting with a label of “IN”.

FIG. 15 is a flowchart showing a routine that starts with a label of “RAMDUMP” in the embodiment.

FIG. 16 is a flowchart showing a routine that starts with a label “EEPDUMP” in the embodiment.

FIG. 17 is a flowchart showing a routine that starts with a label “EEPSET” in the embodiment.

FIG. 18 is a flow chart showing a routine that starts with the label “RAMSET” in the embodiment.

FIG. 19 is a flowchart showing a routine that starts with a label of “SUBCHK” in the embodiment.

FIG. 20 is a computer flowchart showing a routine that starts with the label “DTCSOFT” in the embodiment.

FIG. 21 is a flowchart showing a routine that starts with a label of “SIOSUB” in the embodiment.

FIG. 22 is a flowchart showing a routine that starts with a label “NOTSEL” in the embodiment.

[Procedure 3]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

FIG. 1B

[Fig. 2]

FIG. 3B

[Fig. 13]

FIG. 19

FIG. 1A

FIG. 21

FIG. 22

FIG. 3A

[Figure 4]

[Figure 9]

[Figure 5]

[Figure 10]

[Figure 6]

[Figure 7]

[Figure 8]

FIG. 11

[Fig. 12]

FIG. 14

FIG. 15

FIG. 16

FIG. 17

FIG. 18

FIG. 20

Claims (1)

[Claims] 1. A camera having a central processing circuit for performing main processing of the camera, and a peripheral circuit connected to the central processing circuit; the camera being connectable to the central processing circuit, the camera being provided through the central processing circuit. A computer having a command for checking and adjusting functions, and a subroutine software for operating the central processing circuit and peripheral circuits in the command for checking and adjusting the functions of the camera, which is provided in the central processing circuit. A camera check system having a function of executing an address by executing an arbitrary subroutine from the computer.