JPH0752842B2 - Phase Lock Loop Integrated Circuit - Google Patents

Description

The present invention relates to a frequency synthesizer PLL IC, and more particularly to a PLL IC provided with a control circuit for stopping a function while a power supply voltage is applied.

[Conventional technology]

Conventionally, this type of PLL IC has an internal biased inverter 24 for crystal oscillation circuit and a reference frequency divider 2 as shown in FIG.
5. Input the signal from the voltage controlled oscillator. Inverter 28 with internal bias, variable divider 29, phase detector
31, a charge pump consisting of an inverter 32, a P-channel transistor 33 and an N-channel transistor 34 was constructed using CMOS technology.

[Problems to be solved by the invention]

Since the conventional PLL IC described above does not consider stopping the function while the power supply voltage is being applied, the internal resistance 23,2
In the CMOS inverters 24 and 28 that have been fed back by 7, when the input is open, the input is biased to about half of the power supply voltage, and both the P-channel and N-channel transistors that make up the inverter become conductive and a large through current flows. However, there is a drawback that the requirement of low current consumption cannot be satisfied.

As a countermeasure against this, the switch 44
There is also an example in which the feedback resistor 43 is cut off by, and at the same time, the input of the inverter 45 is pulled down to the lowest potential by the switch 42 via the resistor 41. In this example, if the input signals are not stopped at the same time, it operates as an inverter when the input amplitude is large, and the pull-down resistor 41 acts as a load, which causes a heavy load when viewed from an external signal source. However, when a high precision crystal oscillator is used, there is a drawback that an external gate circuit is required to stop the input. Also, because the output of the charge pump does not become high impedance, the output voltage of the external low-pass filter is not held each time the operation is stopped, and at the start of operation, it takes a time constant for the output voltage to rise every time. There is a drawback that the startup is slow at the time of ass operation.

[Means for solving problems]

The PLL IC of the present invention is inserted in series with an input terminal for stopping the operation, a gate circuit for setting the output of the charge pump to a high impedance, and a power source of the first stage inverter for inputting the reference signal and the variable frequency signal. And a switch inserted in series with a feedback resistor provided between the input and output of the inverter, a switch provided between the first-stage and second-stage inverters, and a ground.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention.

Switches 110 and 112 are off and switch 113 is on when control input 124 is low. Therefore, regardless of the input level of the variable frequency input 109, the power source of the first-stage inverter 111 is turned off, and the output is fixed to the low level by the switch 113. In other words, almost no operating current flows at the input, and the input impedance is close to infinity and the input is completely cut off so that it will not be transmitted to the next stage. On the contrary, when the control input 124 is at a high level, the switches 110 and 112 are turned on, the first stage inverter is biased by resistance feedback, and an AC amplifier is formed by inserting a capacitor in series with the input. Also switch 11
3 is off and the signal is transmitted to the next stage without any problem.

Obviously, the reference input 101 also works. Since the inverter output of 102 is added, a crystal oscillator can be configured by connecting a crystal oscillator between 101 and 102. 124 Control input allows switching between oscillation or amplification and operation stop.

The output of the phase detector 119 is configured to be high level together with the two outputs when the phases of the two inputs match. When the control input 124 is at high level, the output of the phase detector is transmitted to the P-channel transistor 122 and the N-channel transistor 123, and both transistors are off in phase matching. Either one of the transistors is turned on according to the phase difference and charged or discharged with respect to the low pass filter connected to the error output terminal 126, and the frequency of the voltage controlled oscillator is controlled by the smoothed DC output, PLL is configured.

When the control input 124 is at a low level, the gates 120 and 121 turn off both the transistors 122 and 123 regardless of the output of the phase detector. As a result, the current consumption of the IC can be ignored regardless of the circuit connected to the output terminal 126. Since the low-pass filter is neither charged nor discharged, the output voltage of the low-pass filter is held for a certain length of time, depending on its configuration, so initial charging is not required when the IC operation is restarted. The time required for the loop operation to return to the normal state can be shortened.

〔The invention's effect〕

As described above, the present invention minimizes the current consumption regardless of the presence / absence of an external signal and the load condition by stopping the operation of the reference input, variable input, and charge pump output of the PLL IC by controlling the control terminal. In addition to holding down, there is an effect that the operation is resumed after a short time, that is, the rise time at the so-called assault operation can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the internal arrangement of a PLL IC according to an embodiment of the present invention.
FIG. 3 is a block diagram of a conventional PLL IC, and FIG. 3 is a block diagram of an input unit in the conventional PLL IC configured to stop the operation of the input unit.

Claims (1)

[Claims] 1. A reference frequency divider, a variable frequency divider, and a phase detector, wherein the output of the phase detector is configured to have a high impedance by a control input, and the input side of the reference frequency divider and the variable frequency divider. An inverter is provided for each of the inverters, and each inverter has a first
And a second switch provided in series with the feedback resistor and a third switch provided between the output and the ground, the control input turning on the first and second switches, and the third switch. Is off and the first and second switches are off and the third switch is on when there is no control input.