JPH0752385A - Protecting circuit for head of bubble-jet printer - Google Patents

Abstract

PURPOSE:To provide an inexpensive head protecting circuit of a bubble jet printer in a simple constitution which is capable of protecting a head even when a discharge signal not satisfying an impressing pulse width and an impressing pulse cycle allowed for the BJ(bubble jet) head is output from a CPU. CONSTITUTION:When a discharge signal S1 becomes a Hi level, a current runs in a driving part 5, thereby supplying electricity to a heater resistance rH1. At the same time, a capacitor C1 is charged. A predetermined time later, charging of the capacitor C1 is completed and the current to the driving part 5 is stopped, whereby the supply of electricity to the heater resistance rH1 is stopped. When the discharge signal S1 becomes a Lo level, electric charges accumulated in the capacitor C1 are discharged via a discharge resistance R1. Even when the discharge signal S1 is turned to the Hi level during the discharging period, the capacitor C1 becomes immediately saturated, so that the flow of the current to the driving part 5 is promptly shut and also the supply of electricity to the heater resistance rH1 is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a head protection circuit for a bubble jet printer.

[0002]

2. Description of the Related Art Printing control of a bubble jet (hereinafter referred to as "BJ") printer having a head having a resistor for generating thermal energy for causing film boiling in ink as energy used for ejecting ink. When doing
In order to prevent damage to the print head, the ejection signal applied to the print head has restrictions such as voltage, pulse width (application time) and frequency (application cycle). Furthermore, when signals are simultaneously applied to a plurality of heads, the head temperature rises and the heads are destroyed, so it is necessary to stagger the time and sequentially apply ejection signals to each head.

Conventionally, as shown in FIG. 5, the ejection signal S output from the CPU 1 is output to the resistors r _{H1 to} r _Hn in each head.
1 to Sn are turned on by noise or the like to prevent the head pulse width from exceeding the permissible range of the pulse width of the head and causing destruction of the head.
1, 52 are controlled to synchronize the ejection signals S1 to Sn and the head power source 8 is turned on / off to protect the head. That is, conventionally, the ejection signals S1 to Sn and the power control signal S0 output from the CPU 1 are controlled by a program so as to be a power ON signal and an ejection signal power OFF signal. The head is protected by a program by repeatedly outputting the series of signals.

Further, in another conventional example, without controlling the power supply, as shown in FIG. 6, the capacitors C ₁ to C _{1 are connected} to the respective signal lines for outputting the ejection signals S 1 to Sn from the CPU 1 to the drive unit 5. by inserting the C _n in series thereby achieving the protection of the head. In this example, even when the ejection signals S1 to Sn are locked in the ON state, the capacitors C _{1 to} C _n are charged by the ejection signals S1 to Sn and are in a saturated state, so that the potential of the input terminal of the drive unit 5 is changed. It becomes zero. Therefore, even if the ejection signals S1 to Sn are in the ON state, the potential of the input terminal becomes zero and the output of the driving unit 5 is in the OFF state after a predetermined time, so that the head can be protected.

[0005] Here, the capacitor C ₁ ~
The charging time of C _n , that is, the product of the capacitances of the capacitors C _{1 to} C _n and the input resistances r _{B1 to} r _Bn of the drive unit 5 (time constant)
, The capacitors C _{1 to} C _n and the resistors r _{B1 to} r so that the predetermined time is within the allowable range of the pulse width.
Choose the value of _Bn .

[0006]

However, the conventional example shown in FIG. 5 in which the power source is turned on / off according to the ejection of each head has the following problems.

When any one of the ejection signals S1 to Sn and the power supply control signal S0 are locked in the ON state, the head cannot be protected.

It is necessary to control ON / OFF of the power source every time a plurality of ejection signals S1 to Sn are shifted and output.
Since the overhead time becomes long with respect to the ejection signal pulse width (several μs), the total print processing time becomes long.

Further, in the conventional example shown in FIG. 6 in which the capacitors C _{1 to} C _n are inserted in series for each of the individual signal lines, the control overhead time is reduced, but the ejection signals S 1 to Sn are reduced. Either one is ON in a short cycle
When / OFF is repeated, the charge accumulated in the capacitor in the OFF state is instantaneously discharged and all of the ON signal passes through the capacitor, so the frequency (cycle) constraint can be satisfied. The head cannot be protected without it.

An object of the present invention is to provide a bubble jet having a simple structure and capable of protecting the head even if an ejection signal which does not satisfy the applied pulse width and applied pulse period allowed for the BJ head is output from the CPU. It is to provide a head protection circuit for a printer.

[0011]

In order to achieve the above object, the present invention provides a controller for outputting an ejection signal of a head of a bubble jet printer, and a head drive for applying a predetermined voltage to the head according to the ejection signal. A capacitor connected in series with the circuit and a discharging means for discharging the electric charge charged in the capacitor through a discharging resistor, and the capacitance of the capacitor is selected according to an allowable range of continuous energizing time of the head. However, the value of the discharge resistance is selected according to the allowable range of the drive cycle of the head.

[0012]

According to the present invention, when the ejection signal output from the control section is turned on, the output voltage charges the capacitor. When the capacitor is charged and saturated,
Since the input of the head drive unit becomes zero, the energization of the resistance in the head is stopped. When the ejection signal is turned off, the electric charge accumulated in the capacitor by the discharging means is discharged through the discharging resistor, so that the voltage across the terminals of the capacitor gradually decreases. As described above, in the present invention, the current path differs when the capacitor is charged and when it is discharged. And
The charging time of the capacitor is selected so that the energizing time to the head is within the allowable range, and the discharging time of the capacitor via the discharge resistor is selected so that the driving cycle of the head is within the allowable range. In addition, the head is not destroyed by the abnormality of the ejection signal.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, the ejection signal S1 of the CPU 1
Each output port for outputting .about.Sn is composed of transistors 2 and 3, and when this output port is at the Hi level, the ejection signal is in the ON state, and when it is at the Lo level, the ejection signal is in the OFF state. Diode 4, resistance R ₁
The capacitor C ₁ constitutes a head protection circuit, and _one head protection circuit is provided for each signal line that outputs the ejection signals S1 to Sn. Transistor T
₁₁ , T ₂₁ , input resistance r _B1, and pull-down resistances r ₆ , r
Reference _{numeral 7} constitutes a drive circuit for the heater resistance r _H1 . One drive circuit is provided for each of the heater resistances r _{H1 to} r _Hn , and the drive unit 5 is configured by a plurality of these drive circuits. Reference _numerals r _{H1 to} r _Hn are heater resistances, one for each head, and 8 is a power supply for driving the heads.

Here, the capacitance of each of the capacitors C _{1 to} C _n is
The value is selected such that the capacitor is saturated by the ejection signal within the allowable range of continuous energization time to each heater resistance r _H1 to r _Hn . The values of the discharge resistors R _{1 to} R _n are

[0016]

[Equation 1]

The value is selected so that the discharge of the capacitors C _{1 to} C _n does not end within a period equal to or less than the minimum driving cycle allowed for the heater resistances r _{H1 to} r _Hn .

Next, the operation of the embodiment configured as described above will be described.

When the CPU 1 starts the printing operation, it moves the BJ head to a predetermined printing position. Next, the CPU 1 outputs a predetermined signal of the ejection signals S1 to Sn by turning on the transistor 2 and turning off the transistor 3 which form the corresponding output port. For example, when the ejection signal S1 is output, the transistor 2 forming the output port of the ejection signal S1 is turned on, and a Hi level signal is applied to the diode 4. In such a state, the diode 4 is forward biased, so that the ejection signal S1 passes through the diode 4 and reaches the capacitor C ₁ and the resistor R ₁ . Here, since the capacitor C ₁ is in a non-charged state, the signal S1 passes through the capacitor C ₁ and the driving unit 5
To enter. In such a state, the resistance R ₁ is the resistance r _B1 ,
Since a large value is set as compared with r ₆ and r ₇ , a minute current flows through the resistor R ₁ , but its influence can be almost ignored. The ejection signal S1 that reaches the drive unit 5 receives the input resistance r _B1.
After that, the transistors T ₁₁ and T ₂₁ are turned on, so that a current flows from the power source 8 to the heater resistance r _H1 and ink is ejected. As described above, when the ejection signal S1 is at the Hi level, the capacitor C ₁ is charged by the ejection signal and the voltage between its terminals rises.

Next, the transistor 2 is turned off, the transistor 3 is turned on, and a Lo level signal is output from the terminal of the CPU 1 via the transistor 3 and applied to the diode 4. In such a state, the diode 4 is reverse-biased, so that the diode 4 is electrically opened. Then, the electric charge charged in the capacitor C ₁ is discharged through the input resistance r _B1 of the driving unit 7, the pull-down resistances r ₆ and r _{7 of} the transistor, and the discharge resistance R ₁ . At this time, the transistors T ₁₁ and T ₂₁ by the voltage drop of the current flowing through the pull-down resistor r _6, r ₇ of the drive unit 7 is turned OFF state heater resistor r _H1
No current flows through the ink, and the ink ejection ends.

The operation when the normal ejection signal S1 is output has been described above. Next, the ejection signal in the abnormal state is C
The operation of this embodiment when output from PU1 will be described.

First, a case where the ejection signal output from the CPU 1, which is the first cause of head destruction, is held in the ON state and current continues to flow through the heater resistance r _H1 will be described. In the state where the ejection signal S1 from the CPU1 is held in the Hi level state, the current _first flows from the transistor 2 through the diode 4, the capacitor C1 and the input resistance r _B1 and through the transistors T ₁₁ and T ₂₁ in the driving unit 5. However, the value of this current gradually decreases as the capacitor C ₁ is charged. And capacitor C ₁
At the end of charging, the current stops flowing and the transistors T ₁₁ and T ₂₁ in the drive unit 5 are turned off. Therefore,
Since no current flows through the heater resistance r _H1 , the head is protected.

This state is shown in FIG. Figure 2 (a) shows CP
The state of the ejection signal output from U1 is shown in FIG.
Shows the state of the signal input to the drive unit 5.
As the capacitor C ₁ is charged, the potential of the signal input to the drive unit 5 gradually drops. The time required for this drop (charging time) is approximately proportional to the product (time constant) of the capacitance of the capacitor C ₁ and the input resistance r _B1 .

Next, a case where the pulse width of the ejection signal output from the CPU 1, which is the second cause of head destruction, is normal but its cycle is shorter than the head specification will be described. For example, the ejection signal S1 output from the CPU 1 is H
When shifting from the i level to the Lo level, the capacitor C ₁
The electric charge charged in is gradually discharged through the resistor R ₁ . When the discharge signal S1 during the discharge period of such capacitor C ₁ becomes Hi level, in order to discharge the capacitor C ₁ which is charged by the previous Hi level signal is not finished, the capacitor C ₁ is charged immediately As a result, no current flows through the drive unit 5. Therefore, the ejection signal S having a normal cycle
An abnormal ejection signal S is output within a predetermined period after 1 is output.
1 is output from the CPU 1, its ejection signal S
Since the current flowing through the heater resistance r _H1 is immediately cut off by ₁ , the head is not destroyed by such an abnormal signal. Since the above-mentioned predetermined period is almost proportional to the product (time constant) of the capacitance of the capacitor C ₁ and the discharge resistance R ₁ , this value is set to the head specification (condition for the cycle).
You can set it according to.

FIG. 3A shows the state of the ejection signal when the CPU 1 outputs the abnormal signal P'between the normal ejection signals P ₁ and P ₂ , and FIG. 3B shows the state. The state of the signal input to the drive unit 5 corresponding to it is shown.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a circuit diagram showing the configuration of the second embodiment, and the same reference numerals as those in FIG. 1 denote the same components. The difference between the second embodiment and the first embodiment is that C
That is, the ejection signal output port of PU1 is configured by the open drain transistor 12. With this structure, it is not necessary to provide the diode 4 required in the first embodiment. In addition, in the second embodiment, the discharge resistor R _{1 also} serves as a pull-down resistor of the open drain transistor 12.

In the second embodiment constructed as above,
For example, when the ejection signal S1 is at the Hi level,
Current is transistor 12 → capacitor C₁ → Input resistance r_B1
→ Transistor T₁₁, T_{twenty one}And capacitor C₁ Is full
Charged, capacitor C₁ The charge charged to the discharge signal S
When 1 is Lo level, discharge resistance R₁ , Input resistance r _B1
And pull-down resistance r₆ , R₇ Be discharged through.
The other operations are the same as those in the first embodiment, and the description thereof is omitted.
Is omitted.

[0029] As in the well first embodiment in this second embodiment, the charging time of the capacitor C ₁ is a capacitor C ₁
The capacity and the product of the input resistance r _B1 of (time constant), the discharge time capacitor C _1, the discharge resistance and capacitance of the capacitor C ₁ R ₁
, The value is proportional to the product (time constant) of the input resistance r _B1 and the pull-down resistances r ₆ and r ₇ , so by setting each time constant to correspond to the pulse width and pulse cycle of the head specifications. It is possible to protect the head.

[0030]

As described above, according to the present invention,
Since the time condition can be easily added to the conduction of the ejection signal with a simple structure at low cost, the head is applied to the abnormal signal which does not satisfy the applied pulse width and the applied pulse period of the BJ head specifications. The current can be prevented from flowing and the head can be protected.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention.

2A is a waveform diagram showing an example of an abnormal ejection signal output from the CPU 1 shown in FIG. 1, and FIG.
It is a waveform diagram which shows the state of the input signal of the drive part 5 corresponding to (a).

3A is a waveform diagram showing an example of an abnormal ejection signal output from the CPU 1 shown in FIG. 1, and FIG.
It is a waveform diagram which shows the state of the input signal of the drive part 5 corresponding to (a).

FIG. 4 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional example.

FIG. 6 is a circuit diagram showing the configuration of another conventional example.

[Explanation of symbols]

1 CPU 2, 3, 12 transistor 4 diode 8 power supply C _{1 to} C _n capacitor R _{1 to} R _n discharge resistance r _{B1 to} r _Bn , r ₆ , r ₇ resistance r _{H1 to} r _Hn heater resistance T _{11 to} T _1n , T _{21 to} T _2n transistors

Claims (1)

[Claims] 1. A capacitor connected in series between a control unit that outputs an ejection signal of a head of a bubble jet printer and a head drive circuit that applies a predetermined voltage to the head according to the ejection signal, and a capacitor connected to the capacitor. And a discharging unit configured to discharge the charged electric charge through a discharging resistor, wherein the capacitance of the capacitor is selected according to an allowable range of continuous energizing time of the head, and the value of the discharging resistor is the driving cycle of the head. A head protection circuit for a bubble jet printer, which is selected according to an allowable range.