JPH07509795A - Advanced large-scale parallel computer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Advanced large-scale parallel computer This invention is based on contract box MDA-972-90-C-0022 with government support. It was done accordingly. The government has certain rights in this invention.

This invention is useful for large-scale parallel computers, especially those capable of multi-user time-sharing operations. Regarding computers.

Background of the invention A supercomputer that performs large sequential and parallel operations Although both methods are known in the art, massively parallel operations , calculations that require very large amounts of data computation and data communication to be performed in real time. Preferred for applications that rely heavily on calculations. Examples of such applications include weather modeling and medical imaging. Such complex scenarios encountered in such applications Real-time analysis in O's deals with very large data sets.

Prior art Princeton engine (Princeton [!ngineXPE ) is a single instruction multiple data (SIMD) linear array processor. There is. Its linear array processors range from 64 to 2048 processors. 64 increments, and the maximum configuration is scalable to 14MHz instruction clock. , achieving a computation rate of 28.672 million instructions per second (MIPS). Each process The server has local memory and communicates with its neighbors via two two-way channels. I can believe it. 14 and 1.8Gbps as input and output data rates, respectively is obtained. The host of this PR is Apollo/Mentor Graphics Workstation (Apollo/Mentor Graphics Workstat ion) and a high-resolution monitor is used to view the output results.

Each processing element PEO to PEn-1 of the above PE has seven independent internal 1 6-bit data path, 16-bit ALU, 16-bit multiplier, 64 elements 3-port register stack, 16-bit communication port; and up to 640 bytes Contains external SRAM local memory. The register file allows reads to the file. One address port for read-only access and reading of that file Or it has a second address port for writing. Inter-processor communication bus (IP C) allows data to be exchanged between adjacent processors within one instruction cycle. each life Up to six simultaneous operations (input via the 110 bus) or output, simultaneous read and write in register file, one AL U operations and local memory access).

Input data is stored in local memory of each processor for each scan line 0 to v-1 of the video. Recorded in MO to Mn-1, one pixel per processor. subordinate So, over a frame period, one pixel column of the video frame is assigned to each local recorded in memory. The local memory is 8 bits for a frame of 1024 lines. This is sufficient to record up to 640 columns in pixels. The functional diagram 100 in FIG. shows how deoframes are distributed across local memory . Each corresponding video frame sequence O to z-1 is stored in the same local memory. recorded. Therefore, in a temporal algorithm, between processors, i.e., adjacent No communication between local memories of processors is required. Horizontal filters and statistical aggregation The operation requires data communication between processors via the 1Pc 200.

IPC has four modes: normal, bypass, and broadcast. ) transmission and broadcast reception. Normal communication is linear between adjacent ones in a connected array. Data is on IPC channel is loaded in one instruction and shifted to the left or right in the next instruction. This mode is very useful for computing nearest neighbors.

In some cases, it is desirable to perform the contiguity operation on a subgrid of the original array.

This thinning is achieved without compressing the array elements into a smaller concatenated region. can be done. Rather, the processor is bypassed and new adjacent connections between the desired regions bring about. The left and right shift operations are passed through a connected pattern that is bypassed.

In Figure 2, PB represents analog and digital sources and destinations. It is interfaced via controller 200. Input to parallel array and output data channels are 48 bits and 64 bits wide, respectively.

These channels are clocked at 28MHz and have six analog-to-digital interface converter (ADC) and seven digital-to-analog converters (DACs). source. The host computer is used for system or algorithm testing. It has digital access to load or receive data on these buses.

Controller 200 also provides user-selectable locks for ADCs and DACs. do. Three independent input clocks and four independent output clocks are possible. child This allows several different data sources to be read and processed simultaneously. , can be displayed and compared. The output can be displayed on various displays, e.g. Incorporate into the background within tram analyzers and embedded real-time system hardware It can be rare.

The output from parallel processor 202 is a special output, multiport, i.e. Bitslice I10 Random access memory (RAM) built into the IC ) structure 204 is user programmable. local memory access is reduced due to this unique output structure. The output data stream is additionally can be returned to the input of a parallel array for further processing. This feature allows radar processing ( Enables real-time transposition, which is effective for corner turns) and high-speed rotation of large 3D data sets. scale of advanced problems such as radar processing and television simulation. The growth of these prior art massively parallel supercomputer communications and computation , and P(! is insufficient to give its real-time solution. It's not a minute.

Therefore, the bandwidth and computation required to provide solutions to such computational power problems Performance (I10 band up to 1200MBytes/sec and 9.6Tera Larger scale parallelism with both peak computation rates up to ops/sec Supercomputers are needed. Furthermore, sequential supercomputers Time-division Malthusa operation is possible, but the massively parallel processors of the prior art A computer cannot do this.

Outline of the invention A parallel computing system consisting of N blocks, each containing M processors. is listed. Each processor has an arithmetic logic unit (ALU), local memory and human power/output (Ilo) interface. Each block also contains a controller that is programmed to give the same group of instructions. It is connected to each of the M processors in the block. Parallel computing system also I'm N-bu. The host processor divides these blocks into at least the first and second blocks. into block groups, each group containing P blocks. P pieces For each group with blocks of A group is given by the host processor to each of M times P processors. Ru.

Brief description of the drawing Figure 1 shows how a video frame is stored in the memory of a conventional Princeton engine (PE). It shows what is stored in the file.

Figure 2 shows how a host computer can be used to test a system or algorithm. Digital access to load or receive data on the trollerbus 1 shows a configuration in a conventional PE that can be used.

Figure 3 is a schematic diagram of the Sarnoff Engine (SE). be.

Figure 4 shows the connection of the SE host, controller, local memory, and 170 functions. It is an enlarged view of an engine block (EB) showing.

FIG. 5 shows the physical layout of the system modules.

FIG. 6 shows the processor configuration of the SH.

Figure 7 shows the use of the SE stride register. It shows.

Figure 8 shows SE Sen. Modulo Arithmatic Mo An example of de) is shown.

Figure 9 shows an example of the SH bounding mode. There is.

FIG. 1O shows the SE processor resource usage table.

FIG. 11 shows an example of matching two back data words.

FIG. 12 shows a match sequence and its corresponding template.

Figure 13 is a diagram showing matches and matches found between data sequences. 14 shows an example of conditional locking.

FIG. 15 shows four different modes of processor instruction words.

Figure 16 shows four different examples of IPc operations.

Figure 17 shows the SE input/output memory controller (Inputoutput M memory Controller’l (IOMc) input slice (4 slices) chair/chip).

FIG. 18 shows the output slices (4 slices/chip) of IOMc.

FIG. 18a is a block diagram of a preferred image vault (IV) interface circuit. It is.

Figure 19 shows the I10 data format.

FIG. 20 shows the video data format.

Figure 21 shows the data input captured by the input FIFO (first in, first out). are doing.

FIG. 22 shows an example of an input timing sequence.

FIG. 23 shows two diagrams of a processor that handles multiple pixels.

Figure 24 shows the transfer of data from the input FIFO to local memory.

FIG. 25 shows the FIFO input timing sequence.

Figure 26 shows loading output FIFO data from the data output channel. ing.

FIG. 27 shows the transfer of data from local memory to the output FIFO.

Figures 27a to 27i describe the operation of the input and output FIFOs. FIG. 2 is an array diagram of a memory arrangement useful for.

Figure 28 shows the local 0R (LOR) bus.

Figure 29 shows a controller synchronization switch.

Figure 30 shows the conceptual grooving of the controller.

FIG. 31 shows the configuration of a synchronous switch for the controller.

FIG. 32 shows an example of barrier synchronization.

Figure 33 shows the elements of the operating system.

DESCRIPTION OF THE PREFERRED EMBODIMENT Some acronyms are used herein to facilitate the description of the invention. A list of alphabets is attached.

The SE preferably has a 32-bit processor, which has 15 independent processors per instruction. programmable overlay and twice the memory bandwidth (l processor (2 local memory ports per device). Processor at maximum system The total number is 8192, and each processor has a computational data rate of 819 MIPS. 100MHz clock to achieve 9.6x1012 operations/second (Ions instruction cycle). another big The improvement is S[! is multiple instruction multiple data (Multiple In5tructi on Multiple Data There is one controller for each of the processors, and each controller Different instruction streams can be broadcast to processors. This architecture -In the organization, synchronization between controllers is obtained with hardware support and 128MIM Provides up to D instruction stream. SE can also operate in multi-user mode and mode allows some real-time and non-interference between applications. To support real-time applications, the system can time-share this device. may be configured to do so. The system also uses Can be reconfigured into several smaller systems. Figure 3 is a high-level schematic diagram of this device organization. It is.

lOOMI (In order to realize the z system clock, the controller function must be integrated. processor and must be located close to the processor. controller 300 broadcasts instructions to processing elements 302 and processes and signals respond to maintain information. Each controller has instruction memory and program code. Contains a microsequencer that directs control flow. About running processes information is maintained in process control memory. some processes S3゜2, local memory 304, I10 function 306, and controller function By using redundant slices containing The requirement to enable is further fulfilled.

The shaded area of FIG. 3 shows redundant slices of the EB within the SE. There are 64 EBs. Processors, their respective local memory, 170 functions, and host work It consists of a controller function including an interface with station 308.

EB has one controller IC5 program memory module, 16 processors IOMc Ic, 16 local memory modules, and 16 IOMc Ic Physically consists of a multi-chip module containing

FIG. 3 also shows the processor connected to IV320, which V is a large second storage array accessible from each processor's IOMC. . The IV320 has distributed disk recording and works with terabytes at the system level. It has a capacity of megabytes at the processor level. each processor system-level data rate of 4 MB/'s at Data transfer rates of up to 32 gigabytes/'second can be achieved. IV is relative can be used to record long image sequences or large databases .

Figure 4 shows the host, controller, processor, local memory, and 128 Shows 110 functional connections for up to slicing! It is an enlarged view of B. The system is good When reconfigured into a smaller system, each subsystem has host workstation 400 with each old 0 bus connected to a subsystem. exists locally. When maximum SE is used, the leftmost host workstation Only the application/VME bus is active, and the old 0 bus to each slice is connected to each other. connected in series. Global 0R (GOR), Local 0R (LOR) , and a Neighboring 0R (NOR) bus are used to synchronize the controller sets.

Processors are connected to each other in a linear array via an IPC. More processors are added to the system, this architecture Processing capacity increases linearly without the negative effect of increased bar head. Everything in EB 128-bit instruction word (IW) broadcast to the processor. Operates in SIMD mode using . Different because conditional locking is possible Operations may be performed on these processors. All processors I10 have memory IOMG is responsible for data transfer between local memory and 110 sources. are doing. Each processor and controller also has a dedicated profile counter. However, the controller includes a debug interruption mechanism.　′ In Figure 5, SE is a module represented as a hexagon with a width of 50c+n and a thickness of 20cm. It consists of 500 rules. Each module 500 is connected to a power source 16 EB, coolant input, and coolant discharge. Each EB has 64 processors and their respective local memory and 170 functions, and EB controller functions. include. One EB consists of 16 multi-chips using advanced memory manufacturing technology. Packaged using modules. Each system module has its own It can function as a 1024 processor or 16 64 processors. Wear. Modules are vertically arranged (8) to achieve up to 8192 processors Can be piled up.

In Figure 6, the processor prefers four processors using Bi CMO5 technology. It can be integrated on an integrated circuit with a 10 nanosecond full instruction cycle. It is shown. The processor uses the 128-bit IW received from the controller to Operate. IW defines 15 independently programmable operations. P The processor uses a 32-bit data bus and registers, and has several data buses and registers. Registers can be connected to transfer and record 64-bit data. Furthermore, A.L. Some resources like U, register file, and local memory are 6 Operates on 4-bit input.

Each processor is a 64-bit A! , 0600.32 bit multiplier 602.32 bit Tomatochia 604.32-bit auxiliary ALU606.128 word register file address generator (AG) 610-1.610-2. Dual-port local memory specified by processor, for communicating with other processors IPc boat 612, conditional locking hardware 614, and dedicated professional It has a file counter 616.

integer and float to maximize the number of operations per instruction cycle. A decimal point multiplier and an ALIJ unit are integrated. Many processors are integer The integer ALU is used for memory addressing. Parallelization is achieved by performing many calculations in floating-point format while be done. The SE has two dedicated ACs, and floating point and integer operations are usually not performed simultaneously. The integer and floating point units are grouped together and other This saves IC area for the device.

Multiplier 602 multiplies two 32-bit values together and applies the 64-bit calculation result to each instruction. It can be obtained in the second cycle. The result is recorded in the 64-bit P register and its That register is an input to the ALU so that products can be accumulated. Or, square The calculator treats the two 32-bit input values as 64-bit values and stores the 64-bit value in the P register. can load passwords. This means that 64-bit data is supplied to the ALU. It is effective for

A match unit 604 is employed in the processor design. Because it is This is because it is ideal for operations that are highly data-dependent. . Matched with multiplier 602 to optimize the processor instruction word (PIW). 604 share the same instruction field. Matscha 604 is 32 bit back is a special hardware element that performs match operations on data . When the smaller word size is formatted into one 32 pinto word, the data data is backed up.

ALU 600 of FIG. 6 has 32-bit and 64-bit inputs, and two 64-bit inputs. It has an accumulator (ACC). It is an integer and a float in l cycles. Supports dynamic point (32-bit and 64-bit) arithmetic. ACC is also an ALU can be used to record intermediate values in calculations. P register and ACC Serves as a 64-bit input to the ALU600; all other data sources are 32-bit inputs. It's tuto sauce.

Operations that can be performed on the AL111+00 include the normal 32-bit and 64-bit unary binary arithmetic and logic operations, shift operations, and integer/floating point Contains conversion operations. Multi-cycle integer division operations are also possible. conditional subtraction or zero/non-zero (Update ACCI if Zero/NonZero) (used to perform conditional placement) etc. There are conditional operations supported. special purpose operations and then record the larger value in ACCI and the smaller value in ACC2. MIN binary operation, first zero pit recognition and first bit recognition There are unary operations and absolute value operations.

Auxiliary ALU (AuxALU) 606 (Figure 6) is a 32-bit counting operation. used for.

Counting operations are very common to applications that perform image processing. Therefore, Aux ALU 606 is included in the processor design. Ext Since the counting operations are pipelined by the ALU, the factor 6 Speedup is achieved with conditional counting operations. AuxALU is a cash register It is located near the R11 port of the star file and has two registers, namely AuxA LU data register (Aux ALU Data RegisterXADR) and AuxALU condition mask register (AuxALU Condition Ma sk Register) (ACMR). ADR is AuxALIJ operation ACMR contains a processor status word to monitor conditions. (Processor 5tatus WordXPSW) Contains vs.

A special feature of AuxALU is to reduce the value of ADR and to This may cause the processor to lock up. This operation has an execution time of can be used for data-dependent operations. Each processor has its own After finishing the session, it decreases its value to zero and locks itself to NO. (execution of P), makes the LOR signal the signal that terminates the controller. All programs When the processors finish their operations and send out their LOR signals, The controller unlocks all processors and execution continues. This operator The implementation is a rule that depends on local data conditions on a group of SIMD processors. This is useful for incorporating groups. LOR connects processor to controller 1 bit wire, all processors send a high signal, and LOR The LOR signal remains low until you bring the signal high.

A 32-bit dedicated profile counter 616 (Figure 6) is used for real-time profiles. Exists on each processor. In addition, each controller can be used for real-time profiling. It includes a dedicated profile counter 3301 (FIG. 33) that is used. profile is usually an instruction added to the original program to count the number of occurrences of an event. It is done by adding. Some programs like communication via IPC This type of profiling because the segment is taking a long time to reach its limit. is not possible in real-time mode. Dedicated profile counters Used for profiling without interfering with execution.

Each processor profile counter 616 and controller profile counter 3301 has four functions: load counter value, start counter, stop the corresponding controller to execute one of the following: counter, reset counter It is controlled by two bits within the controller or processor IW. Count from counter The ability to read a value is controlled as a write operation to a register. and the register receives the result. From Figure 15a, which is the processor IW format: 15d, the profile counter control field is a 2-bit file. FCC.

Additionally, the number of instructions encountered before the profile counter is incremented is This can be changed by setting the 2-bit field . These two bit fees The four states of the field set the profile counter 616 on each instruction or It can be used to increment each four 16 or 64 instructions.

Each processor has a 128-word (32-bit word) register file (RF)6 0B (Figure 6). Each instruction cycle has four reads and two writes. It can be executed up to the point of writing. and increases on-chip parallelism and memory access by reducing the bottlenecks required to keep functional units operational. Give bandwidth. RF608 has two input ports (R11, RI2) and four It has output ports, which are directed to registers ROI-RO4. each instruction In a cycle, two 32-bit words can be written to RFf308 and four A 32 bit word can be read from RF608. Register pair (ROI, R O2) and (RO3, RO4) are also 64 bits for other processor resources. Can be used as a register pair.

Each processor has an 8 megaword, dual-port DRAM memory 304 (see Figure 3). and 33). The controller is loaded via one bit of the processor IW. initialize the internal memory. Each processor has its own local memory Therefore, there is no competition between processors for memory. Each instruction cycle Two 32-bit word memory accesses can be performed in the memory bottleneck. Doubles the memory bandwidth for processor calculations by reducing Ru. 64-bit value reads/writes upper and lower words simultaneously can be accessed by Memory size is 2 gigabytes for a group of 64 processors Large enough to record an image in 8Kx8 bytes or 64. Low The structure of data across the storage memory is similar to that in FIG.

Two AGs, one for each memory port on each processor, Since the main ALU is used for addressing operations, Not possible. AG enforces certain conditions on checks and/or array access has a special addressing mode that eliminates the need to Become.

The AG performs hardware area checks on the array and It is possible to calculate stride updates. In addition, some special boundary conditions can be defined for.

The AGs share six sets of addressing registers, with four sets for array accesses. Address arithmetic mode, namely normal mode, modulo arithmetic mode, bound arithmetic mode, and butterfly arithmetic mode.

Each processor has a conditional lock hard drive that provides the processor with a conditional lock execution mechanism. The mechanism is conditional execution of code based on local data conditions. By causing processors to lock themselves, A SIMD processor is executed using the MIMD method. processor is on the controller NOP (no operation) instead of the command sent to it from the command nocence The processor execution state is defined as ``locked'' when executing Ru. The processor executes a NOP until an unlock instruction is encountered within the processor IW. keep going.

Instructions that lock or unlock the processor are issued within structured segments. This segment includes [begin J ('begin') and 'end J (' end') sentence. These segments are “If f-then-else') structure, and nesting is possible. rock and unlocking decisions always concern the nearest nested structure. conditional lock The code does not involve any changes in control flow. Instructions are given in order from the controller. broadcast and executed by the processor based on lock instructions and local data conditions. Select one of the codes to run. Conditional lock information is stored in the processor status recorded in the code. Context recording and retrieval instructions are supported and all An interrupt is generated requesting that all processors be unlocked.

AG is a processor component that calculates addresses to access local memory. It is basic. It includes all basic addressing modes and regular array access We give further operations for efficiently computing . ■Per processor There are two AGs, and each local memory boat has its own dedicated AG. AG is a memo uses a common set of registers to access the memory. 8 user bases register (tlBRo-UBR7), eight user limit registers (ULRO -ULR7), 1 bank select register (BSR), 16 base registers star (BRO-BR15), 16 limit registers (LRO-LR15), 8 offset registers (ORO-OR7) and 8 stride registers There is a model (SRO-3R7).

The UBR and ULR provide program data readout for eight banks of local memory. Used to remove mitts. Program data is stored consecutively in each bank. shall be recorded. The BSR determines which memory bank is active. This is a 3-bit register used to store data. 16 BSRs and LSRs are an array It is used to remove limits on the structure of data. Specify all arrays as B Relative to R, LR determines whether the reference to the array structure is out of scope. Used by the AG to make decisions. Eight ORs point to specific locations within the array. The eight SRs are used to update the offset value according to the contents of the SR. used for.

The address word has the following format: (1) absolute/IJB-relative addressing, (3) buffer (20) memory bank address.

The AC operates on a 23-bit address, with the most significant 3 bits specifying the memory bank. The lower 20 bits correspond to one word in a megaword (32-bit word) of bank memory. Specify the code. Since the address is recorded in a 32-bit configuration, the address There are nine additional bits that are not regularly used, some of which contain additional information. carry news. 1 bit indicates that the address is relative to the absolute value or user base (UB). Used to determine whether it is a 08 value or not. UB relative addressing is Used when accessing program data. This use allows the program to make system data relocatable. υB relative address is less than the user limit (L) value If it is greater than or less than zero, an access violation occurs. Absolute addressing mode In the UB code, the address is not added to the UB value. This mode is used for split system information. This information is stored in lower local memory.

AG uses BRO-OR15 and LRO-LR15. Base register (BR ) determines the starting position of aggregate data such as arrays, tables, and stractures. , the limit register determines the address boundaries of the aggregate data. This is hard Enables the software to perform region checks at runtime on each memory access. O R and LR controls are now 8RX must be used with LRX be bound. Only the bottom eight IIRO-BR7 and LRO-LR7 are base-limited. A set offset-stride (BLO3) operation may be used. B.R. contains a 24-bit value, of which 20 bits are for address, and ■focus is absolute/ For UB relative addressing, the 3-bit field specifies the BR memory bank. . The limit register contains 20 bits that limit the offset to BR.

The AG also has eight 21-bit offset registers (ORO-OR7) and eight 21-bit offset registers (ORO-OR7). Contains a 0-bit stride register (SRO-3R7). These registers are Provides an effective means of repeatedly accessing the array with regular strides . Array element to which base-offcent pair (BRx, 0Rx) is to be accessed is used to calculate the address of Therefore, the value of SRx is used to update the offset register. 5RO-3 Additionally for R7, the hardwired constants 0, +1, and -l are the stride values. It is available as follows. The OR value is automatically updated by the stride register value, If the offset does not need to be updated, a stride of zero is specified.

If the new offset value is out of bounds (OOB), the OOB bit is set in psw. Set. Only the lower eight BRO-BR7 and LRO-LR7 are B1. OS operation, and BRx is used with LRx, ORx, and SRx. Hardware controls are bound so that they must be SR is 2 .

It holds a 1-bit two's complement number, and the offset register holds a positive 20-bit value. Ru.

An example of the use of SR is shown in Figure 7, where the offset is initially 2 and the stride value is 3. Sequential array accesses are shown in shaded areas. address is a command Generated every cycle. There are six addressing modes available, these is immediate, register direct, direct, indirect, base relative, and This is the base index. The first two addressing modes do not use AG. A small AG is not used in immediate mode. For use in processor operations. A value is specified in the immediate field of the PIW for this purpose. AG is also register direct mode But it's not used. When values are read from or written to the register file. Ru. Register direct reads are performed using Rol, RO2, RO3, or RO4 files in the PIW. It is executed by specifying the register file address in the field. specified The contents of the registered register file location are then loaded into the appropriate ROX renostar. It will be done. Direct register writing is done by writing a register into the R11 or R12 field of the PIW. This is executed by specifying the data file address. Specify the R1x port value is written to the registered register file location.

In direct addressing mode, scalar data recorded in local memory is loaded. accessed by specifying an address in local memory. register file Although it is more efficient to record scalar data in local memory, If you need to record error data (e.g. register overflow or scalar values (non-indirect case specified by a pointer) exists. The address is from U[lR is specified by specifying the displacement using a direct source (DS). Yes The calculation of the effective address is: effective address - DS + UBy.

The non-indirect addressing mode is most commonly used to fill pointers with data in memory. often used. The address of data in local memory is loaded into BR. O The offset is not needed in this mode, so for the top 8 BR8-BRI5 An indirect address value should be loaded. This mode is the base phase at zero displacement. Equivalent to paired addressing. Calculation of effective address is as follows: Effective address = BRX + υ By.

Base-relative addressing mode is for structure member access and regular pattern addressing. Randomizers in arrays (like table nodes) that are not accessed in the most commonly used for system access. BR has a collective structure such as a structure or an array. The base address of the data structure is loaded. Displacement offset via DS sent as. Offcents are not needed in this mode, so the top 8 BR8 -OR15 should first be loaded with the base relative address value. address Arithmetic mode may be used for base-relative addressing. Calculating the effective address is The effective address will be -BRX + DS + UBy.

Base index addressing mode is for addresses that are accessed in a regular pattern. Most commonly used for lei. BR, limit register, offset register Initial values are loaded into the register and stride register. Valid address occurs After the offset value is updated, the offset value is updated by adding the stride value. subordinate Only 8 BRO-BR7 and LRO-LR7 for BLOS operation lanes can be used. Address arithmetic mode is used with base index addressing. It can be done. Calculation of effective address is as follows: Effective address = BRx + ORx + UB y and 0RX = ORX + SRX.

Used in conjunction with base relative and base index addressing modes There are four address arithmetic modes (AAM). These special purpose modes are Used to reduce computations in accessing arrays in standard format. These modes is executed in hardware and operates on one-dimensional arrays in local memory. .

They are modulo arithmetic mode, bounding mode, butterfly arithmetic mode, and normal mode.

Modulo arithmetic mode converts out-of-bounds array accesses into arrays using modulo arithmetic. Map to. The modulo value is given by the limit register value. array When the access is out of bounds, the bounding mode is set to the bounding condition specified by the user. Give address. Butterfly arithmetic mode is a fast Fourier transform (CFFT) stage. Generate all butterfly addresses for the floor. Out of bounds access fixed However, normal mode does nothing.

With base-relative addressing, the effective address of modulo arithmetic is Juro 1. Calculated by Rx and effective address - BRx + DS + υBY It will be done.

In base index addressing mode, the effective address of modulo arithmetic is The effective address is calculated as follows: Effective address = BRX + ORx + 1JBy Here, OR1 = (ORx + SRX) after being generated by modulo LRx , the offset is updated.

The modulo operation is calculated as follows.

X=X −LRX (when X>=LRX (7)) X=X + LRx (X< When O) X=X <Other times) In the modulo arithmetic mode example, looking at Figure 8, a two-dimensional array is passed to the processor. They are distributed in one column for each processor. to column 30 of array A. A processor with data has an upper limit of 99 for a sequence of 100 elements. Generates a large offset of 150. Under this mode, the border or element 50 The limit value is deducted from the offset to yield a new offset within I am drawn to it. This mode also checks if the offset is less than zero. , if so, limit to yield a new offset that is within the array bounds Add an offset to the value.

In bounding mode, when an array access goes out of bounds, the offset value Replaced with the address location of the boundary condition value. This is done as follows. That is, A default boundary condition is recorded immediately following the last array position and its As a result, it is recorded at position (BRX + LRX). An out-of-bounds address is detected. When issued, the AC returns the address (BRx + LRx), which is the boundary condition value This is the position of

In base-relative addressing mode, the effective address in bounding mode is It is calculated as effective address=BRx÷boundary (DS)+uoy.

In base index addressing mode, the effective address for modulo arithmetic is The effective address - BRX + ORX + UBy where, OR1 = boundary (ORx +5Rx).

The boundary (X) of the boundary offset operation is X=X (0>=X>LRx O)) X=LRx (other cases) In the bounding mode example, looking at Figure 9, a two-dimensional array is passed to the processor. They are distributed in one column for each processor. to column 30 of array A. A processor with data generates an offset 120, which is a 100 element sequence greater than the upper limit of 99 for . Therefore, array element A[30,120] is activated. When accessed, a value of zero is returned.

The AG operates in two modes: address generation mode and address register load and It has a setup mode for writing and writing. This mode is Determined by the address generation mode bit. Both AGs share this bit, Therefore both AGs are always in the same mode of operation.

In setup mode, the lO bit AG field in the processor instruction field is The field has the following format: (2) read/write enable, NOP; It has (2) direct source selection, (3) register selection, and (3) register number.

2-bit read/write enable field, register is AG register Determines whether it is read into a fileset or written to RAM. Ru. When a write operation is made to RAM, the corresponding RAM instruction field is also You must also specify writing. AG writes register value to RAM When writing, select the write data selection field of the RAM field. The loading operation overwrites it. 2-bit DS selection is in the AG register file set. Determine source selection for loading data.

The 3-bit register select selects the register to be loaded. In the register set , 1) tlBo-UO3, 2) ULO-UL7.3) BRO-OR7, 4) OR 8-OR15,5)LRO-LR7,6)LR8-LR15,7)ORO-OR 7,8) There is SRO-3R7.

The 3-bit register number field indicates which of the set of eight active registers. Select one of the registers.

In address generation mode, the PIW has the following format:

(2) Addressing mode 00 Direct addressing 01 Indirect addressing IO-based relative addressing II Base index addressing (2) Direct source selection (Valid for direct and base relative addressing modes) (2) AAM selection (Effective for base relative and base index addressing modes) 00 modulo Arithmetic mode Ol bounding mode IO normal mode 11 Butterfly arithmetic mode (2) Stride selection (Effective for base index addressing mode) 00 Constant 0 01 constant 1 10 constant -1 11 Use the stride register specified by BLOS register selection (3) BLO S register selection (Effective for base index address specification) (4) Pace renostar selection (Valid for indirect and base relative addressing modes) Address generation instruction format Direct address 00 xxdd XXXX indirect atrea, 01 xxxxx bb bb base relative address 10 mmdd bbbb base index 11 mm5s 0bbbbbbbb: BR selection 0bbb: BLO3 selection dd: Direct source selection mm: Address arithmetic mode selection SS6 Stride selection xx, unused As an example of using AG, consider the following multiplication of two 3x3 matrices.

CI=A1xB1+A2xB4+A3xB7C4=A4XB1+A5XB4+Δ 6xB7C7 = A7xBl + A8xB4 + A9xB7 To increase efficiency, calculation systems, to reduce address calculations and/or use caches. To maximize usage, the data is divided into one matrix in large row format and one matrix in large column format. Record in other matrices. However, AG does not have a stride update function. Therefore, matrix data can be recorded in a consistent format on the SE. In particular, both matrices Data for can be recorded in large format in rows. the second matrix (its columns are used in the calculation) ) in the same column for a 3x3 array recorded in row large format. While using a stride with a distance of 3 between elements, the first matrix (its rows are (used in the calculation) uses a stride with a distance of 1. This improves performance by freeing you from arithmetic calculations. In fact, a very tight vibrator A group is formed by processor resources. Figure 10 shows the efficiency of the processor This is a resource utilization table. The rows of the table represent resources, and the columns represent instruction sizes. Represents Kuru. The shaded area represents resource utilization for a particular instruction cycle. . This table represents calculations for filling the columns of a matrix that represents calculation results.

The vibration line calculation proceeds as follows. Add two matrices in the first instruction cycle A response is generated. The value is retrieved from local memory on the next instruction cycle. . Since the memory ports are inputs to the multiplier, these values are then used for the next cycle. Multiplies can be combined in The product is then accumulated in the next cycle. after that , the elements of the resulting matrix are temporarily recorded in the register file. different litho The resources work independently for each step of the computation and each resource, eliminating blockages. Vibration line calculation will occur.

Using the Vibrine method above, the multiplication of an NxN matrix is (N2+4 It requires N+6) instructions. Matrix multiplication is a total of (2N3-N2) times. Requires surgical operation.

The dedicated hardware matcher 604 effectively matches data sequences of arbitrary length. Count the match numbers. Matsucha is ALL so that Matsuchi counts can be accumulated. It is located in front of I. The matcher shares an instruction field with the multiplier in the PIW.

Like a multiplier, it has X and Y data sources and a P register to record the result. use. The multiplication operation is orthogonal to the match operation (i.e. In other words, during the match operation, multiplication is not required, and when the match is in the middle, the match operation is not required. ), this design was adopted.

Matscha operates on data sequences of packed data words. two or more twists When data words of small size are placed within one 32-bit word, data is packed. The matcher matches two 32-bit values in each instruction cycle. and records several packed word matches in the P register. P register The values recorded within can then be input to the ALU and accumulated.

A 32-bit keyword is converted by a matcher as packed data. 32 each Bitwords may represent multiple words of smaller size. Possible for input The following match formats are: ■Bit, 32 words: 2 bits, 16 words, 3 bits bit, IO word; 4 bit, 8 word, 5 bit, 6 word, 6 bit, 5 word Code: 7 bits, 4 words; 8 bits, 4 words, 16 bits, 2 words, 32 bits Tsuto, there is one word.

3.5.6.7 Bitword format has unused bits ignored by matcher . The match format loads the B register (placed in the match format) in that match format. Determined in the set-up command. As an example, the two 3 Consider a 2-bit data word. If the B register is packed word size If initialized to be 4, 5 matches will be recorded.

acronym Is Complement of I 2S 2's complement 800 accumulator ACMR auxiliary ALU condition mask register ADR auxiliary AL [I data register Notification address generator ALIN Active locking identifier number ALU Arithmetic logic unit AuxALLl Auxiliary ALIJ BLO3 base-limit-offset-stride BR base register CID communication identifier CIDR communication identifier register CLC3 conditional locking code segment DIC data input channel DOC data output channel DS direct source EB engine block FAG frame address generator FBR frame base register FIFO first-in first-out method FITSRFIFO input timing - Keno register FOR frame offset tre register FOTSRFIFO output timing sequence register GE zero or more GOR global 0R Bigger than GT 1110 Host human power/output +11OR host human power/output register HRQ host request queue 1/F integer/floating point I10 Human power/output IC integrated circuit IMD immediate value INE inaccurate 10Mc human power/output memory controller 10Q input/output queue 103 Human power/output server IPc inter-processor communication Matsushi does not necessarily start on a 32-bit word boundary, so Aligning data sequences becomes complex. Within a 32-bit word, all One set of templates showing all possible backward starting positions must be defined. In this example, for a 32-bit word, four Since there are two backward words, the match is within the 32-bit word of the D sequence. , starting at the eleventh second, third, or fourth backward. like this and four match templates must be defined to cover this case. Must be. Figure 12 shows the pine tree used for the seven ASCII character sequences. It shows a set of templates. The empty bones of the template are in the D sequence. Initialized for unused characters to ensure no false matches be done.

For accurate matching, each template must be matched with a D-sequence of the same size. do. If all of its templates are compared with subnokens, sequence comparisons are shifted relative to the D sequence by 32 bit words. . This is illustrated in FIG. This allows all characters of D It is guaranteed that the subnocence is consistent with the matching sequence.

The match number is stored in the P register and accumulated by the ALU.

The match is accurate by comparing the contents of the P register with the match sequence length. I understand that. This comparison compares the contents of the P register with the match sequence length. is executed in AL[I. In this example, this matching connection is The result must be compared with number 7, which is the number of characters in the match sequence. Must be.

An implementation that gives the processor the performance of conditionally executed code based on local data conditions. The row mechanism will be explained next. After reviewing conditional locking, the processor describes the operation of and describes the hardware for performing conditional locking. We define the hardware requirements and present some pseudocode examples.

Instead of instructions sent from the control unit's instruction sequencer, the processor When s (no operation) is executed, the processor state is '1ocked'.

Conversely, if the control device executes the instructions sent, the processor unlocks the d'. If the processor is locked, the control unit issues an unlock command. N0Ps are executed until . If the processor is unlocked, I The PC is still in a computing state and requires a specific book to determine when to unlock. Keeping operations are still performed by the processor.

Conditional locking mechanisms allow conditional code execution in SIMD environments. It has sufficient performance for many purposes. Conditional code incurs additional instruction overhead. This can be done without any changes to the control flow. Change processor state The decision to change the conditional 07 King code segment (Conditional Locking CodeSeg+oent: ClO2). C lO2 is an assembly language level code separated by begin and end statements. It is a structure. Each CLC3 has a lock 10 number (Lock ID N umber:LIN). Instructions in CLC3 are based on information from psw. then lock and unlock the processor.

ClO2 is supported by the highest level languages. It has a format similar to a construct. 'then' body of sentence else' body of sentence There are mutually exclusive execution conditions such that either statement body cannot be executed by the processor. is executed, but not both. CLC3s can be nested, but No overlap (if CLC3I starts and then ClO32 starts) ClO32 must be terminated before CLC3I is terminated).

To conditionally lock and unlock the processor, use the following operations: will be done. That is, l) Begin ClO5; 2) End ClO2; 3) Conditional Lock (conditional); 4) Co Conditional Unlock; 5) Conditional [ ! Ise　；　6　　In狽■Nitrogen buoyancy■ Unlock; 7) Interrupt Re5tore; and 8) N It is OP.

Begin ClO2 and End ClO2 are used to separate ClO2 Ru. Conditional Loc if the condition given to the instruction is met The k instruction locks the processor. Conditional Unlock instruction is all locked on the current (highly integrated and nested) ClO3 Unlock all processors. Conditional [! The Ise command is , all processors not executing code in the current ClO3 are All programs that are locked and have executed code within the current ClO3 Sessa is locked. Interrupt Unlock instruction occurs or during a context clause switch that unlocks all processors. used. Interrupt Re5tore is Interrupt Un Used to restore processor state before the lock instruction is executed.

The CLC3 example shows that ClO2 is 1f (to resemble a hen-else construct Presented to illustrate the method.

1f (conditionl) Begin CLC3thenCondit ional Lock (not condition) statement 1 statement 1 else 1f (condition2) Con dional　ElseConditional　Lock(not co ndition2) statement 2 statement 2 else Conditional Elsestatement 3 stateme nt　3End　ClO2 The following hardware supports the process to support conditional locking. used by the

ALIN counter Active LIN number (ALIN) This is the LIN number of the client CLC3.

LIN Lenster: The LIN value is the number of ClO2 that the processor is locked to. be.

If the processor is unlocked, ALIN and LIN are the same.

Cond register: The Cond register is a conditional register that locks the processor. Contains PSW.

C status bit: The C (Context) status bit is located in the PSW. , determine the state of the processor. If the bit is set, the processor will If the bit is not set, the processor is unlocked. Ru.

X status bit: The X (Executed) status bit is located in psw However, within CLC3, mutually exclusive execution of statement bodies is performed. suppress X bit and mutual exclusivity.

PLIN register: Previous LIN register (PLIN) This is where the LIN is stored when a problem occurs.

PCand register: Previous Condition register (PC and) means that the Condition register is stored when the interrupt occurs. It is a place where you can

PC status bit/Previous Context (PC) status bit This is where the C status bit is stored when a crash occurs.

PX status bit: Previous Executed (PX) status bit , is where the X status bit is stored when the interrupt occurs.

Generally, the ALIN counter value increases as ClO5 is entered and ClO It decreases when 2 is exited. Thus, the ALIN value is determined by the ClO3 nesting level. is equivalent to The ALIN value is the same for all processors and Increases and decreases even if the sensor is locked.

The second value, called the LIN value, records that ClO2 caused the processor to lock up. Record. This information is necessary for CLC3s to be nested and the processor It must be determined whether the external CLC 3 or the internal CLC 5 has locked the external CLC 3 or internal CLC 5. P If the processor is unlocked, the LIN value is the same as the ALIN value. P If the processor is locked, the number of LINs is less than or equal to the number of ALINs.

If the processor is conditionally locked, the PSW is stored in the Cond register. and the LIN value is no longer affected by the ALIN value. The C bit locks the processor. is set in the PSW being checked. Your code has a conditional unlock instruction conditionally unlocks the processor, but the LIN value is different from the ALIN value. are the same. Thus, the unlocking instruction always Applies to O2. The processor is unlocked by one of four instructions. Ru. That is, Conditional Unlock, Conditional Else, Interrupt Unlock, (conditional code segment This is the End#CLC3 command.

The X bit is used to effect mutual exclusivity within CLC3. Ru. If the code is executed in CLC3, the X bit is Set to state processor. If the ClO2 °else clause is executed is used to determine which processors the X bits are not running. process If the X bit of the processor is not yet set, the statement body in CLC3 is unexecuted. be.

Next, use hardware support to perform conditional locking operations. Explain how to use Each operation presented uses pseudo code. describes the operation of conditional locking hardware, followed by A method for executing instructions is explained.

Begin ClO2 ALIN=ALIN+1 1P (C=O) IN=LIN+1 x: O NDIP ALIN increases (even if the processor is locked). processor is activated If unlocked, the LIN value also increases. X bit is reset This is because the ClO5 code has not been executed against the new CLC3.

Ens ClO2 1F (LIN=ALIN) IN=LIN-1 X=1 N.D.I.F. A1. IN=ALIN-1 If LIN=ALIN, ClO2 has been exited, so the processor The C bit of can be automatically reset (to unlock the processor).

The LIN value decreases. If ClO2 is nested, the processor: The X bit is set because the statement body of the deepest nested ClO2 is executed. . This relationship collapses X bits of information and yields a number of Instead, use 1 bit.

Since ALIN must decrease unconditionally, the following IF statement ``Condit'' Appears outside of "ional Lock (conditional)".

IF((C=0)AND[(condition TRUE)OR(X=1) ])C=1 Cond 2 PSW LSE X=1 N.D.I.F. If the processor is unlocked, the condition is true or the X bit is set, the processor is locked and the PSW is stored in the Cond register. Ru.

If the condition is false, the processor is still unlocked. CLC3 body furnace body, so the X bit is set.

Next, consider the following IF statement "Conditional Unlock".

1F ((C=l)AND(LIN=ALIN)AND(X=0))-O N.D.I.F. The processor is highly integrated and locked with nested ClO2 If you are not executing the statement body for ClO5, the processor will be unlocked. It is. This instruction has no effect if the processor was previously unlocked. stomach.

Next, consider the following IF statement "Conditional Else".

IF((C!=X)AND(LIN=ALIN))C;x N.D.I.F. This instruction unlocks all processors not running on the current CLC3. lock the processor to be executed on the current CLC3, and Provides the functionality of the 'else' statement in the 'en-else' statement.

The command for "Interrupt Unlock" is as follows.

PLIN=LIN pc=c px=x PCand=Cond LIN=O This instruction saves the state of all registers, so interrupts are You can use the LIN number without affecting the status. all processor is unlocked and can respond to interrupts.

The command for "Interrupt Re5tore" is as follows.

LIN=PLIN c=pc x=px Cond=PCand This instruction restores the state of all registers after the interrupt routine finishes. Ru.

Figure 14 is an example of translation from high-level language pseudocode to low-level code. Ru. Note that most translations are one-to-one and have little execution overhead. must be considered. In addition, FIG. 14 shows processors with different data conditions. Explains how to execute different statements. Each processor is nested Executing the simple statement Sx within the if statement is partially due to the condition in the Cond#[+lse statement. This is because the mutual exclusivity of attached statements is valid.

As appropriate, the processor executes code dependent on the data until the condition is met. Repeat the operational execution with . When the processor finishes executing the operation, the LO If R (LOR) synchronization is provided, set the LOR bit in the PSW. A signal is sent to the control device that has completed the calculation. All processors are controllers If it locks, the controller unlocks the LOR bit. Send a signal to reset. Go to next run.

As an example, when a processor calculates an XY value, the X and Y values are Consider the case where they are different. Although (Y-1) multiplication is required to calculate the result, , this result varies from processor to processor. The controller sends the code to its processor. Then, continuously multiply the partial products by X until receiving the LOR signal to continue execution. . The pseudocode program for this operation is as follows.

P=1 CounF=Y+1 Begin#CLC5 Repeat until LORsignal received by a ll processors [ Decrement-and-Lock-On-Zero (Count) P=P Book X Ko End#CLC3 ResetLORbit Conditional Locking/LOR synchronization operation pseudo In the code, Decrement-and-Lock-On-Zero is , Auxiliary This is a special instruction given by the ALU. to this command If the value of ADH decreases and the result is zero, the processor is locked.

In Figure 15, a PIW defined as 128-bit length is transmitted from the control device to the processor. broadcast under its control. Two instructions are time-division multiplexed is sent as a 64-bit word. PIW with the IW format shown in Figure 15 consists of multiple instruction fields.

P lnsuction Field (1 bit) is used for error checking parity focus. Even if a parity check is performed (parity check The total number of l's in an instruction (including cuts) is always an even number. The error in the command is 10 during transmission from the controller to the processor. 1 bit error is not detected However, it must be noted that 2-bit errors are not detected.

The Mode In5truction Field (2 bits) is shown in Figure 15. The four IW formats, namely Mode O, Mode I, Mode 2, and Mode 3, are select. The difference between these different modes is simply that of the coronation data field in IW. It's the size. Space for immediate fields is RI2 and RO2-RO4 Overlaps the instruction field that specifies the instruction field. like this When the immediate value is specified, the number of data transferred to the RF 608 is limited. immediate fee The sizes of some of the fields are defined to minimize conflicts with RF608 access. is justified.

Mode I+++++++ediate Field Rlx available R Ox availONone 1.2 1.2.3.4 1 32bit 1 1 2 16bit 1, 2 1.4 3 8bit 1, 2 1, 3.4 RField (1 bit) sends a signal to play local memory. IP c In5truction Field (8 bits) is described later. There is.

ALU In5truction Field format (19 bits) is (M ultiplier　l bit (common with In5tructionField) l/F 5elect; 8-bit ALtl operation: 2-bit 5source A Select; 2 bits 5 source B 5 select; 1 bit A CCI Enable; l bi-soto ACC2 Enable; l bit A CCI H/L 5elect; l bit ACC2H/L 5elect ; and 2 bits 0output 5hift.

ALU In5truction Field is the operation and data for ALU. Identify the source. 1 bit l/F 5 select is calculated by ALU. Determine whether is in integer or floating point mode. 8-bit ALU 0operation Field specifies what executes the ALU function. 2 Bit 5source A 5elect specifies one of the four data sources. , 2-bit 5source B 5elect is the ALU operand. Identify one of your data sources. The two 1-bit fields are in the ACCI register. Determine whether the data and ACC2 registers have been updated. ALU responds to commands If not used, the ACC value is saved. two l bit fields The upper or lower 32-bit word of ACCI and ACC2 is Determine whether the input is in a data source. 2 bit 0 output The Sh field specifies the normal shift for the output of the ALU.

Data 5source for 5source A and 5source B: 5o source A: P5 source B: ACC2ACCI RO2 ROI IMD IPc MRI The operations that can be executed by ALU600 include standard 32-bit and 64-bit 1 Base and binary arithmetic and logical operations, shift operations, integer/n dynamic point conversion operations, multiplexing There is an cycle integer divide operation. Conditionally supported operations like conditional subtraction and (conditional Used to execute subject writing) In case of Zero/NonZero has Update ACCI. Special purpose operations are large in ACCI. MAXMINZ arithmetic that stores large numbers and small numbers in ACC2, find-first-zero-bit and find-first-one-b It includes l-adic operations and absolute numbers.

Auxiliary ALU (AuxALU) In5truction F ield (4 bits) is located near the R11 port of the register file. Identify operations to perform using AuxALUs. AuxALU is Used to conditionally increase or decrease data in ADH. 4 bits AuxALU 0operations in the 0operations field is , as follows.

i.e.: l) conditional increase value; 2) inversely conditional increase value; 3) unconditional increase value. , 4) Conditional decreasing numerical value, 5) Inverse conditional decreasing numerical value, 6) Unconditional decreasing numerical value, 7 ) conditional decrease number and lock if number is zero, 8) inverse conditional decrease number and number Lock if value is zero, 9) Unconditional decrease number and lock if number is zero, l O) ACMR load, 11) ADR load, 12) ACMR write, 13) ADH write, and 14) NOP.

To conditionally increase or decrease, the PSW mask must be loaded into the ACMR. Must be. If the conditions specified by the mask are met, the ADH is recorded. Arithmetic operations are performed on the stored numerical values. Operator loading ACMR and ADH In the application, data is read from the R11 port. All conditions are clear in PSW option using the inverse condition specified by the mask. There is a peration. (Many of the conditions are mutually exclusive, such as zero and non-zero. Ru. ) decreases and locks at zero value The above operation reduces to the power (x, y) It is used to perform data-dependent operations such as (x to the power of y). The value of y is The partial product multiplied by the number X is calculated while decreasing through the AuxALU.

If the value y decreases to zero, set the LOR bit in the PSW and lock it. Ru. If the controller receives the LOR signal, the controller unloads the processor. Send a command to check.

Multiplier/Match 5elect In5truction Field (1 bit) determines whether the multiplier or matcher is active . Both resources cannot be active at the same time. This is because the command field is over-knobbed. one instruction field When specifying a resource, other resources must perform a NOP in that instruction cycle. go If both resources must perform a NOP, match has a specified NOP instruction.

Multiplier In5truction Field (6 bit) type The formula is (1) 0operation; (2) 5source X 5e select; (2) 5source Y 5elect; and (+) I s/2S 5elect.

The l bit 0 operation field selects the operation for the multiplier. Choose. 2 bit fields 5 sources x 5 select and 5 sources Y5elect is the four data of X source and Y source input to the multiplier. Select one of the data sources.

1 bit Is/2S 5 select field indicates that the multiplier operates on one Determine whether in complementary form or in two complementary forms. 1 bit l/F 5 select determines whether the multiplier operates in integer mode or in floating point. to identify. This bit is located in the ALU Instruction Field. The ALU and multiplier both operate in the same mode.

The multiplier performs two operations. (1 bit 0 operation field (more specific) or direct loading of the P register with a 64-bit value. It is a code. 5source X 5elect and 5source Y 5elec t specifies the position of each upper and lower 32-bit word, which is P It is to load it into a register.

Data SourceSour for 5sources X and 5sources Y ce X: IMD 5source Y: IPcMRI MR2 RO3RO4 ACCI ACC2 What is Matcher In5truction Field (5 bit) format? , 1 bit 0operation; 2 bits 5source X 5select ; 2 bits 5source Y 5select; and 4 bits B 5ele ct (fields are 5 sources, and the X and Y fields are mutually exclusive).

The 1 bit, 0 operation field selects the operation for the matcher.

2 bit fields 5source X 5elect and 5source Y 5e lect selects the data source for the X,Y source input. 4 bit B 5elect field is 5source X, Y 5eleC [field are mutually exclusive for use in match setup instructions.

The matcher performs two operations: matching and match setup.

When Matsushi executes Matsushi operation, 5source X 5e select and 5source Y 5elect are the data of the X and Y inputs of Matsucha. identify the data source. Matching two 32-bit numbers in each instruction cycle Ru. The recorded match number is stored in the P register.

If a match set up operation is specified, 4 bits B 5el The ect field specifies the number to be loaded into the matcher B register. liga The LeB values include l-8, 16, 32, and mouth (unchanged). For B value If there is no change, both the multiplier and matcher are performing NOPs. It means. Data 5 for 5sources X and 5sources Y sources Source X: IMD 5 sources Y: IPCMRI MR2 RO3RO4 ACCI ACC2 The R11In5truction Field (11 bit) format is a 7 bit Register File Address; 1 bit Write E and 3-bit Write Data 5source.

The R11 port is used to write numbers to the 128 word RF608. 7 The Bit Register File Address field specifies the destination RF address. Identify the code. The 1-bit Write Enable field specifies Determine whether the RF has been updated. 3 bit Write DaLa 5 The source field identifies the source of the data transfer. The following registers/files field is the source of the R11 port.

R11: ACCI IMD P(H) IPC MRI CR ROI　PSW RI21nsuction Field format (10 bits) is 7 bits R egister File Address; 1 bit Write Ena ble; and 2-bit Write Data 5source.

The R12 port operating lane is the same as for the R11 port, but with 2 bits. The difference is that the Write Data 5 source field is used. under The register shown below is the source of the R12 port.

R12: ACC2 P(L) R2 ROx In5truction Field (8 bits per field) type The formula is (7) Register Fi Ie Address (1) Re ad Enable.

The Rol-R04 register synchronizes the numerical value read from the 128 words RF608. Used for temporary storage. 7-bit Register File Ad The dress field is also used when the word from RF608 is read into the register. Determine whether the The 1-bit Read Enable field Determine whether the register has been updated.

Both registers ROI-RO4 are data sources for other process components. It is

ROI: ALII(A) RO3: MPY(X)MWI MAI RI I I PCDR R RO2:　ALU(B)　’RO4:　MPY(Y)MW2　MA2 R121PCOR/CID SW Immediate (IMD) Field (32 bit, 16 bit, or (8 bits) is present if the mode field is non-zero. field rhinoceros The field changes with the mode value, and that field is the R1x field and the ROx field. overlap the field. The IMD fields should be entered in the source below. It is used as follows.

IMD: MPY(X) MAI A! U(B) MW2 R11lPcOR/CID Address Generator Mode Bit (1 bit) is A G is calculating in the address generation mode and in the setup mode. Determine whether the Setup mode loads and writes the AG register set. It has a memory function.

Address Generator 1.2 In5truction Fi elds (10 bits per field) can be set up in two modes: mode and address generation mode. The mode is Address Ge Determined by the nerator Mode Bit.

In AG mode, the In5traction Field has the following format:

That is, 2-bit Addressing Modes: 2-bit DS 5el ect (mutually exclusive with Stride 5 select field): 2 bits Address Arithmetic Mode 5 select; 2 Bit 5tride 5elect (mutually exclusive with DS 5elect field) 4-bit Ba5e Register 5elect (This is BL O3Register (overlaps with 5select field); and This is a 3-bit BLO5Register 5elect.

Address Generator In5truction Field is , Address Generator. two AGo) DS 5 select is as follows.

AGiDS: IMD MRI ACC2RO3AG2DS: IPCMR2A In CCI RO4 setup mode, In5truction Field has the following format: That is, 2-bit Read/Write Enable e, NOP; 2-bit Direct 5source 5elect; 3-bit Register 5 select; and 3-bit Register It is Number.

The 2-bit Read/Write Enable field indicates that the register is read into the register file set, but it is determined whether it is written to RAM. Set. If the write was to RAM, the corresponding RAM instruction field The writing must also be specified. AG wrote register value to RAM In this case, the write is Write Data 5 in the RAM field. Cancels select field selection. 2-bit DS 5 select is data Select the source to load into the AG register file set.

The 3-bit Register 5elect selects the register cent to be loaded. Choose. The register set is I) LIBO-UB7.2) User Lim1t Registers (ULO-UL7), 3) IIRO-OR7, 4) Ba se Registers (OR8-OR15), 5) Li+niL Regi sters (LRO-LR7), 6) 1.1m1t@Register s (LR8-LR15), 7. ) ORO-OR7, and 8) SRO-3R7 be.

The 3-bit Register Nu+nber field is the active value within 8 cents. Select live register. Details are given above.

RAM Intrusion Field (3 bits per field) type The formula is (1) Read/Write, and (2) Write Data 5e It is lect.

There are two independent read/write ports that pass through local memory. There are two 3-bit instruction fields that independently control access to memory.

Random Access Memory: RA Each of M) controls access to local memory through the processor.

1-bit Read/Wri (e field, data value is read from memory. Determine if it should be written to memory. that data is written in memory, 2-bit Write Data 5e lect determines the data source whose content is written to memory. child The exception to this is if Address Generator is in S mode and R This is the case when a write operation is being performed to AM.

RAMI Data 5 sources: IPc MRI ACCI ROIR AM2 Data 5 sources: IMD MR2ACC2RO2PSW , a 32-bit register in each processor, which stores the processor state after the final operation. Contains information about the status. A1. U-Operation, AG, and Processor Information regarding the outcome of the condition is found in the PSW.

The following ALU 5 status Bits (8 bits) are compatible with PE. It has been preserved. The two groups of 8-state bits are complementary.

The False (F) bit is constant and zero.

The Carry (C) bit is set if ALII generates a carry.

The >0(GT) bit is set if the ALU result is greater than zero.

The 0 (GE) bit is set if the ALU result is >.0.

The Valid (VAL) bit is set if the ALU result is valid.

The Under41ow (UF) bit is set when the ALU result underflows. Set.

The Over41ow (OF) bit is set when the ALU result overflows. determined.

The Zero (Z) bit is set if the ALU result is zero.

Two additional bits are used for floating point.

The Inexact (INE) bit indicates that the floating-point result is rounded but not truncated. Set if the

The NotANumber (NaN) bit is set if the word is not a number. Ru.

Address Generator 5 tatus Bits (2 bits) below ) is generated from AGs. The array offset is outside the boundaries of the array. The bit is set if

The next offset is assumed to be outside the boundaries of the BLOS addressing operation. or at the current offset of the other addressing obeline. The bit is set if it is calculated that (Address Generate (see detailed description above for r).

0utOfBoundl (OOBI) Array offset is outside the bounds of the array. It's on the side.

(From Address Generator) Out of Bound 2 ( 00B2) Array offset is outside the boundaries of the array.

(From Address Generator 2) Processor Cond itional Locking 5 tatus Bits Process below ssor　Conditionioㅍ■ l Locking 5 status Bits (4 bits) An operation that determines the execution state and conditionally locks and unlocks the processor. used for See above for details.

Context (C) This status bit locks or unlocks the processor. Ru.

The context clause bit is stored when a PrevContext (PC) interrupt occurs. , so its context is then restored.

Executed (X) This status bit indicates when the processor executes the current LIN number. Used to determine if it is running on a bar. This bit is the condition Used to enable interoperability between executions.

When a Px interrupt occurs, the execution bit is memorized and cannot be restored later. Ru.

The following two bits are used to signal the sequencer.

LOR (LOR) This status bit provides an indication that an event has occurred to the processor. is sent to the processor's control unit to send the signal. As an example event, data follow The processor may signal the controller that a specific operation is complete. Ru. Instead, LOR is used as a 1-bit communication mechanism.

The IPC5 status Bits (2 bits) below are the processor IPC0p Display status information for generations.

IPc Parity Error (IPCP) IPc Model Operation If the IPC data has a parity error when the Set.

IPCReduction (IPcR) A reduction operation processes the received data. Bits are set when needed to process and no operations are performed.

The following Image Vault 5 status Bit (1 bit) is the data Im to signal that it has finished loading the data into local memory. Used by Vault (IV).

The IV Finished (IVF) bit is set when IV data is loaded. Set.

Of the 32 bits, 12 bits of the status word are currently undefined.

IPc is a partial channel that transfers data between processors. IPC is Has near-array network connectivity. Data is transferred via data shift, bypass within a regular communication pattern such as broadcast, broadcast, or any one-on-one or Can move within a to-many communication pattern. The IPC Logic of each processor is su m　Sm1n　.

Regarding IPC data such as max, and, or, or xor operations It also has the ability to perform reduction operations.

Because IPC is built into the processor design, latency communication is low. mutual A processor with four processors separated by data can be transferred once. IPc linear array connectivity allows communication Reduces to one dimension, which simplifies routing and assembly. IPC contraction Small operations provide additional functionality to the processor and enable on-chip parallelism. increase. In addition, there are Since there is a ration mode (called IPCTagged Mode), Provides virtual crossbar communication performance.

IPc has a width of 64 bits, two parity bits, and a storage capacity of 3.2 GBytes/ 400M1 (calculated by Z. Dual 33-bit Executes as a processor channel and performs at one to four times the processor's instruction clock speed. Calculate.

IPC operates from two sources of instructions. The 8-bit field from PIW is , determine if IPc is active, load and store IPc registers control. Other instruction sources are 64-bit IPc 0operation Register (IPCOR), which allows the Determine the specific IPC operations to be performed. This execution causes each processor to Unique IPC operations can be identified. IPC operation is MIMD It is.

IPc has two basic modes: IPc Mode and IPc Tagged Calculate - in Mode. In channel mode, 33-bit IPc is independent It is programmable. Each of the IPCs sends data left and right on the channel. , bypass the data left and right on the channel, or shift the data left and right on the channel. Broadcast to other processors. Figure 16a shows the rightward shift of the IPC. It shows the Bypass operation allows the processor to perform shift operations. removed from the section. In Figure 16a, processor 5.6.7 is bypassed. , processor 8 receives data from processor 4. broadcast operation In communication, a processor that is a communication source sends a number to an adjacent processor. Ru. These processors successively soft data through the channel ( Figure 160). In Figure 16d, the broadcast number is A processor defined as a link continues to pass data if it receives it. do not have. Processor 7 is a local broadcast source and sink. It is.

In IPc Tagged Mode, IPC is configured as a single 66-bit channel. calculate. This mode is used to provide arbitrary one-to-one and one-to-many communications. It will be done. In this mode, the Counciation ID (CID) field A tag called ``LD'' is associated with the data. The processor that receives the data is All load the same CID value in its CID register (CIDR). Next, I The PC is shifted at maximum speed (4 shifts/cycle) and the IPc Logic The matching hardware will match the CID value with the number in the CIDRID field. Load the IPC Data Register (IPCDR) containing the tag data for the code.

Before the IPc operation, processors 0, 4, and 4 load the tag data into the IPc. and all processors as shown in table (a) below. identifies the received tag data. After the IPC operation, the following table As shown in Figure (b), all processors are identified by CIDR. Receive tags and associated data.

CID tag 5 20 10 Data AB Bromo Ke 012345 CIDR20105202020 P.C.D.R. (a) Before IPc operation Processor 012345 CIDR20105202020 IPcDRB CA B B B (b) After IPC operation In addition to the 13-bit CID field, the 66-bit IPc Tagged operation The translation word is a 50-bit data field, a 2-bit tag field, and an even number of parity bits. The 2-bit tag field is user-defined. However, the tag value 00 is reserved to assert that the data is invalid. Ru. The data field is formatted by the user and has a minimum significant 32 bits. Masked for IPC shrink operations. Additional data field bit When used properly, it includes the return CID, so the numbers open the tag data calculations. The memory address or array offset may be returned to the starting processor, or the memory address or array offset data field focus, so the receiving processor stores the memory location in the receiving data. can be associated with data.

IPC Operator:In is determined from two instruction sources. PIW-specific 8-bit IPCIn5truction Field and IPCOR There is a 64-bit IPCooperation loaded. (IPCIn5tr Since the uction field appears in the PIW, it is visible to all processes. The specified IPC0operation is common to all processors, while the specified IPC0operation is It is Cal.

IPCIn5truction Field (8 bits) is located in the PIW There is. It has the following subfields:

(1) Run/5top (2) Load IPCDR (Preserve, Load H&L, L oad L, Load t() (2) 5source 5ele for IPcDR ct(1) Load lPcOR(Preserve, Load)(1) Load CIDR (Preserve, Load) (1) IPCOR, C The 5source 5electl bit Run/5top field for IDR is Determine whether IPC is active on the current instruction. 2 bit Load IPCDR determines if and how a 64-bit IPCDR is loaded. do. The 4 modes are IPCDR, Load IPcDR (L), Lo Saved contents of ad IPCDR (+(), and Load IPCDR (L, H) It is. In the last example, the lower and upper words of IPcDR are the same 32 bits. Loaded by value. 2 bits 5source 5elect indicates which source is the IP Determine whether it will be loaded into CDH. 32-bit sources are RO3, ACCI , ACC2, and MRI. l bit Load lPcOR is lPcOR Load or save the numbers. 1 bit Load IPCCIDR is CID Load or save the R value. 1 bit 5ourc of lPcOR and CIDR e5elect determines which source is loaded. IPCOR and C IDR has a common source which is IMD and MR2.

Since the operation is dependent on data and processor, IPC0perat ion (64 bits) is stored within the processor. +pc 0per ation is a 64-bit value loaded into IPCDR. Each operation It controls IPc independently so it is actually two 32-bit operations. Ru. The upper 32 bits control IPCI, and the lower 32 bits control IPC2. control If a 64-bit value is communicated over IPc, the IPC operand The upper and lower words of Yon must be the same. Two types of operation i.e. IPC0peration and IPc Tagged 0perati There is on.

IPc0operation is an IPC operation supported by PE. Similar.

In this mode both IPCs are separately programmable. 64 bit value is transmitted via IPC by programming the two channels identically. be done. Three types of operations: shifting, pipe passing, and broad It's casting.

IPCTagged 0operation is a Designed for any communication. In this mode, both IPcs are 64 Must be used together to transmit a bitword. The word is It consists of a message number, CID, and data. Data originator sends to CID Allocating a 64-bit word to Must have the same CID loaded into the IDR. In this way, one-on-one correspondence communication and one-to-many communication protocols are supported. Instead, its processor ID as the CID, the range of processors is identified as the receiver of the data. . The data format is left to the programmer and includes that information as the return CID. be able to.

Load data to IPcDR for IPCTagged 0operation. After loading, the IPC contents are updated each cycle within the time determined by the sequencer. shifted each time. The sequencer calculates the number of cycles it takes to send data to the destination. It has a user programmable counter to determine. Each processor has an IP Compare the data shifted to c and compare the CID and CIDH values of that data. Compare. If the two CID values match and the tag bit of the word is non-zero, then A 64-bit word is loaded into the IPCDR.

IPC operation/yeon (27 bits) performs IPC shifting and piecing. , including IPc operations such as Broadcasting. these The operations of the two control IPC independently, so the can be executed immediately. (The IPCI instruction is within the upper 32 bits of IPCOR. The IPC2 instruction is stored within 32 bits. ) IPC O The operation has the following 27-bit instruction field format:

That is, 1 bit (set in Channel Mode) Mode field 1 bit IPcDR High/Low 5 select; 1 bit II” C5peed (1 shift/cycle, 4 shifts/cycle); l bit En able Boundary Value; 3-bit Reduction 0operation; 1 bit Left/Right Direction al Bit; 2 bit 0 operation (Shift, Bypa ss, ar oadcast, NOP); 1 bit Broadcast 5end (Broadcast 5end N0P); 2 bits g Broadcast Receive Left Boundary 5Broadcast R■Mo■Amama■ Right Boundary, Broadcast Receive NO P): 13-bit Capture Cycles; 1 bit Repeat 0 operations.

A 1-bit mode field identifies instructions that are IPC0operation. . 1-bit IPcDR) I/L 5select is the upper word of IPcIIR or is whether the lower word is being read by another processor component. Determine. The 1-bit IPc 5peed field indicates whether the IPc is Are you calculating at the same speed (1 shift/cycle)? Processor speed It is determined whether the calculation is performed four times (4 shifts/cycle). the processor is 1-bit Enab that specifies whether to shift the data value of There is a Boundary Value field. Allowing boundary values gives us between several independent IPC operations using IPC at the same time. prevent interference. The 3-bit reduction operation field is the same for both modes. I am a connoisseur.

IPc0operation determines whether the IPC direction is left or right. It has a 1-bit field for reading. 2-bit operation field is a shift, bypass, broadcast, or NOP being performed. Determine whether the If a broadcast operation is being performed , the 1-bit broadcast send field is is the originator of the cast. The 2-bit field is Determine how the subscriber will participate in broadcast reception. Processor processes data receive the value and pass it to an adjacent processor in the IPC, or as part of a boundary specification. If selected, it acts as a sink for broadcast values. on the left Boundary broadcast reception refers to the left edge of the IPC where that processor receives data. processor. Right border broadcast reception means it is right Identify the edge processor. 32 bits for IPc 0operation 5 bits for each channel are currently unused.

Figure 16 performs shift, bypass, and broadcast operations FIG. 2 is a high level diagram of IPc. The register represents the IPCDR of each processor. Ru.

The top diagram illustrates the right shift of the bus. Figure 2 illustrates bypass operation. and three processors are bypassed. In this example, (left A bypass pattern that makes the first and fifth processors logically adjacent (counting from has been established. A single shift to the right from the first processor transfers the data to the fifth processor. It is softened by the sensor. (The operation does not necessarily occur in l instruction cycles.) You have to understand that there is no. If many processors are bypassed requires several instructions to shift data to the next logically connected processor. There may be an order. ) In the third figure, the third processor counting from the left is being broadcast. In the bottom diagram, some processors are Casting. The second and fourth processors counting from the left are Broadcast At the same time as executing the 5end instruction, the third processor executes the Broadcast R eeeive Right Boundary and the fourth processor executes Br oadcast Receive Left Boundary is running . This identifies the sink for broadcast and local broadcast This is a way to prevent them from interfering with each other.

IPCTagged 0operation (62 bits) allows one set of programs Any communication between processors is allowed. In this operation, the IPC is It is used as a 64-bit channel. For tag operations, sequence The sensor's counter is low for the number of cycles required to complete the communication. is coded. When the counter reaches zero, IPc communication is completed and the sequencer A signal is sent indicating that the communication is complete. The tag operation consists of two It has a data format, and this format determines how the CID is interpreted.

IPCTagged 0operation uses 62-bit instruction field format. have. That is, l bit Mode (with Tagged Mode set) Field; l bit IPcDRHigh, 'Low 5 select: I bit Cut IPC5peed (1/ft/cycle, 4 shifts/cycle), 1 bit Enable Boundary Value: 3 bits Reducti on 0operation; 1 bit IPCData Range format, + 1 bit Le4t 5hift Cyclex 4; I 1 bit Right t 5hift Cycle x 4: and 32-bit Reduction It is Mask.

IPCTagged 1 bit mode field at 0operation identifies the instruction. 1 bit IPCDRH/L 5 select is IPCDH High word or low word read by other processor components Determine whether the l bit IPC5peed field Is the IPC operating at the same speed as the processor (l shifts/cycle)? Determines whether calculations are being performed at four times the processor speed (4 shifts/cycle). Set. Specifies whether a processor should shift the data value to the next processor. 1-bit Enable Boundary Value field for setting There is. Allowing boundaries allows several independent IPs to use IPc at the same time Prevent interference that occurs between C operations. 3-bit reduction operation fee The field is common to both modes.

The 1-bit IPc Data Range format has two formats for interpreting CID values. Specify one of the glue data formats. Where is the data left and right of the processor? There are two 11-bit fields to specify what has been shifted.

Specific values are measured by multiplying by 4, so specify the numerical value in the field. means that the data has been shifted by a factor of 4 in that direction. 32 bits The reduction mask is applied to the minimum valid 32-bit data of the IPcDR to reduce the reduction mask. The number of bits in the word that is dependent on the operation is specified. two undefined bits be.

In Tagged Data format 1, the CID value is interpreted as a communication ID number. be interpreted. Any processor with a matching CID number of CIDR , and receive that data.

The IPc 64-bit data word format has l-bit Even Parity B. it; 13 bits 1-CID field: 2 bits) Tag bit field; and a 50-bit Data field.

In this format, l bit Even Parity bit is used to detect errors. used for. The 13-bit CID field is aligned by the destination processor. Contains numerical values. There is a user-defined 2-bit tag field. That fee If the field is non-zero, the meaningful data is a 64-bit word. ( Although the tag bit is user-defined, the tag bit butterzo 00゛ is reserved. It is. ) 50 bit field is for data. Deciding on the data format is the responsibility of the programmer.

One suitable data format that can be used for 50-bit is 11-bit Return. CID address: and 11-bit data. Another suitable data format (18) 0ffset to the array; and (32) (store and read in the array ) Data.

Example of how to communicate using IPc Tagged Data format 1 are shown in tables (a) and (b) below. Table (a) is IPc The state before 0operation is shown, and all processors are loaded into CIDR. It has a CID value.

CID tag 5 20 10 Data AB C Bromo Ke 012345 CIDR20105202020 PcDR (a) Before IPC0operation The processor then inputs the local data into the IPCDH along with the CID tag. Ru.

The bus is shifted at high speed and the matching hardware Attempts to match the value with the CIDH value. If compatible, the data is loaded to IPCDH. is coded. So after IPC0operation, the result is in the table ( b).

Processor 012345 CIDR20105202020 IPCDRB CA B B B (b) After IPC0operation If several words of data in IPc have the same CID value, Certain result values are dependent on the IPc reduction operator.

The format of IPC 64-bit data is (1) Even Parity Bit (13) CID field; (2) Tag bit field; (8) Range field; and (42) Data field.

1-bit Even Parity bit is used to detect errors . The 13-bit CID field contains the numeric value of the processor ID. This mode In the code, the CID field is loaded with the processor ID. User defined There is a 2-bit tag bit field. if that field is non-zero , meaningful data is in 64-bit words. (Tag bits are user-defined. However, tag bit pattern 00' is reserved. ) 8 bit Ran The ge field specifies a contiguous range of processors (Range values are [C The processor between [ID] and [CID+Range] receives data. ). In the case of 42-bit data field data, the programmer must determine the data format for that field.

The examples shown in the two tables below are in IPCTagged Data format. It explains how 2 works. In this example, processor 0 is data processor A' is sent to processor 2-5. First, as shown in the first table below, Each processor enters its logical processor number into CIDH and processes processor 0. specifies a CID of 2 in a range of 3.

Opening price: Processor 0123456 CIDROl 2 3 4 5 6 Range 3・・・・・・・・ After IPc 0operation, as shown in the second table below, Processors 2-5 have correct data values.

After IPC0operation: Processor 0123456 Reception・・AAAA・ Reduction 0operation Field (3 bits) is the IP Common to both C and Tagged operations. It is IPC data Identify the reduction operation to perform on. That field will shrink If it is determined that the PSW is not Set. There are eight reduction operations. 1) XOR5) Max 2) AND 6) Min 3) OR7) Sum 4) Replace 8) In 5ortChannel Mode, the data The field is a 32-bit value of IPCDR for a particular channel (channel 11 uses 32 bits of IPCDR, and channel 12 uses the lower 3 bits of IPCDR. (use 2 bits). In Tagged Mode, data fields are variable is defined by the 32-bit Reduction Mask, but it applies to the minimum significant 32 bits of data. The identified reduction operation is , on words received via the IPC bus and IPCDR. its operation The result of the tion is provided to the processor as signal IPC. In FIG. 6, the signal I The PC is written to local memory via AG610-1 and the RF608 Y operand of match unit 604 or multiplier 602 is applied as the A operand of ALU 600.

The data reduction operation is performed as follows. IPC via IPC bus The data value received by logic 612 is the l operand and the IPCDH The number stored in is another operand. Once the operation is executed The result is then stored in the IPCDR, replacing the initial contents. above two The two replace and sort operations are best explained. I can understand it very well. Replace operation allows The received value replaces the initial contents of the IPCDR. By sort operation The large operand occupies the 32M5R position of IPcDR, and the small operand occupies the 32M5R position of IPcDR. The operand occupies the 32 LSB positions.

The 10MC handles all data transfers between the SE and all external sources. the The SE is organized into /linders, with each cylinder containing a processor, local memory , and 10MC. Since the cylinders are organized, the IOMC and The only form of communication between processors is through local memory. In this way, Processor I10 is a map memory, a link between external sources and local memory. It is the role of the controller and IOMC to ensure that data transfer is performed properly. It's a discount.

10MC has three main Ilo Channels, namely Data Input t Channel (DIC); Data 0utpu+ Channel l (DOC): and Ho5t Ilo Channel (1+l0c) Connected. This includes video sources, video destinations, and host workstations. each handles data transfer between the two versions. DIC and DOC are lnp The processor interfaces are ut5lice and 0utput5lice. connected to the IOMC via the

Ho5t Ilo Bus (HIO) is I (ost Workstation) A 32-bit bidirectional channel connects the IOMC to the IOMC. That channel is The IOMC of the array is connected to the host placed at the left end of the HIO. that channel The file has a data rate of 200MB/sec.

DIC connected 10IJC with maximum 5 sources at the same time 4 It is an 8-bit unidirectional channel. DIC has four independently controlled 12-bit serial It consists of channels (each channel has 5 different video sources). ) Each channel operates from a different clock so that it can be read out.

DIC has a linear array IOMC located at the left end of DIC. Connected to urce. Channels transmit data across the bus from left to right . DIC is connected to IOMC via Input 5lice.

The channel operates at a maximum speed of 86M1+Z, with a data rate of 1.2GB/sec. have.

DOC can simultaneously connect IOMC to the maximum number of Video Destinations. A connected 48-bit unidirectional channel. Similar to DIC, DOC is independently controlled consists of four 12-bit serial channels (each channel has a different ) for each channel so that it can be written to the Video Destination. The channels run from different clocks. Video input/output channel is same format When transmitting data at the same speed, the DOC calculates from the DIC clock. There is a mode. The DOC places the linear array IOMc at the left end of the DIC. Connected to Video Destination. bus through it Transmit data from right to left. DIC connects I via 0output 5lice. Connected to OMC. The channel operates at a maximum speed of 86MHz and supports 1.2G It has a data rate of B/sec.

In Figure 17, Input 5lice is 10MC interface for DIC. A total of 64x32 bit FIFO 1702, one for each DIC. Input Controller 1700 consisting of -1 to 1702-4 and It consists of hardware that has an interface with the DIC. Each FIFO1 702-1 to 1702-4 are filters that change 12-bit input to 32-bit output. Contains Foma Tsuta (FMT). Data from DIC is loaded via FIFO. of the next IOMC in the linear array via the DIC. Bused to Input 5lice. Instead, the previous IOMC's 0output Data from 5lice is routed to IOMc Input 5lice. can be used. Control device! 700 has two functional roles. That is, , controls the data loaded from DIC to FIFOs 1702-1 to 1702-4. from FIFO 1702-1 to 1702-4 to local memory. It is to transfer data.

In Figure 18, 0output 5lice is 10MC interface for DOC. face, each DIC1, m--1 (7) total four (1) 64 x 32 bit FIFO] -802-1 to 1802-4 0output Con Troller 1800 and hardware that interfaces with DOC? It is becoming more and more. Each PIF01802-1 to 1802-4 has a 32-bit power It includes a formatter (FMT) that changes to 12-bit output. local memo The raw data is directed to DOC via PIFo 1802-1 to 1802-4. data in the DOC from the previous IOMC is bussed to the next IOMC. . Control device 1800 has two functional roles. i.e. local memory Transfer data from 0output to FIFO 1802-1 to 1802-4 In addition, the output of FIFO1, 802-1 to 1802-4 (7) is sent to DOCl, m. It is to believe.

Old O is a non-real-time data transfer between local memory and the host workstation. used for data transfer. It is based on user interactive control and algorithmic control. Modification of rhythms and activities such as program loading, daggers, and output Support Tee. The host channel is used for data transfer and vector data transfer. is supported.

Transfer data between the host and memory is buffered. Host and SR are in different clones Because it operates on the read rate and is not strongly coupled, no data buffering is required. be. The host sends data to the Operating System via the VME bus. m (OS) Read and write to Buffer. IOMc sends data to HI Read and write to O3Buffer via O bus. One set of registers exists in each IOMC and control device connected to the linear array (see Figure 3). ). Data is shifted over the HIO bus at a rate of 200MB/sec. O 3Board coordinates the use of O3Buffer to ensure that data is shared between host and local ensure accurate transfers to and from memory. O3Buffer and O3B Details regarding oard will be described later. The HIO bus connects all IOMCs and control devices is a 32-bit bidirectional path connected in series with Data to O3Buffer Until stored, the data loads it into the old ORegister (HIOR) ) 110 bus to the left and write to the O3Buffer. be caught. Similarly, until the data reaches the destination HIOR, [writing to OMC is Executed by reading O3Buffer and shifting the data to the right be done.

There are two types of data sent over the bus. In other words, vector data and It is data. Vector data is 32 bits with the same size as the number of processors. This is an array of data. The data is sent in reverse order to old 0, so the first data The word is directed to the rightmost processor, and the last data word is directed to the leftmost processor. Directed to the processor. This way, all data is processed in the same cycle. It reaches Sessa.

The data is sent to all 10 MC processors in the destination host word. Identify the ID number (PROC#NUM) and copy a single word of data to the old OBu. s to the IOMc. You can't shift in swash mode. Otherwise, the postbus operates as a true bus monitored by all processors.

To determine if it is the destination for the data, each 10 MC uses the host Compare the PROC#NUM of the code with the value of PIDR.

The IOMc receives the 42-bit Ho5tCom from the control device that identifies the old 0 It has and. The old OCommand has the following command fields. .

(1) Vector/5calar 5elect (1)) lost Re ad/Write 5hift (1) 5hift Enable (Load HIOREnable) (13) Processor ID (1) Memory Enable (1) Memory Read/Write (23) Memory Add ress Field (1) Load PIDRenable 1 bit Vec tor/5calar 5elect field indicates that the bus data is a vector. Determine whether it is there or not. 1 bit Ho5t Read/Wri te 5hift moves data to the left on the path for reading by the host. Shift to shift data right on the bus for writing by the host . The leftmost IOMC sends data to the host via Ho5t Readshift. Shift and the rightmost processor is the last processor, so it pulls the data from the bus. shift. 1 bit 5hift Enable transfers data from the bus to the old OR shift. The 13-bit Processor ID field is Used in scat mode to compare with numbers. If the numbers match, then The value of is loaded into the old OR. 1 bit Memory Enable field allows local memory access. 1 bit Memory Rea The d/Write field indicates whether the memory access is a read or a write. Identify if there is. The 23-bit Memory Address field is lost Specify the local bank and address participating in Read/Write. Ru.

Since the PROCRNUM value is not wired to the cylinder, 1 bit Load E The nable field only needs to be executed during SE initialization. During initialization , the host transmits the array of PROCIINUM values as a vector value. (Be The PROCRNUIJ value is not used in vector data transmission. ) numbers are old OR If the value has been received by the No. Load PIDREnable is a PID with contents of ) IIOH Load R. Also, PROC must be initialized with PRO(jlNUM) do not have. Also, since PROC#NUM is written to local memory, PR OC reads the value and initializes it as PROC#NUM.

Video Input is sent to the SE via a 48-bit unidirectional DIC.

The DIC is actually four 12-bit channels that are independently controlled and have different Vi Each can be read from deo Input. Conceptually, Video In put is at the left end of the DIC and is connected to the left end 10MC processor.

All IOMc processors are connected in series by DIC, and the rightmost IOMc is the last processor on the bus. Data is from left to right of DIG forwarded to

The 10MC/DIC interface is called Input 5lice, and the IO Controlled by MCInput Controlle. Input Ca The noker performs two basic functions. Input data from DIC t FIFOO’1deo Capture) and data In put FIFO to local memory (Video to Memory Tr (ansfer). Based on the synchronization signal sent by the data source Video Capture is executed autonomously. Control device is video o If interrupted by Interrupt, Video! .

Memory Transfer is executed.

Currently, S [! There are seven video data formats supported by be. The formats are Composite Video, Y, C (Lumi nance/Chroma) (Multiplexed), Y, C (L+u+ +1nance/Chroma) (Dedicated Channel), RGB (Multiplexed) ARGB (D (Channel), and Feedback.

Data loaded into local memory is retrieved from a 12-bit serial channel. The 32-bit data is stored by the formatter located in front of the Input FIFO. It will be backed up. Data with multiple fields is time-division multiplexed and It's in Omatsuta. Its format is determined by the Input Controller. determined. The format is Video Capture 5etup In5tru ction.

In FIG. 19, the formatter has three pixel formats. All of the above All video formats match the pixel format. Bixel format 1 is 32 bits is a single 12-bit data field located in the lower 12 bits of the word. . Bixel format 2 has two 12-bit data fields, each containing 16 bits. Fills the lower 12 bits of the first halfword. Bixel format 3 has three data files. It has a field. That is, two lO bit fields and a 12 bit field. The word has a 12-bit field in the lower 12 bits.

Figure 20 shows the different video modes supported by the SE. Com In composite Video mode, Composite Video is 12 Sent as a bit value over a 12-bit channel. The number is 32 bits Loaded into the lower 12 bits of the word. Input Conke offer This is in pixel format, as specified by .

In Luminance/Chroma (Y, C) mode, two 12-bit Information encoded as values is transmitted over a 12-bit channel. Part two The two numbers are time-multiplexed by the formatter using 32-bit words. . The luminance value is loaded into the lower 12 bits of the upper 16 bits of the clock. The master is loaded into the lower 12 bits of the lower 16 bit word. This is Input This is pixel type 2 specified by Conker.

Y, C (Luminance/Chroma, Dedicated Chan In the nel) mode, the two components are provided with dedicated channels. two The two 12-bit values are stored in the lower 12 bits of a 32-bit word by the formatter. loaded. This is in pixel format (Co+nposite Video (same format as o).

In RGB (Multiplexed) mode, the RGB signal is 12 bits It is encoded as three 10-bit values transmitted over the channel. three The numbers are time multiplexed into 32 bit words by the formatter. top 20 The bits are loaded with red and green components, with the lower 10 bits being the blue component. loaded by the component. This is done by Input Controller. pixel format 3, the 10-bit value is placed in the lower 12-bit field. loaded.

In RGB (Dedicated Channels) mode, each color component is given to a dedicated channel. The three 12-bit values can be formatted as is loaded into the lower 12 bits of a 32-bit word by the controller. this is pixel The format is 1 (same format as Composite Vtdeo).

Feedback format mode is used to feed back 32-bit values. It will be done. The word is split into two 10-bit values and a 12-bit value. The three numbers are , time division multiplexed into 32-bit words by the formatter. 12 bit value occupies the lower 12 bits of a 32-bit word, and the two lO bit values occupy the upper It occupies 20 bits. This is specified by the Input Controller. pixel format 3.

The RGB format uses four 8-bit fields to represent R, B, and G, and a video signal. It has components of No. Words are transmitted via DIC and DOC. The second is decomposed into two lO bit values and a 12 bit value. The three numbers are formatted is time-division multiplexed into 32-bit words. This is Input Cont pixel type 3 specified by roller.

In Figure 21, Video Capture Commands are from DIC. The process of “capturing” video data and loading it into the Input FIFO 2100. used for Two-dimensional video input frame data is 5eri al　Transmitted via DIC. That frame is displayed as soon as the page loads. IOMCInput C, which is read line by line from left to right in the DEC The role of each ontroller 2102 is to determine which pixel in the DIC This is to determine whether the file has been loaded into the local memory 2104.

The video input is not delayed, so you can capture the pixels from the DIC and send them to the Inpu t The operation to load into the FIFO 2100 is a no-control instruction stream. automatically by the Input Controller 2102 independently from the system. executed. Input Controller is DICInput Tim ing 5equencer Register 2106 (ITSR) H (Horizontal 5 ynchr onization　Signal), F　(Frame　5ynchron ization Signal) and video clock signal to another video signal. Determine when to load the cells from the DIC into the FIFO. Each channel has its own set It has an initial signal and an ITsR.

The Input Controller has two counters, one set for each channel. have.

That is, they are the Pixel Counter and the Line Counter. This card The counter operates in HSF, and the video clock signal is input within the frame of the video input. Used to determine the location of a certain pixel. Pixel Counter is , displays the horizontal position of the DIG pixels for the current line of video input do. Line Counter is the DE for the current line of video input. Determine the lateral position of the pixels of C.

DIC calculates the video clock signal rate and determines when the video clock signal is asserted. Each time a different 12-bit value is clocked into the DIC Register (DICR). It will be done. Pixel Counter is 1 video clock cycle, 2 video clock cycles. Whether it increments every 3 video clock cycles or every 3 video clock cycles. Cell format is 1 data field, 2 data fields, or 3 data fields It depends on whether you have it. A new line of videos has started, so ■The signal increases the Line counter and increases the Pixel counter. Reset. An F signal is generated each time a frame of video is transmitted through the DIC. . If it is generated, Pixel Counter and Line Cou nte" are reset. Also, the F signal is Send a signal to the Generator (FAG) and set the frame buffer address. change. SE uses any buffering system, with a minimum number of buffers is 2 (double buffer). Then one video frame is processed by the processor. and other frames are loaded by the IOMC. Any The main advantage of buffering is that much of the data is loaded after the previous frame has been loaded. It is possible to survive for several frames. This stores temporary data Required by the program you use.

ITsR determines when to read a pixel from DIC to Input FIFO. used for It also depends on the number of consecutive pixels to be read out and the readout process. Specify parameters such as the number of repetitions of the process.

In the 27bit DICITsR format, DIC data is read into the Input FIFO. used to specify the parameters of the method to be discovered. The register has four frames. It has a field. That is, (2) Pixel Data format, (13) In1tial Pixel Po5ition, (6) Number of Pixels, and (6) Pixel Repeat at Interval be.

The 2-bit Pixel Data format field is set by the channel formatter. Select the pixel format used. This is the Pixel Counter It is necessary to determine the number of times the video clock signal is increased proportionally.

The 13-bit In1tial Pixel Po5ition field is Determines when pixels are read from the DIC for each line of video input . It specifies the lateral position of the current line's pixels. this field The value of is compared with the value of Pixel Counter. Two numbers are consistent If so, the pixels are loaded into the FIFO.

6bit Nua+ber of Pixel field is read into FIFO Determine the number of consecutive pixels that will be displayed. In1tial Pixel Po5iti If on matches Pixel Counter, PixelRepea t Interval Counter (PRI Counter) is zero or , this number is loaded into the NumPix Counter. o Num Pix Counter will decrease Pixel Counter Input Conkey is incremented every time until the counter decreases to zero. r loads the pixels into the FIFO. 11 signal is NumPix Count Reset er.

The 6-bit Pixel Repeat Interval field Determines the number of times to read into a pixel in the group. In1tial Pixel Po 5ition field is aligned by Pixel Counter value In this case, Pixel Repeat Interval is PRI Count loaded into er. Every time Pixel Counter increases, PRI C outer decreases. When PRI Counter decreases to zero, , PRI Counter and NumPix Counter are reloaded.

11 signal resets the PRI Counter and NumPix Counter. to

As an example of a format for pixel input, ITSR is described (see FIG. 22). child In the explanatory diagram, In1tial Pixel Po5ition is 1 and Numb This is an example in which er of Pixels is 3 and PRI is 11.

FIG. 23 shows the difference between the two problem spaces. consecutive multi-vixels The ability to obtain this is inherent in SH. In the case of PE, the processor Since we are only receiving cells, the problem space is limited to the number of processors crossing local memory. It was distributed according to the law. In the case of a 1024 processor system (see Figure 23) Identical ones of the 1024 processors in the 23, the one next to the 1024 processor is indicated by the double hatched area. ), the 1024th column of l-frame video is all processed by the same process. exists on the server. Based on scheme l in Fig. 23, in the case of PE, 20 To process the first 1024 pixels of the 48 pixel scan line, 1 024 processor system and then this 2048 bit This same sequence again to process the second 1024 pixels of the xel scan line. All of one 1024 processors must be used. Also, SE is good While operating according to Scheme 1, it is also possible to operate according to Scheme 2 of Figure 23. Ru. In this case, additional flexibility is added to the system design, with up to 64 rows of Rice can be embedded in the same processor.

In FIG. 24, Video Io Memory Transfer (FI FORRead) reads the contents of Input FIFO2400 to local memory. It shows how it is incorporated. Execute the Video Capture command. FIFO 2400 is successively loaded as the data progresses. Inside FIFO2400 In order to store the content in the memory 2402, the controller 2 404 must be interrupted by the interrupt program 2406. this is executed through the inch labd, but it is not possible for other video lines to be connected to the DIC. Called every time a lock is acquired.

Input: How and where data in the FIFO is stored in local memory There are five registers that define each channel to determine. These four Regis valid base address of the active frame buffer used by the FAG. generate a file. As shown, FAG is a Frame Painter (FRT R) + Address Counter 2408 is used. fifth The register is FIFOInput Timing 5equencer Regi ster 2410 (FTTSR), which stores data (in local memory). It describes how to store data in the frame buffer.

Video to Me+++ory Transfer In5tructi on is a multicycle instruction. If it is executed, the pixel characteristics Constants are transferred from FIFO 2400 to local memory 2402. of that command The parameters are stored in FITSR2410.

FIFOInput Timing 5equence Register 2 410 (FITSR) format (32 bits) is Input FIFO used to specify parameters for how to read data in local memory into local memory. used. The register has four fields. The fifth field is IT It starts with SR. That is, (11) In1tial Frame 0ffset , (6) Defta 0ffset, (11) Modulo L, (4 ) Wait Cycles, and (6) (from ITsR) Number B f Pixels.

11-bit 1n mountain al Frame 0ffset indicates that the first element is frame-based. Specifies where the frame is stored in proportion to the value of the frame. For example, an offset of 8 is specified, the image represented in local memory will be displayed on the video source. As shown, it has been shifted 8 lines directly below the image. 6 bit De lta　0ffset is an additional vertical value added to the address for each operation. Determine the offset of 11 bit Modulo 1. The field is vertical Determines when the position calculation wraps around. The field holds (in the limit) a numerical value Ru.

In FIG. 25, if In1tial Frame O[fset is 2, Delta 0ffset is 3, Modulo L value is 16, continuous Data transfer to lines 2.5.8.11.14, l, 4.7.10, 13, etc. Is displayed.

The 4-bit Wait Cycles field waits before the transfer is completed. Used to determine the number of additional clock cycles. This field is slow Used when local memory is accessed.

6 The Number of Pixels field is moved to local memory. Specify the number of pixels to be sent. This number is for Video Capture is always the same as Video to Memory Tran. Although it is a parameter for sfer, the parameter is not specified in FITSR. not present.

IOMc has a single FAG that all channels use. local memory Since there is one port to , there is one FAG for Video Input and 0utpu It is only needed for all 5 sources. Each channel has five levels. I have dysstasis. That is, Frame Ba5e Register (FB R), Frame 0ffset Register (FOR), Fra me 5trid■@Regis ter (FSR), Fra+ne Lim1t Register (FL R), and Pixel 0ffset Register iFOR) It is. The frame buffer for each channel is located in the adjacent memory of local memory. Assign. Each frame buffer must be the same size. FBR and FLR identifies the first and last locations of memory allocated to the frame buffer do. FSR includes frame size. FOR is an α proportional to the FBR value. Contains the offset for the active frame buffer. (The frame buffer is If a buffer is currently loaded with data, it is active . ) Each time another frame of data is loaded, the AG loads FOR=(FOR+FS R) Compute modulo FLR to generate the next buffer offset. Active The base address for the frame is Effective Address=FBR+ Calculate FOR.

FOR is used to refer to a position within the active frame buffer. P OR is updated by the parameters described in FITSR. (The F signal is If generated, POR is In1tial every time a new frame starts. Frame is initialized to 0ffset. Video to Memory If a Data Transfer command is made, the pixel offset is calculated. calculated.

FOR=Initial Frame 1Mfset (immediately after F signal) FOR= (POR+DelLa 5tride) Modulo In1tial Frame 0ffset, Delta 5tride, and L value are all FTrSR is specified. Also, (by the Number of Pixels field) )FOR is incremented once for each pixel transferred. Add.

F! for a location in the active frame buffer! effective Loc al Memory address is calculated as EA=FOR+FOR+FOR Ru.

Video Input 0operation 5etup is for each channel. ITSR, FITSR, and FAG Register are initialized with new values. I will briefly explain how to do this. All these numbers are user specific and are Processor dependent, so addressing information must come from the processor. do not have. To simplify the initialization and modification of this register, the local memory portion is reserved. has been done. The processor uses a dedicated memory that allows the IOMC to read the data. Write to the memory location.

Reserved memory locations are used for initialization, so you cannot change video parameters. Execute the instruction to update the system as a system call. Some parameters include user There are some things that cannot and should not be specified by the user. For example, the The system allows users to parameterize channels used by another application. Required to protect against situations where you attempt to update the meter. thus, A system call that can protect against such situations is the video input operations is the proper way to perform a setassembly.

Video output is sent via a 36-bit unidirectional DOC. D.O. C is one of three independent controls that write to different Video 0 outputs. Consists of 2-bit channels.

Conceptually, Video 0output is at the left end of the DOC and connected to the left end IOMc. It is continued. All IOMcs are connected in series by DOC, right The edge IOMc is the last processor on the bus. Data is from right to left on the DOC transmitted to.

10Mc/DOC interface is called 0output 5lice, and IOMC Controlled by the 0output Controller. 0output Co The ntroller performs two basic functions. In other words, the data can be stored as a local memo. Transfer from Memory to Video to 0output FIFO Transfer) and data from 0output FIFO to DOC. (Video Display).

If you are interrupted by a Video Interrupt message, the Nokensa will memory to video.

Transfer is executed. Video Display is the output data channel. Based on the synchronization sent by the channel source, 0output It is executed autonomously by er.

Details of the definitions of video formats and pixel formats are provided above. Supported video There are seven data formats. That is, Composite Video, Lum1 nance/Chroma, Lum1nance/Chroma (Dedi rated Channel), RGB, RGB (Dedicated Channels) ARGB.

and Feedback.

0output Video Data located in FIFO is a 32-bit word It is backed up.

FIFO receives the signal from 0output and 0offer and stores the data. When sending to a 12-bit serial DOC, (Out 4 LCo port trol )0output FIFO according to the pixel format specified by Ier. The located formatter unbacks the data and transfers the data to D in a time-sharing manner. Separate into OC. This pixel formatter of 0output FIFO is In put Performs the inverse operation of the pixel formatter located in the FIFD. Ru.

Video Display Commands output pixels to DOC A process for displaying video data is described. two dimensional video Complications arise as output frames must be transmitted via serial DOC . As pages are written, pixels are written to the DOC line by line starting from the left. Clocked to the right. 0output When FIFO is clocked by DOC It is the role of each 10MC0put Controller to determine .

In Figure 26, the operation to write the contents of PIFO2600 to DOC is , 0u independently from the control unit's instruction stream so that the video output is not delayed. This is automatically executed by the tput canoler 2602. 0ut The put controller 2602 outputs the HSF and video clock signals. , DOC0output Timing 5equence Register 2604 (OTSR) with the specified parameters to t Determine when to write another pixel in FIFO 2600 to the DOC.

0output controller 2602 is a channel that increases with 11, F Each set has three counters and a video clock signal. This counter determines the pixel position within the output frame of the video. Pixel Count er determines the horizontal position of the DOC pixels for the current line of video output. it's shown. Line Counter is for the current line of video output. Determine the vertical position of the pixel of the DOC.

DOC calculates the video clock signal rate and the video clock signal asserts Each time, another 12-bit value is clocked into the Pixel Counter ■Video clock cycles, 2 video clock cycles, or 3 video clock cycles The pixel format is 1 data field, 2 data fields. Depends on whether you have a tough field, or 3 data fields. bidet Since the new line of O has started, the 11th signal will increase the Line Counter. and reset the Pixel Counter. the frame of the video is completed An F signal is generated each time the If a signal occurs, P1xel Count Both er and Line Counter are reset. Also, the F signal is F Sends a signal to the AG to change the frame buffer address. SE can be used with any Use a faring scheme. Since the minimum number of buffers is 2 (double buffer processing), - the video frame is processed by the processor and another A frame is displayed.

0TSR2604 is pixel 0output from FIFO2600 to DOC Used to determine when to load. Also, it is necessary to write consecutive Identify parameters such as number of cells.

DOC0TSR2604 (27 bits) is 0output FIFO2600. Used to specify parameters regarding how data is written to the DOC . It has the same format as ITsR. The register has four fields. Ru. That is, (13) Initial Pixel Po5ition, (6) N amber of Pixel, and (6) Pixel Repeat In It is terval.

The 2-bit Pixel Data format field is set by the channel formatter. Select the pixel format used. This is the Pixel Counter is needed to determine the number of times that increases proportionally to the video clock signal.

The 13-bit In1tial Pixel Po5ition field is After generating the signal, the next pixel in the 0ulput FIFO is loaded into the DOC. Decide when to That pixel has the video output frame horizontally Locate the location. The number in this field is the number of Pixel Counter. compared to the value. If the two numbers match, the pixel is loaded into the DOC. It will be done. The 6-bit Number of Pixel field is a continuous pixel field. Determine how many to load into the DOC. This number is In1tial Pixel P.

5cion matches Pixel Counter, or Pixel Re peat Interval Counter (PRI Counter) If it decreases to zero, it is loaded into the NumPix Counter.

NumPix Counter is associated with each Pixel Counter instruction. 0output Control ler loads pixels into the DOC. ■The signal is NumPix Count Reset r.

6 bits Pixel Repeat Interval field is pixel Specify the number of consecutive times to write the number of consecutive times in the DOC. In1tial Pixel P If the os mountain on field matches the Pixel Counter value, P ixel Repeat Interval is loaded to PRI Counter be done.

Every time Pixel Counter increases, PRI Counter decreases. Ru. When the PRI Counter decreases to zero, the PRI Count er and NumPix Counter are reloaded. H signal is PRI Co Reset counter and Nu+nPix Counter.

0TSR specifies the same type of pixel output formatting as TTSR. Ru. The only difference is that a reverse operation is being performed.

In FIG. 27, the local memory 2700 is 0output FIFO2 in Transfer (FIFO Write) 702 is shown. FIFO2702 is Video Dis It is continuously emptied as play commands are executed. the contents of memory 0output In order to load to FIFO 2702, the control device 2704 Must be interrupted by rhabdo program 2706 and memory transfer will proceed to.

This is called every time another line of video is ready to be clocked into the DOC. Executed via Inch Loved issued.

Which data in the local memory 2700 is loaded into the 0output FIFO? defined for each channel to determine which channels are loaded and in what order. There are five registers. These four registers are used by the FAG to Generates a valid pace address for the dynamic frame buffer. five regis The data is FIFO0output Timing 5equence Register er 2708 (FOTSR), which includes (located in local memory) ) describes how to read data from the frame buffer.

Memory to Video Transfer is a multicycle instruction. A specific number of pixels if it is executed is transferred from local memory 2700 to 0output FIPO. that command The parameters for are stored in FOTSR 2708 as follows.

The FOTSR format (32 bits) loads the data in the 0output FIFO. Used to specify parameters for how to read into local memory.

It has the same format as FITSR2410. The register has four fields. The fifth field is read from 0TSR2604. Immediately (6) DeltaOffset, (II) Modulo L, (4 ) Wait Cycles, and (6) (from OTSR) Number 　o■ It's a Pixel. The 11-bit In1tial Frame fMfset is Specifies the additional vertical offset added to the frame when displaying the image. do. For example, if an offset of 8 is specified, the output image will be It is displayed eight lines below what it previously appeared in local memory. 6 bit D elta0ffset is the vertical value added to the address of each operation. Identify the offset. If a Delta 0ffset of 2 is given, The first transfer has a vertical offset of zero and the second has a vertical offset of 2. , the third offset may have a vertical offset of 4, etc. It becomes. The 11-bit Modulo L field is used for vertical position calculations. Decide when to enter. The field holds a (limit) numerical value. for example, If the In1tial Frame offset is zero, then Delta 0 ffset is 4, Modulo L value is 15, continuous data transfer is on line 0. 4.8, ■2.1.5.9.13.2.6, etc. 4 bit Wait The Cycles field specifies additional clock cycles to wait before the transfer is complete. used to determine the number of cycles. Slow local memory is accessed This field is used if 6 bit Number of Pixe The ls field specifies the number of pixels transferred to the 0output FIFO . This number is always the same as for Video Display, so Parameters are not specified in FOTSR. However, it is still Mei This is a parameter for vory lo video Transfer.

Video 0output 0operation 5eLup is for each channel. Initialization of 0TSR, FOTSR, and FAG Registers with fold values The method is briefly explained. All of these numbers are user specific and process addressing information is received from the processor. There must be. To simplify the initialization and modification of this register, a local Memory section is reserved. The processor is a dedicated device that can be read by IOMc. Write data to a memory location.

Reserved memory locations are used for initialization, so changing video parameters The instruction to do this is executed as a / stem call. Among the parameters is the user There are some things that cannot and should not be specified. For example, the system The system allows the user to add parameters to a channel used by another application. must be protected from situations where an attempt is made to update the data. In this way, the A system call that can be protected from the situation is the video output operation This is the proper way to perform a startup.

Due to the feedback performance of SH, the data of Out 4T FIFO2600 is Write to the data output channel (DOC) and read to the Input FIFO2400. SE can be used to extract notes without involving other parts of the processor. data can be processed. Figures 27a to 27i show two memory It explains the peration process, in which one process rotates the numerical array and the other process replaces the numeric array. The memory organization is illustrated in Figure 27a. Simplification , only four processors (0 to 3) are shown, each with four processors (0 to 3). Address one memory location.

In Figure 27a, the four memory locations are mapped to each program using an offset of O to 3. addressed by the processor. The example below shows that the P processor is a numeric NXN This is the case when calculating with a matrix. Thus, in Figures 27a-27i , N and P are both equal to 4.

FOTSR, 0TSR to perform array transpose operations , FITSRl and ITSR registers are set as follows. FOTSR In the register, In1tial Frame Pa1nter 0ffset The field is set to (P+1) module ON. Defta 0ffset The yield is set to +1. Module o Set in L field N The Wait Cycles field is set to l. Also, Number The of Pixels field is set to l. In the 0TSR register, The In1tial Pixel Po5ition field is set to P.

The Pixel Repeat Interval field is set to N. N The umber or Pixel field is set to l. These registers controls the 0output FIFO to load the array in the order shown in Figure 27b. supplies numerical values to the data output channel (DQC).

In FITSR Lenstar, In1tial Frame Po1nter The 0ffset field is set to (P-14N) modulo N. Delta The 0ffset field is set to 1■. Modu1oL field is N is set to . Wait Cycles is set to l. Nu+nber The of Pixels field is set to l. In the ITsR register , In1tial Pixel Po5ition field is (P-1+N) Modulo Set to N. Pixel Repeat Interva The l field is set to N. Set Number of Pixels to l be done. These registers control the Input FIFO and are shown in Figure 27b. Data values are stored in the array from the DOC in the order in which they were received. Figures 27d and 27e are , via p in the memory array before and after the array transport operation. Another useful memory operation to represent each pixel is array rotation. It is an operation. In this operation, it is as if the array were rotated 90°. The contents of the array are reorganized as if it were Array rotation operation To execute, the FOTSR register is set to In1tial France Pa. 1nter field is P and Delta 0ffset field is +1 , the Modulo L field is N, and the Wait Cycles field is field is l, and the Number of Pixels field is 1. is set to 0TSR register is In1tial Pixel Po5ition field is P and Pixel Repeat 1nLe rval is N, and Number of Pixels is! as it is Set. With these registers, the 0output FIFO 2600 is The numbers will be supplied from the array to the DOC in the order shown at 27f.

To complete the operation, the FITSR register is The rame Po1nter 0ffset field is (N-P-1), Delta 0 (Eset field is +1, Modulo L field The code is N, the Wait Cycles field is I, and the Number The r of Pixel field is set to l. ITSR cash register The In1tial Pixel Po5ition field is (N-P -1), and the Pixel Repeat Interval field is N and the Number or Pixel field is set to l. be done. Using this number, the Input FIFO 2400 is set as shown in Figure 27g. Data values are stored from the DOC into the array in the order in which they are stored. This operation The result is shown in Fig. 27h, and the data values are transferred to Fig. 27i via p as shown in Fig. 27h. translated into the indicated rotational position. Control input/output FIFO2400/2600 Other configurations of registers are used to perform other mapping operations. FIG. 18a shows a circuit arrangement that is envisioned to be used for. this is To interface each of the processors with the IV via the associated IOMc used for. The 1V320 has an array of disk drives, which are connected to the SH. one for each processor. However, flash memory, magnetic bub other types of memory devices, such as random access memory devices, or even random access memory devices. It is assumed that the second memory is used as 1V320.

In Figure 18a, each disk drive interfaces with the 10MC It has a serial input/output section that connects to the section. For example, these are standard R5-23 2 connections. Data is transferred via parallel circuit to serial (P/S) interface. 1816 and a serial output connection. The data transmitted through the serial/parallel (S/P) interface 1818 be done. On the IOMc side, the data is sent to the P/31816 and the 39-bit F One kilobit is received from S/P 1818 by the IFO buffer. 3 The 9 bits include 32 data bits and 7 bits of error detection code (EDC). There is.

The FIFO 1810 also receives control information (i.e., data access) from the IV's disk drive. address) or supply control information thereto. This control information is the control circuit 1 82o to the data stream. transferred via control circuit 1820 The address value entered is a 23-bit value, and each number is separated into a separate 32-bit data word. Compatible.

Therefore, a typical disk drive can hold up to 32 megabits of data. . Data transferred via PIFo 1810 is 32-bit EDC encoded. 1812 or to a 32-bit EDC decoder 1814. depending on whether data is written to or read from the IV. belong to. Additionally, the EDC decoder 1814 decodes the error-decoded data. An l-bit error signal is provided to indicate that an error has been detected. respond to this signal The processor then attempts to access the data again or simply overcomes the error. control device or post.

In Figure 18a, four 32-bit outputs are used to send and receive data to and from the IV320. power channel and four 32-bit channels. As shown in Figures 17 and 18 This channel is multiplexed into local memory for input and output slices, as shown in be converted into

1v has a large database, probably because it holds relatively long image sequences. can be used to High data bandwidth resulting from high degree of parallelism enables image processing Rapid image acquisition for administrative applications and high-speed data acquisition for database applications. You will be able to search the database.

SE has MIMD performance. There is one controller for every 64 processors. , each controller broadcasts a different instruction stream to its processor be able to. This organization provides hardware support for synchronizing between control devices. provides the maximum MIMD instruction stream. Synchronization is the control device and its control between the receiving processors and between the control units. ALOR(LOR) The buses are used to synchronize the processor to the control unit, LOR bus, Gl obal OR (GOR) bus, and Neighboring LOR (NOR ) bus is used for synchronization between control devices.

Processor synchronization has its completion time dependent on local processor data Necessary for operation. For example, local data status is incorrect Until then, all processors may have to repeat the code section.

This causes all processors to remain constrained until they finish executing their loop code. The control device is allowed to broadcast a loop code. If the control device is stop broadcasting program code and continue program execution The LOR signal is used to signal when it is possible. The LOR signal is used by the processor to send a signal to the controller indicating that an event has occurred. Ru. The LOR bus is a single line from each processor to its controller.

The numbers on the OR bus are initially low, and each processor uses the LOR bits in its PSW. By setting this to , the upper signal of LOR is asserted (see FIG. 28). Everything If all processors assert their LOR signal, the LOR bus number will be high. The controller receives a signal to synchronize all processors. It will be done.

By definition, MIMD programs have multiple instruction streams. , which are asynchronous to each other and are computed independently. If appropriate, this instruction string The systems are synchronized, so calculation results can be shared. In SE, the control device is the same. By means of the following mechanisms used to stream can be executed. In Figure 29, each control device has a switch. It has a combination of LOR and NOR signals. switch network , connected so that only groups of consecutive control devices are synchronized with each other . Each control device can configure the switch configuration using software. Figure 30 shows the seven Fig. 31 shows a conceptual grouping of control devices, and Fig. 31 shows a switch network. The switch configuration for the configuration is shown.

The synchronization between the controllers is as follows. formed by a switch network The LOR/NOR bus is configured such that all sequencers via the bus assign upper-level signals. Execute so that the bus signal goes high only when the The control device controls other When the point in the code is reached where it is needed to synchronize with the signal, the PS Issue a command to the processor to set the LOR bit of w. all Since the bit is set in the processor, this action causes the LOR bus to go high. Ru. Then the controller goes into standby state and switches network to high wait for the bus defined by . A NOR signal means that an adjacent control device This is a signal that summarizes when the R signal is set. All controls are LO If you assert the R signal, the bus defined by the switch network goes high and its controllers synchronize.

The GOR bus is a bus that connects all control devices. This bus is Used in situations that require global synchronization of locations. One example is S This is when R is in time-sharing mode, and the new program's context clause is loaded. Ru. GOR synchronization is required when SIMO programs are synchronized and executed. This is to ensure that it starts. Another example is when the MIMD program is finished. This is the case. - Streams may end early, but all streams should wait for the program to finish before the controller signals that it is finished. Ru. As an example of using a LOR/NOR switch network, there is a concept called barrier synchronization. Consider lower level MIMD programming constructs. instruction stream reaches the barrier, other instruction streams participating in barrier synchronization You must wait until you reach the barrier.

If the controller encounters the barrier of its command no-ken, it will LO the upper level signal. Sends to R/NOR bus and waits for bus to go high. All controls are If the rear synchronization point is reached, the bus goes high and the participating controllers synchronize. do. As an example, consider FIG. In this example, the first sequence l , 2 are synchronized and the sequence 1.2.3 is synchronized.

Time division is the normal mode of operation for SH. remember the context clause There are two memory ports that can be loaded, so when switching between context clauses between programs, The intermission time is short (approximately 250 instruction cycles).

Additionally, programs can run on a subset of the architecture. SE is scalar Because it is designed as a blue architecture, the system has several small Reconfigured at EB level to operate as a system. Next, the program has a new configuration Load and run on a system subset to handle resource allocation for small problems can do.

Hardware support for real-time operating systems is provided by O5Board. It responds to requests from the SH's host workstation and controller.

O3Boa'd buffers requests from host workstations and controllers. Contains hardware queues to In addition, O3Board is a buffer memory The read and write operations are controlled by the post, control device, and IOMC. can do. The post and SE run at significantly different clock rates and are loosely Because it is coupled, O3Board is the only way to transfer data between two systems. Laws must be adjusted.

Additionally, the control unit offers additional hardware support for multi-user environments. There is a Each control unit has jobs, including pending jobs, scheduled for execution. Has a queue. (O3Board has full control over scheduled jobs. broadcast to the device, but the control device is not scheduled in the job queue. There is. ) The controller has process table memory and polling hardware. There is. Process table memory is sl! Contains information about the processes that exist in I'm reading. Polling hardware prevents real-time jobs from being scheduled to run. Decide when you need to do it.

The O3Board is a Motorola 68040 processor or equivalent device. It has an operating system that continuously monitors the O3Board queue. run the system program. It is from the active program and host It waits for incoming requests and responds to one request at a time. Requests have priorities.

Some activities can be executed immediately, such as a real-time program execution schedule. Some activities have to be performed, and some other activities require Some things are not bound to run in real time like loading priorities is low. A standby request has a low priority, but the O3Board does not enter it from the queue. Executed when reading . High-priority items that need immediate attention The request is executed by interrupting the O3Board processor program.

In order to guarantee that a set of real-time programs can run together, a new proposal The issued real-time program can be executed in a manner compatible with existing real-time programs. The following rules are used by the RAP when deciding whether to That is, , a real-time program (including overheads like context clause switching) The total execution time is based on the standard (shortest) frame time (frame bar) of the real-time program. (time to load the buffer) should be less. This applies to each program. This guarantees that the ram can be executed once for each reference frame.

This is a conservative estimate. Most real-time programs use longer frames using time. Therefore, the situation must be handled by the program. You are overestimating the number of times. Real-time program execution time is profiling and determined through user estimates.

Scheduling real-time programs is a first priority requirement. real time di The job is prepared to run every time another framebuffer is loaded. . Each control device performs frame synchronization ( It has a polling register that polls the F synchronization) signal. (Real time program (due to completion of a run or non-real-time job slice) Each time a block is completed, this register is read and reset to A series of jobs are scheduled. More than one F synchronization signal is read. If so, the job will be scheduled with the shortest frame time first. New F If there is no synchronization signal and there are fewer than two jobs scheduled to run, , the O3Board schedules available non-real-time jobs for execution.

A control device is a controller that interacts with operating system activity. It has 14 components. That is, Polling Register, P o1l Correspondence Table (PCT), Job Queue (JQ), Job Finished Signal, Time Quantum@Regis ter (TQ), Time 5lice Counter (TSC), Pr ocess Table Memory (PTM), Pr Shield Mo■Tang■ Base Registers (PBRs), Ilo Request S ignal, Ilo Ready Signal, )IInR, In5t ruction Memory, PC stack memory, and Loop stack It's memory.

Polling Register is four pit registers, each bit corresponds to Data Input Channel. That register is the last After Paul checks it, Frame 5ynchronization (F 5ync) Used to poll whether a signal is being received. a Tomic instructions are used to read and reset registers.

If the F synchronization signal is received, the corresponding bit is set to Polling Regis. ter, it indicates that another frame of data has been loaded into the system. and that real-time jobs that use the data can be scheduled.

The PCT sends the polling signal summarized in the Polling Register to the D Related to real-time programs that use ata Input Channel used for.

JQ selects the queue executed on the hardware containing the next job number for execution. - is. JQ receives jobs from O3Board and determines which jobs are scheduled. Determine which module is used. When the control device prepares a job to be executed, Delete the ob Queue head.

Job Finished (JF) Signal indicates that the current job When the execution of the slice is completed, the controller jfO sends O3[1oard. This is a signal that A signal is sent to the O3Board so additional jobs can be scheduled. can be

TQ is the number of times a non-real-time job is allocated when a real-time job is executed. used to determine. The TQ value is used for non-real-time jobs to run Loaded into the TSC when scheduled.

TSC is for calculating the number of cycles a program is allocated for execution. used for. The time slice value is loaded into a counter and It will continue to decrease. If the counter decreases to zero, program execution is interrupted. the controller is then prepared to run the scheduled program. . Time 5lice for real-time programs is Process Cont It is obtained from rolTable (PCT). for non-real-time programs Time5lice is obtained from TQ.

The PTM contains program information for each program. It's a program Information such as Ram context clause information and In5truction and Local (Data) Ba5e Address for the program in Memory Contains s.

One set of PBRs consists of 16 registers, each of which corresponds to the page being displayed. Holds the base address of the PTM Entry for the job. at a specific time Hardware burden of 16 programs (real time and non-real time) that can run SE There is a limit.

For example, PBR5 is the base address of the process table entry for job 5. maintains a

110 Request Single is an O3 request from the control device requesting 110. It is sent to the IOQ located on the Board. The request is a program that requires Ilo. This is the job number of the program. When the O3Board examines the request , the job is scheduled for Ilo. More information about host I/O Detailed information is as follows.

Ilo Ready Signal indicates that the program running on the control device is s signal indicating that the information in the s buffer has been loaded or read. Used to send to O3Board. More information about host I/O can be found below. As written.

HIOR allows the control device to exchange data with the Ho5t Workstation. This is a register that is accessed when necessary to do so. It is the old OBus Part of it.

Instruction Memory is where the instructions for the program are in the SE. It is a place where you can Memory has multiple ports, so you can use the program to can be loaded and another program is read out (for execution) Ru.

Program Counter (PC) is where information for function calls is programmed. This location is maintained while the program is running. Each PC5tack has each user program It has three dedicated registers consisting of 16 sets, one for each RAM. They are PCBa5e, PCLimlt, and 5tack Po1nter Reg isters. These registers delimit the program's data in memory. It is used for accessing. Does that memory have multi-ports? allows a program to load memory and another program to load memory. is read (for execution).

Loop 5tack Memory is used with special loop hardware This is the location where the information that is displayed is stored during program execution. Each Loop 5tac k has three dedicated registers consisting of 16 sets for each user program. They are LoopBase, Loop Limlt, and Loop OP 5tack Painter Registers. These cash registers Stars are used to separate and access program data in memory. . That memory is multi-ported, so when you load the memory programmatically, Also, another program is loaded (for execution).

Interactions that IOMG has with operating system activities Only the remote control can read and write to HIOR, which is part of the old OBus. . Decisions to read and write to this register are sent from the controller to the IOMG. It will be done.

The host sends Ho5t Request Signal, )lost Sig Operating system activities such as nal and Ho5t Bus It has three components that interact with the user. In addition to this, host Software running on the machine allocates machine resources and sends HIQ requests. Role of servicing uests and reading and writing data to files or terminals There is.

Ho5t Request Signal is sent by the host to O3Board At the signal, add the job to the ost Request Queue. is for program loading, program killing, and program reloading. Contains deing. Ho5t Signal is sent by the host to O5Board. In order for the host to complete the O3Buffer read and write with the signal sent to the O3Buffer. This indicates that execution has been completed.

HIO is a 32-bit bidirectional connection that connects all IOMcs and control signals in series. bus. Transfer data to old OR until data is stored in O3Buffer By loading and shifting the )110 bus to the left, that data is transferred to O3 Written to Buffer. Similarly, a write to IOMc indicates that the data is Read the O3Buffer and move the data to the right until it reaches HI [lR of This is done by shifting.

The RAP resides on the host, maintains resource allocation information, and responds to new submissions. Determine whether the program can be executed. RAP is the system's Physi Cal　5specification information and system current It holds information regarding 5tate. Physical 5 specifi cation information is Total N number of Functioni ng Process Tang Shield ■ s + Physical Data Memory 5tze, and Phys ical In5truction Men+ory 5i 嘯■■■ I'm reading.

Currer+t System 5tate information is In5truction Memory MapSLocal Memory Mabuki B PC5tack Map, 1. oop 5tack Map, Ilo Re 5source Map and Reference Fram■@Time Contains Map. The first four maps above relate to different memory allocations. Provide information on The map is used to determine the amount of fragmentation that occurs in various types of memory. used. Resources exist for the program, but memory fragmentation If you want to prevent the program from being loaded continuously, use Re5source. A11ocator may send requests to relocate non-real-time programs. can. A real-time program will be completely relocated by the next time it needs to run. is not guaranteed, so it cannot be relocated. Ilo Re5source Ma p indicates that IloRe5sources is used. lastly , Reference Frame Time Map is for real-time processing. Determine your instruction budget or whether you have enough time to run non-real-time jobs. Decide whether to use it or not.

The Reference Frame is the first frame of all active real-time programs. Defined as short frame time. Re5source A11ocator is It operates according to the following rule called Reference Frame Ru1e.

All real-time program instruction counts (including all possible real-time programs) If the total is less than or equal to the size of the Reference Frame, A real-time program is scheduled for execution. What this rule states is , (each program must be executed once for each Reference Fra+ne) All programs are executed under the strictest assumption that If all programs can run under relaxed conditions, the condition is Some programs have less than once per Reference Frame Time. There are some (long) frame rates that mean some actually run ).

RA where the real-time program changes the Reference Frame Rate (This means that the submitted program is the currently running program.) ), the instruction budget will increase at this new frame rate. Therefore, it must be recalculated. The running program and the program under consideration are If this instruction budget is not exceeded, load the program and ranceFrame must be updated. Similarly, Reference e If the Frame Rate program operation control is completed, the life The new Reference Fratne has the effect of increasing the budget. It is determined.

Whenever a real-time job is loaded or terminated, the The TQ is updated. The TQ value is the same as when a non-real-time job executes a real-time job. Determine how long the scene will run. The explanation of Time Quantum value calculation is below. It is written down.

If a program terminates, RAP uses the resources used by that program. Release the source. Typically, a map representing a newly available resource is I updated the knobs and recalculated the Reference Frarne as much as possible. This means updating the 105 Program running on the host.

In Real-Time Job Scheduling, the last job is Receives JF Signal from the control device indicating that time slice execution has finished. After the O3Board is located on the O3Board and the Job Queue Decrease the Job Counter that tracks the job number in .

The O8Board determines which real-time jobs are ready to run.

This means that when checking the Polling Regtster of the control device O, Fr If any of the ame5syncronization (F5sync) signals It is determined whether it has been generated. If an F synchronization signal is received, the corresponding The polling bits are set in the Polling Register to indicates that the system is loaded on the system. The actual entity that uses that data Time jobs can be scheduled. O3Board is F5yn Read the Polling Register so as not to miss any of the c signals. Use atomic instructions to issue and reset.

Next, the O3Board determines the relationship between the bits of the Po1l Register word. Determine real-time jobs that use and Data Input Channels Please refer to the PCT for this purpose. There are four entries in the PCT. Each entry is Contains the number and Input Channel Frame Rate. .

All real-time jobs whose F5sync signal is polled will thus Scheduled for IQ at the location. One or more jobs are scheduled. If the priority is determined by the PCT, the Frame Ra for the job is specified by the PCT. It is determined from the te information. Priority is the highest speed frame (Fas test Frame Rate First).

JCTL increases with the number of jobs added to JQ.

If the real-time job is not scheduled, O3Board will Determine whether there are any non-real-time jobs to be run. O3Board is a job Check the Counter. If there are less than 2 jobs in JQ, Non- Entry is made from Real-Time Job Queue (NRTQ), Added to JQ. This condition is maintained, so JQ is always ready to execute. There are jobs available. There is only one job running on the system in multi-user mode. If so, a dummy job is scheduled to run. system Job execution must be scheduled like a host request to load a program. This can also be used if there is only one active jigob, as this may be necessary. Conditions are maintained.

O3Board Re5ident Program (I (via RQ) requests from the host, the control unit (via 110 Queue), and another job. job finished signal). Operate Operating system programs often ball requests and respond to requests as they arise. is modeled as an endless loop that executes The model is O3Bo Used in the ard program and must constantly check for new zero requests. No.

The first priority of operating system programs is Job 3chedu 1ing activity. Running real-time jobs and associated time constraints are tight. Therefore, when the JOb Finished signal is generated, another job is immediately executed. There is a strong need to schedule. Also, lower priority requests (Ilo and host request) can take a long frame time to execute, so Job Sc Heduling should not wait after one of these requests. In this way, J ob Scheduling activity is an operating system program executed as interrupting RAM.

The next priority level is response to host requests and controller requests to Ilo. Ru. At this point, there are no more important burdens than priorities. However, the priority system Since the system is implemented entirely in software, there are no issues regarding relative priority. The issue is being deferred to the future.

The following explanations are simplified and suspicious for operating system programs. Similar code.

main program loop forever [ exam)IRQ update SSRif new job request pending if not empty, process host requestex amine l0Q update SSRif new job request pending if not ew+pty, process Ilo request] scheduling 1interrupt: (11JFsignal.

[ 5 chedule a real time jobif no real ime job available and 1ess than 2jo bsschedule a non-real time jobif a n ew job request is on HRQ or IOQ, rese t SSR Entry] Traditional debugging techniques have problems for highly parallelized real-time programs. is presented. This technique typifies instructions into a program to help debugging. Add the target. However, this code does not support IPc operations or delayed braking. Interferes with time-critical code segments such as pinching, but does not interfere. S In E, control bag 5! IW (7) Debug Interrupt (DI) is used to mark an instruction, about which the program is Debug Interrupt H located in the reserved area of the instruction memory of the control device Interrupt against andier. This hardware for debugging in the present invention hardware support means that the program runs without inserting any additional code. Provide breakpoint facilities that allow you to: A specific bit is set in the program IW. debugging routines are automatically controlled. Deva During execution of the programming routine, the operator The control unit, local memory variables, and the state of the processor's registers The condition can be inspected. Control is programmed as soon as you exit the debug routine. Return to mu. Since the interrupt is based on a single bit of the controller IW, Debug routines can be called during instruction execution in the controller program. Wear.

Also, large datasets that require solving both heavy calculations and data communication. There are many other problem areas including: Examples are weather modeling, medical Image, computer vision, molecular modeling, VLS I-imulation. as well as neural networks, volume, visualization, and and polygon rendering.

The invention is illustrated by the operating apparatus and method described herein. I can understand that. Easily modified by those skilled in the art without departing from the spirit and scope of the invention. You can also add

lnji'bu A hook FIGURE4 FIGURE5 FIGURE 8 FIGURE 9 CDABDCA Ma Sochi Sequence ABCD ABDCABAD CCBD ABCD DBCB...FIGU RE　13 FIGURE 16 Excitation slice (4-pronged rice/4-rough 0) FIGURE 17 FIGURE18 ・1νOdatum tn I FIFO word Data Format 1 ( 12 bits): M-===ko] Scale C・2 Ilo data to l F IFOwordData Format, 2 (24bits): Myu 12 it 12 bits’″3 Ilo data to one FIFOwo rdDataFormat3 (32bits): M, , ko, “FIGul ’:IE 19 Composle Video 12 bitsRGB (Multiplex ed) 10 bits 10 bus 10 bitsRGB (Dedic alecl Channels) 12 bitsF1GU self 20 Scheme 1: Scheme 2: FIGUI”lε23 [] 10MC Chiff “1: Azu3 Fa Ri Audience FIGURE 25 Rocco 411　F1n’)shif’　HGURE26χしIREKun-1〉Su1　4ketoshi Kens 2 Imperial Sequence 3 FIGURE 32 FIGURE 33 Continuation of front page (72) Inventor Beaters, Joseph Etward Jr. New Chassis, United States 7 Austin Drive, East Brunswick, 08816 (72) Inventor Tiller, Barbert Hudson Jr. New Chassis, United States 5 Tamburland Road, Pennington 08534

Claims (1)

[Claims] 1. N blocks, where N is an integer, and each block is M processors, where M is an integer, and each processor has an arithmetic logic unit (ALU), a local memory the M processor, including memory, and input/output (1/O) interfaces. A controller connected to provide the same group of instructions to each of the M processors and M processors. host means for selectively coupling said N blocks comprising control means and control means of said N blocks into at least first and second block groups, each group comprising P blocks, where P is N blocks; For each group with P blocks, the same A parallel computing system comprising: a host means in which respective different groups of processor instructions are provided to each of M times P processors. 2. Each of the M processors in a block has an interprocessor communication (IPC) channel. channel that allows the processor to place data values within the block. can be transferred to other processors of M processors in a block, and can be transferred to other processors of M processors in a block. A method for programming the M processors within that block to determine the The control means of each block includes a stage, in which each of the processors within any one boundary Each processor can communicate with another processor within its one boundary via the IPC, creating a data communication bus to each of the groups with P blocks. means for selectively combining N groups of IPC channels with means for controlling each of the M processors in the respective block, wherein the PC channel connects the M processors in one of the blocks in the predetermined sequence; selectively programming each IPC channel to a) passing a data value received from a processor to the next processor in the sequence without receiving the data value; b) passing the data value to one or more processors in the sequence; multiple pros 2. The system of claim 1, including means for receiving data values sent to the processor. 3. Each processor conditionally executes instructions given by means for indicating local data conditions within the processor and control means based on the indicated local data conditions. 2. A system as claimed in claim 1, including means for determining. 4. a plurality of processors, each having: a source of a system clock signal; an arithmetic logic unit (ALU); a means for indicating local data conditions within the processor; local memory; and an input/output (I/O) interface; and profiling counters are installed. When enabled, has a counter value that is incremented in response to the system clock signal. a plurality of processors, the plurality of processors comprising a profiling counter; a control means responsive to the control instruction and coupled to provide the same group of processor instructions to each of the plurality of processors; and a control means for providing the control instruction and the processor instruction to the control means. A parallel computing system comprising a host means for each profile in Enoki's processors. Fields used to enable and disable ring counters The parallel computing system wherein each processor instruction includes a field. 5. Separate program with count value that is incremented only when the counter is enabled. The control means includes a filing counter, and the control means has a profile. each of the control instructions includes a field for selectively enabling and disabling a counter, and the control means is configured to control the controller. In response to the first of the command commands, the data associated with the immediate value and the control means are One of the values obtained from the data register is used as the profiling counter of the control means. and in response to the second of said control instructions, records the count value in the data register, and each of the processors responds to its first processor instruction. the immediate value and one of the values obtained from the processor's local memory. 5. The system of claim 4, wherein the system loads a profiling counter of the processor and records the count value in local memory in response to a second processor instruction. 6. A processor suitable for use in parallel computing systems that stores operand values. an arithmetic logic unit (ALU) that performs arithmetic and logic operations on operand values; a multiplier separate from the ALU that generates the arithmetic product of the first and second operand values; and a match unit separate from the ALU. and the bits from the memory means. Count the match numbers between the bit pattern and the bit sequence, and The processor includes a match unit that generates a count value indicative of a detected match number between a subsequence of a sequence of bits and a subsequence of bit sequences. 7. The matching bit pattern has a number of bits smaller than the number of bits of the bit sequence, and the match unit records a sequence of templates representing each possible match position of the bit pattern and the corresponding bit pattern of the bit sequence. The means for A means for comparing a bit sequence and all templates in a sequence, and giving the count match between a bit sequence and a template as a match number. 7. A processor as claimed in claim 6, including means for obtaining. 8. A multiplier is coupled to generate an arithmetic product as an input operand to the ALU. the match unit is coupled in parallel to the multiplier, the bit pattern is included in the first operand, the bit sequence is included in the second operand, and the count value generated by the multiplier and the arithmetic product generated by the ALU are only one of them is presented as an input operand to the ALU at any given time, and the ALU responds to an instruction word containing a first subfield and a second subfield to field is used by the ALU to perform one of the arithmetic and logic operations, and the second subfield The code is used by a multiplier to generate an arithmetic product or a matcher to generate a count value. The processor according to claim 6. 9. The processor according to claim 6, further comprising: a first accumulator; and a second accumulator; The ALU is coupled to feed both simultaneously. sa. 10. means for providing a processor instruction word; memory means for maintaining a plurality of arrays of operand values; an arithmetic logic unit (ALU) having first and second input ports coupled to receive and select a respective operand from a first of the plurality of arrays of operand values for providing to a first input port of the ALU; , coupled to the memory means, the first frame of the instruction word; first address generating means responsive to the first field, coupled to the memory means for selecting a respective operand from a second one of the plurality of arrays of operand values and providing it to a second input port of the ALU; is the second field of a different instruction word. A processor suitable for use in a parallel computing system, comprising second address generating means responsive to a field. 11. Each array of operands has a lower boundary address and an upper boundary address, and each of the first and second address generating means determines that the generated address value is invalid and therefore Specify whether to generate an out-of-bounds signal by specifying whether it is smaller than the lower boundary address or higher boundary address. means for determining whether the address value is greater than the address value, and means for responding to an out-of-bounds signal and converting an invalid address value to a predetermined address value, the predetermined address value being 11. The processor of claim 10, further comprising: means for addressing a predetermined operand value within an upper boundary and a lower boundary of a second operand. 12. P processors, P being a parallel number, each processor coupled to a source of a clock signal having a predetermined frequency; an arithmetic logic unit (ALU) capable of performing at least one arithmetic operation during one period of the clock signal; and a local memory coupled to retrieve and record data values in synchronization with the clock signal; control means coupled to provide instructions to each of the P processors; A processor coupled to each of the P processors for transferring data values between processors. an inter-processor communication (IPC) means coupled to each of the P processors and a bus comprising means for transferring a clock signal, the data clock signal causing the IPC means to transfer one of said data values on the bus during each pulse of the data clock signal; The one PC means is responsive to the control means to generate data at a first frequency substantially equal to a predetermined frequency. a clock signal and output a clock signal at a second frequency approximately equal to N times the predetermined frequency. 1. A parallel computing system comprising means for providing a computer clock signal, N being an integer greater than one. 13, P processors, where P is an integer, and each processor has an arithmetic and logic unit. The P-processor contains the local memory (ALU) and local memory for holding data values. control means coupled to provide instructions to each of the P processors; Inter-processor communication (IPC) means coupled to each of the P-processors; A bus containing means for transferring data values to each of the processors, capable of transferring 2N bits at a time, where N is an integer, stored in local memory. the bus, each of the data values held therein being an N-bit data value, and the bus being responsive to the control means for causing the bus to transfer data values in one of first and second opposite directions between the processor sequences; , first and second separated N-bit buses; IPC logic for allowing the bus to operate as a 2N-bit bus or as one 2N-bit bus 1. A parallel computing system comprising: said one PC means including a processing means. 14, N blocks, where N is an integer, each block having M processors, where M is an integer, each processor responsive to processor instructions and having an arithmetic logic unit; a control means responsive to the control instructions and coupled to provide the same group of processor instructions to each of the M processors in the block; The N blocks containing the N blocks, and the control instruction and the processor instruction are given to the control means of each of the N blocks. a host means coupled so as to control each block; control instructions and processor instructions given to each other block. A parallel computing system comprising said host means different from and processor instructions. 15. Each of the M processors in each block has an interprocessor communication (IPC) channel for responding to IPC instructions and transferring data values between the M processors in the block. a means for indicating local data conditions within a processor; means for conditionally executing processor instructions responsive to the means for and a separate group of IPC commands for each PC channel. 15. The system of claim 14, including means coupled to an IPC channel of each of the M processors. 16. P processors, where P is an integer greater than 1, each processor having: memory means having N memory locations for holding N data values, where N is an integer greater than 1; means, coupled to the memory, a first output controller; reading said N data values from memory locations in the memory means in the order determined by the signal; output data buffer means for inputting and providing read data values at instants determined by a second output control signal; and output data buffer means coupled to the memory for receiving data values at instants determined by a first input control signal. , and input data buffer means for applying the received data value to said memory location of the memory means determined by a second input control signal, wherein the data value provided by the output buffer means is the data value received by the input buffer means. means for coupling the output buffer means and the input buffer means, and providing first and second output control signals and first and second input control signals, stored in respective memory means of the P processor; A parallel computing system that includes programmable control means for reordering data values. 17. Each of the P processors is identified by a unique processor identifier value, and each processor's memory means is recorded at the memory location indicated by the offset value. responsive to the offset value for accessing one of the N data values, programmable control means provides a first output control signal and a second input control signal to each of the P processors to specify the offset; including the means of an offset of P is used to access the N data values stored in the memory means, and the first output control signal and the second input control signal are offset from P and P, respectively. 17. The system of claim 16, wherein: and N different functions. 18, M processors, where M is an integer, and each processor has an arithmetic and logic unit. a controller coupled to provide identical processor instructions to each of the M processors; control means, giving a control instruction to the control means, and giving a processor instruction to the M processor. a host means coupled to a control means for controlling a process table that maintains information on real-time and non-real-time processes executed in a parallel computing system; memory, a port for determining when a real-time process should run on a parallel computing system. resource allocation means for allocating processors to processes running in parallel computing systems. queuing means for queuing real-time and non-real-time processes executing in the parallel computing system; and queuing means responsive to a synchronization signal for removing a process from the queuing means and directing the assigned processor to do so. schedule for executing the specified process A parallel computing system comprising said host means comprising a cursoring means. 19. Process table memory is used to store real-time processes executed in parallel computing systems. For each process, the predicted program execution time and predicted frame time are maintained, and the combined program execution time of all processes in the queue is summed. The resource allocation procedure is executed only when the program execution time of the new real-time process added is less than the minimum frame time of any process in the queue. 19. The system of claim 18, wherein the stage allocates processors to new real-time processes. stem.