JPH07509113A - Device for installations for the formation of digital radio links between fixed and mobile radio units - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Equipment for the formation of digital radio links between fixed and mobile radio units The direction is the device Conventional technology The present invention provides a digital radio link between a fixed radio unit and a mobile radio unit. Forming equipment relates to equipment.

A device providing such a radio link is described in British Patent No. 9304901.3. It is written in the book. The specification includes, for example, the in-phase composition of a wideband pilot signal. Use of a Wiener set filter etc. that predicts well the amplitude of the minute and quadrature component Q It describes about.

Wideband binary phase shift keying using pilot signals (BP) S K) A known form of the Wiener set filter used in radio receivers is shown in Figure 1. vinegar.

The RF input signal passes through a filter 2, and the output side of the filter 2 is a half-linear multiplier. It is fed to the input side of the calculator 4.6. The local oscillator 8 has a phase shift of 0/90°. The phase shifter 9 converts the local oscillator signal into a half-linear A signal of 90@phase is supplied to the second input terminal of the multiplier 4 of the half-linear multiplier 6. is supplied to the second input terminal of. The output signals from each half-linear multiplier 4 and 6 are , to a plurality of rake fingers 10.12.14.16. each lake fin The moth has a pilot correlator 18 and a signal correlator 24, and the pilot correlator The output side of the signal correlator 24 is connected to a Wiener set filter 20, etc. The output side is connected to a delay circuit 26. Each correlator 18.24 has a half linear A receives the output signal from the multiplier 6. Wiener set filter etc. 20 and delay circuit The outputs of circuits 26 are multiplied together in a multiplier 22, the output of which is A first input of line 28 is provided. Each rake finger also has a pilot correlator 30, and the output side of the pilot correlator 30 is connected to a Wiener set filter 32, etc. It is connected. Signal correlator 36 has an output connected to delay circuit 38 . The pilot correlator 30 and the signal correlator 36 are connected to each other from the half-linear multiplier 4. receive the output signal of

The output signals from the Wiener set filter 32 and the delay circuit 38 are processed by a multiplier 34. The output of the multiplier 34 is supplied to the second input of the adder circuit 28. addition times The output signal generated in circuit 28 is supplied to another adder circuit 40, which 40 sums all output signals from the remaining rake fingers 12.14.16. The zero multiplier 22.34 is a four-quadrant multiplier with multiple bits of precision on the input side. be. All circuit configurations shown for rake finger 1 also apply to other rake fingers. The same is true. The only difference between each rake finger is that they are received via different routes. A correlator is a pseudorandom sequence timed to correlate with the signal being received. The architecture shown in Figure 1 is intended to be fed to different lake fields. satisfies a fully coherent maximum ratio. Vienna Multiplication with the output of the set of filters not only compensates for the phase of the signal, but also The amplitude of each rake (finger) component is weighted according to its signal strength.

It can be seen that the circuit described above is suitable only when using pilot signals.

Referring to FIG. 2, another form of construction such as a Wiener complete filter is shown, The above form is DBP5K (Dual Binary Phase Shift Keying) demodulation. It can be used for. When demodulating DBP5K without pilot reference signal Also, carrier reference signals can be obtained and used by determination for the purpose of carrier extraction. Can be done. Here, the samples fed to the Wiener set filter etc. are the reference signal It is modified according to the data judgment to supply the signal. In Figure 2, multiple rays Kufinga is marked 42.44.46.48. Each rake finger is in phase A signal correlator 50 for processing the signal and another signal correlator 52 for processing the quadrature signal. have. The output signal from the correlator 50 is output via a 1-bit delay circuit 53. - is supplied to a linear multiplier 54. The output of the half-linear multiplier 54 is It is supplied to the input side of a filter set 56.

The output of the Wiener complete filter etc. 56 is provided to a multiplier 58. Also, the correlator The output of 50 is fed to another input of a multiplier 58, the output of which is It is supplied to the first input terminal of the adder circuit 60.

The output signal from the signal correlator 52 is converted into a half-linear signal via a 1-bit delay circuit 61. is supplied to the multiplier 62 of. The output of the half-linear multiplier 62 is It is supplied to the input side of an expression filter or the like 64. The output of Queener set filter etc. 64 is , are supplied to the input side of the multiplier 66. Further, the output signal from the correlator 52 is multiplied by The output of the multiplier 66 is supplied to the second input of the adder 60. Supplied to the input end. The output of the adder circuit 60 is applied to the other rake fingers 44, 46 . 48 to an adder circuit 68, and the adder circuit 68 adds all the input signals. The calculation result is generated and supplied to the determination circuit 70. The determination circuit 70 simply determines whether the signal is high or not. The output of the determination circuit 70 is passed through the latch circuit 71 to (1) 42 to the second input of each half-linear multiplier 54, 62. banked and also feeds half-linear multipliers in other rake fingers as well. back, each Wiener set filter etc. in rake finger (1) 42 56.6 4 and similarly modified in other rake fingers. . The output of decision circuit 70 is a differential signal configured to output data on output line 74. It is supplied to the input side of the decoding circuit 72.

The circuit shown in Figure 2 uses all rake filters to remove modulation from the received signal. It uses a hard decision that is performed using summation values that span over 300 Hz. The best for river use Since the new judgment value is the preceding judgment value, in order to remove the modulation, this preceding judgment value is used. , must be applied to the previous sample delayed by one sample. This delay is By using a Wiener set filter etc. that operates as a one-step predictor, removed from the resulting channel prediction. Inevitably, this means that channel prediction The dispersion is a system that captures a pilot signal to which symmetric filtering can be applied. This means that the dispersion of the stem is greater than the dispersion of the stem.

The problem of the present invention is to provide a Wiener complete filter having functions improved from the configuration of the prior art. Digital radio between a fixed radio unit and a mobile radio unit using a configuration such as a The aim is to supply equipment used in equipment that provides links.

According to the invention, it is adapted to generate a data output signal and a feedback signal. It has a plurality of circuit means and a processing means respectively configured, and the circuit means has an in-phase input. an in-phase channel and a quadrature input signal configured to receive a power signal and a quadrature input signal, respectively. The processing means includes a Kuina set filter for the literary channel, and the processing means receives the input signal. determining the nature of said feedback signal to be supplied to each circuit means to modify the provides a digital radio link between fixed and mobile radio units In equipment used in equipment that symmetrical filters, and the output from each Winner set of filters is and the output from the pre-sample symmetric filter is processed by the output data signal A fixed wireless unit and a mobile wireless unit characterized in that they are used to generate A device can be provided for use in equipment that provides a digital wireless link between clients.

Next, embodiments of the present invention will be described with reference to the accompanying drawings.

drawing FIG. 3 shows a block diagram of a dual path determination contemplated demodulator according to the invention.

Figure 4 shows a block diagram of the two-stage Wiener set filter used in the configuration shown in Figure 3. vinegar.

FIG. 5 shows an alternative embodiment that is a simplified block diagram of the demodulator shown in FIG.

FIG. 6 shows another implementation of the Wiener complete filter shown in FIG. 4 for use in the demodulator shown in FIG. An example is shown.

FIGS. 7 and 8 show the demodulator and winner set files shown in FIGS. 5 and 6, respectively. 3 shows another embodiment of the filter.

9 and 10 illustrate processing of multiphase differential phase shift key ink (MDPSK) 2 shows a block diagram of another embodiment of the present invention suitable for.

FIG. 11 shows another embodiment of the block diagram shown in FIGS. 9 and 10.

Example Referring to FIG. 3, a demodulator with multiple rake fingers 76, 78, 80, 82 equipment is shown. Each rake finger includes a signal correlator 84 that processes the in-phase signal. , and a signal correlator 86 for processing quadrature signals. The correlator 84 has a 1-bit The input side of the delay circuit 87 and the input side of the multiplier 90 are connected to each other. 1 bit slower The output side of the extension circuit 87 is connected to the input side of a half-linear multiplier 88. The output side of the calculator 88 is a one-step prediction filter 92 and a preceding sample symmetric filter. 94 and a signal shift register 96. 1 step prediction filter The output of 92 is connected to another input of multiplier 90. Leading sample symmetry The output side of the filter 94 is connected to the input side of a multiplier 98 and a signal shift register. The output of 96 is the output of a 0 multiplier 98 connected to another input of a multiplier 98. The side is connected to the input side of the adder circuit 100.

The signal correlator 86 connects the input side of the 1-bit delay circuit 101 and the input side of the multiplier 104. and is connected to. The output side of the 1-bit delay circuit 101 performs half-linear multiplication. The input side of the multiplier 102 is connected to the input side of the multiplier 102, and the output side of the multiplier 102 is connected to the one-step prediction block. The input side of the filter 106, the input side of the pre-sample symmetric filter 108, and the signal It is connected to the input side of the foot register 110. 1 step prediction filter 10 The output of 6 is connected to another input of multiplier 1.4. The output of multiplier 104 The input side is connected to the input side of an adder circuit 112, and the adder circuit 112 has a second input The output of the multiplication circuit 9o is received at the end. Output side of preceding sample symmetric filter 10B is connected to the input side of the multiplication circuit 114, and the output side of the signal shift register 110 is , the output side of the zero-power field circuit 114 connected to another input side of the multiplication circuit 114 is It is connected to another input side of the adder circuit 100. Each rake finger is The output signals from each adder circuit 100 are added by an adder circuit 116. Ru. The output side of the adder circuit 116 is connected to the limiter 118. The output side is another of the preceding sample symmetric filters 94.108 in each rake finger. Connected to the input side to invert inaccurate samples.

Further, the output side of the adder circuit 116 is connected to the input side of the half-linear multiplier 126. has been done. As mentioned above, each rake finger has an adder circuit 112, The output side of the circuit 112 is connected to the input side of the adder circuit 120, and the adder circuit 120 has an output connected to a limiter device 122. Output of limiter device 122 The force side is another input of each half-linear multiplier 88, 102 in each rake finger. The input side of the data shift register 124 is further connected to the input side of the data shift register 124 .

The output side of the data shift register 124 is connected to another input of the half-linear multiplier 126. connected to the power side. The output side of the half-linear multiplier 126 is delayed by 1 bit. It is connected to the input side of circuit 128 and the input side of multiplier 130 . 1 bit slower The output of the extension circuit is connected to another input of the multiplier 130. 1 bit delay Circuit 128 and multiplication circuit 130 constitute differential decoding circuit 132.

Next, the operation of the configuration shown in FIG. 3 will be explained.

The configuration shown in FIG. 3 improves the performance of the prior art configurations of FIGS. It is improved by combining the beneficial effects of each component. This means that This is achieved by using a second path to demodulate the data. fundamentally, The processing is as follows.

Similar to when the tentative decision is used in the architecture shown in Figure 2, one step is required. A tentative determination is made based on a prediction filter. At the same time, these preliminary judgments is used to feed a symmetrical pre-sample filter 94.108, said Filters 94, 108 pass the channel estimate corresponding to the current sample to a later time. to be generated. With this new sample available, the previous trial court should be more accurate. Any test for 0 that can be used to validate or invalidate the The modification is not only on the output side, but also on the second component of the longer-term Wiener complete filter. It can also be supplied to half of the eye.

As previously mentioned, the configuration shown in Figure 3 is compatible with known piping for the respective operations. It combines the characteristic parts of Figures 1 and 2 that use lot signals and judgments, respectively. Ru. In FIG. 3, the block labeled 76, rake finger 1, is a mirror image. It shows the circuit of the allegorical part and the circuit of the imaginary part drawn as . inner components performs determinations aimed at the circuit operation of the prior art shown in Figure 2, while The side components perform the pilot reference detection operation of FIG. 1 step prediction ilters and leading sample symmetric filters 92.94 and 106.108 will be explained later. By performing the two filtering operations together, as shown, the desired complexity They are each shown combined into one block, so that a reduction in complexity can be achieved. It is.

The operating principle is as follows. The one-step prediction filter 92.106 the predicted value of the signal for each rake finger 76-82. Used for phase adjustment and amplitude weighting. From the 1-step prediction filter After passing through each multiplier 90 and 104, these output signals are summed by an adder circuit 112. A hard (provisional) judgment is made. 1-step prediction filter and leading samples The data supplied to the symmetrical filter has been corrected to some extent by the decision value.

For any given position in the receiving order, e.g. later, The pre-sample symmetric filter produces new, typically more accurate channel estimates. Ru. The new channel estimate similarly phase-adjusts the samples of the delayed received signal. , used for weighting. The sample delay of the received signal is determined by each signal shift level. It is caused by Gista 96.110. The output signals from multipliers 98 and 114 are: The addition circuit 100 adds the values to generate a new judgment value. But each delayed signal It should be noted that the sample has already been corrected by provisional judgment.

This means that the new decision value represents the difference between the tentative decision and the final decision.

If the output of the limiter device 122 is positive, the original judgment value is valid; It will be reversed. The output signal from limiter device 122 is synchronized with multiplier 88.102. and is supplied to the shift register 124. The output from the shift register is half linear. The output from the adder circuit 116 is multiplied by the multiplier 126 in A, and the differential decoding circuit 132 supplied to Then, the new decision value is further included in the preceding sample symmetric filter. It can be used to correct the contents of the shifted register. This means that 2 Feedback from the limiter device 118 to the Winner complete filter block This is accomplished by a path called “Inversion of Incorrect Samples (Invent Inco rrect Sample)”.

Next, examples of the one-step prediction filter and the preceding sample symmetric filter are shown in Fig. This will be explained with reference to 4.

FIG. 4 shows a two-stage Wiener set filter.

The Winner set filter etc. is input from each half-linear multiplier 88 and 102 in Fig. 3. It has a shift register 136 for receiving signals. Centralized sample and dump (i The integrate snd dump) circuit 142 also receives the input signal.

The final stage of the shift register 136 is connected to a half-linear multiplier 138, and Multiplier 138 receives the inverted signal of the illegal sample as shown in FIG. Her The output side of the Frinia multiplier 138 is connected to a shift register 140 and a second set sample. input of the file and dump (inleHa+ewadduIIIp) circuit 146 connected to the side. The final stage of the shift register 140 contains (aggregate samples and at the second input terminal of the inle and dump (inle[+*le and dump) circuit 146. It is connected. aggregate sample and dump uo+p) circuit 142 is connected to a second input connected to one stage of shift register 136; It has a force end. Aggregate samples and dumps (i+++e(rste and d The output side of the ump) circuit 142 is connected to the input side of the shift register 144, and the output side of the of the in+eg+ue and dump circuit 146. The output side is connected to the input side of shift register 148.

The block labeled 150 shows a one-step predictor and includes three multiplication circuits 152. ．． 154.156, and each multiplication circuit has a respective shift register 144. has an input connected to each stage and also receives the weighting coefficients as shown in the figure. It has a second input end. The output side of each multiplier circuit is connected to the input side of adder circuit 158. , and the adder circuit 158 also includes aggregate samples and dumps (in+cH-electronic e has an input side connected to the output side of the ind dump) circuit 142. addition times The output of path 158 is the output of the one-step predictor, which output corresponds to the connection of FIG. connected to a multiplier circuit.

The symmetric pre-sample filter has summing circuits 160.162.164.166 Ru. Second set sample and dump (in+eg+ue and dump) times The output side of the adder circuit 146 is connected to the input side of the adder circuit 160. The second input terminal is connected to the final stage of the shift register 144. Addition circuit 162 and 164 each have a set of input lines, one of which is a shift are connected to different stages of the register register 144, and their second input terminals are connected to different stages of the shift register 144. They are connected to different stages of the register 148, respectively. The adder circuit 166 has an input connected to the last stage of the shift register 148, and another input connected to the aggregate sample. Output of pull and dump (in+eHa+e and du+ap) circuit 142 connected to the side. Output side of adder circuit 162.164.166 Special table Hei 7-50 9113 (7) is the 0 multiplier circuit 1 connected to the input side of each multiplier circuit 168, 170, 172. 68.170.172 has another input side that receives the weighting coefficients as shown in the figure. have The output of the multiplier circuit is connected to the input side of another adder circuit 174, Circuit 174 also receives the output from summing circuit 160. Output side of adder circuit 174 is the output side of the symmetric pre-sample filter, which is connected to each multiplier in Figure 3. has been done.

The block labeled 150 has different coefficients depending on how fast the filter is required. This can be repeated, for example, three times.

Referring to FIG. 5, this figure shows a simplified implementation of the circuit shown in FIG. Similar circuit blocks are designated with the same reference numerals and their functions are described with reference to FIG. It can be seen that the function is the same as that described in .

From FIG. 5, each pre-sample symmetric filter 94.108 has a It can be seen that each of the 86 outputs has an additional input connected thereto. believe even more The number shift registers 96 and 110 also output signals from the half-linear multipliers 88 and 102. from the signal correlators 84, 86 instead of being connected to receive the signals respectively. Receive the output respectively. With the circuit connected as shown in the figure, the second half of the modulation in the path is removed by a signal provided by limiter device 118. , the additional input signal for each pre-sample symmetric filter is the input half of the second path. constitutes a signal.

In FIG. 5, the data shift register 124 shown in FIG. There is no need for the multiplier 126. The output side of the addition circuit 116 is a differential decoding circuit 132. The 1-bit delay circuit 1280 is connected directly to the input side of the 1-bit delay circuit 1280. The operation in Figure 5 is basically It can be seen that this is the same as described above with reference to FIG. Half of the first path of the input signal The minutes are generated from the output side of the half-linear multiplier 8 and 102. It should be noted that

Modifications to FIG. 3 as described with reference to FIG. It is necessary to modify the Winner set filter, etc. A set of two-tiered Kuina shown in Figure 6 Filters etc. basically operate in the same manner as described with reference to FIG. Components of similar circuits are designated with the same reference numerals as in FIG. I understand that. Referring to FIG. 6, the shift register 136 is half of the input signals of the first path are input to another shift register. 175, and the separate shift register 175 has a lumped sample and Connected to the input side of the inle (tile and duIIIP) circuit 142 has a final output stage. integrate sample and dump ! Another input side of the nd dump) circuit 142 directly receives the input signal of half of the first path. Receive and receive messages.

Another embodiment of the circuit configuration shown in FIGS. 5 and 6 is shown in FIGS. 7 and 8. similar Circuits and similar components operating in this manner are given the same reference numbers. I understand that. Comparing FIG. 6 with FIG. 8 for the input signal of the second path half , the modulation of the input signal in the shift register 136 and half of the second path is removed. It can be seen that there is no need for the half-linear multiplier 138 used to do this. figure 8, the input signal for half of the second path is transferred to the shift register 140 and the centralized signal. sample and dump (i+++cgri+e and dump) circuit 146 and is supplied directly to To achieve the simplicity of this circuit configuration, as shown in FIG. The block diagram shown below shows a one-bit delay circuit 97 and another multiplier for the common mode channel. 99 and another 1-bit delay circuit 111 for the direct phase channel and a half linear It has a multiplier 113. In each case, a 1-bit delay circuit 97.111 receives the outputs from shift registers 96 and 110, respectively, and delays them by 1 bit. The outputs from the extension circuits are sent to half-linear multipliers 99 and 113, and to the limiter circuit 1. It is multiplied by the signal supplied from 18. From half linear multiplier 99.113 The output of 94.108.

Referring to FIG. 9, processing polyphase differential phase shift keying (MDPSK) A block diagram of another embodiment of the invention suitable for use is shown.

A plurality of rake fingers are shown with reference numbers 180, 182, 183, 184, each The rake finger has a circuit structure shown similar to that described with reference to rake finger 180. It can be seen that it has a certain structure. Each rake finger has a signal correlator 186 and the phase The converter 186 receives at its input the in-phase signal I from the downconverter.

The output side of the signal correlator 186 is connected to the input side of the 1-bit delay circuit 188 and the signal shift It is connected to the input side of register 190 and the input side of multiplier 192. Signal The output side of the shift register 190 is connected to the input side of the multiplier 194, and a 1-bit delay is applied to the input side of the multiplier 194. The output side of the circuit 188 is connected to the first input terminal of the complex linear multiplier circuit 196. Ru.

The second signal correlator 198 receives at its input the quadrature signal from the down converter. The output side of the signal correlator 198 is connected to the input side of the 1-bit delay circuit 200 and the multiplier The input side of the signal shift register 204 is connected to the input side of the signal shift register 204 .

The output side of the signal shift register 204 is connected to the input side of the multiplier 206. .

The output side of the 1-bit delay circuit 200 is connected to the second input terminal of the complex linear multiplication circuit 196. It is connected. The complex linear multiplication circuit 196 includes a pre-sample symmetric filter 20 8 and the 1-step prediction filter 210. (8) It has a first output. The output side of the preceding sample symmetric filter 208 is connected to the multiplication circuit 1 94 is connected to another input side of 94. The output side of the 1-step prediction filter 210 is , is connected to another input side of the multiplier circuit 192. The complex linear multiplication circuit 196 The second output side is connected to the input side of another pre-sample symmetric filter 212 and to the one-step pre-sampling filter 212. It is connected to the input side of the measurement filter 214. Preliminary sample symmetric filter 21 The output side of 2 is connected to another input side of the multiplier circuit 206, and the 1-step prediction filter The output side of the multiplier 214 is connected to another input side of the multiplier circuit 202 . multiplication circuit The outputs of 194 and 206 are respectively supplied to the input sides of adder circuits 216 and 218. Ru.

These adder circuits receive outputs from other rake fingers 182.183.184. The output side of the 0 multiplier circuit 192, 202 is connected to another adder circuit 220. ．． 222, respectively, and the adder circuits 220 and 222 are connected to other rake filters. 182, 183, and 184, respectively. Addition circuit 21 The output side of 6°218 is connected to each input side of the differential decoding circuit 224, and the output side of the differential decoding circuit 224 is Signal circuit 224 produces data on output conductor 226 . Also, the addition circuit 216. The output side of 218 is the amplitude normalization and threshold to the nearest phase within the alphabet. The output side of said circuit is connected to each input side of circuit 228 , and the output side of said circuit is connected to each input side of circuit 228 . Connected to the input side. The output side of the adder circuits 220 and 222 is a normalized signal of another amplitude. and the input side of the threshold circuit 232 for the nearest phase within the alphabetic character. The output side of said circuit is connected to each input side of another complex conjugate circuit 234 and each It is connected to the input side of delay circuits 236 and 238. Output of complex conjugate circuit 234 The force side includes complex circuits within each rake finger, such as circuit 196 within rake finger 1. Connected to each input side of the near multiplier circuit. The output side of the delay circuits 236 and 238 is , is connected to each input side of another complex linear multiplication circuit 245, and the multiplication circuit 24 5 receives the output from complex conjugate circuit 230. The complex linear multiplication circuit 24 5 has two output lines, the lines being used for the signals generated from the complex conjugate circuit 234. 196-like complex linear multiplier in each rake finger. can do. When using this latter connection, the complex linear multiplier circuit 196 is , input labeled I COMP IN above the preceding sample symmetric filter 20th side and the input labeled Q COMPIN above the preceding sample symmetric filter 212. It has two output lines connected to the power side and the power side, respectively. Lead sample symmetric fill The output side labeled I COMP OUT on data 20 is the complex linear multiplier circuit 1. 96 and similarly connected to the input side of the preceding sample symmetric filter 212. The output side labeled POUT is connected to another input side of the complex linear multiplier circuit 196. be done.

Next, circuit operation will be explained with reference to FIGS. 9 and 10.

To process multiphase differential phase shift key ink (MDPSK) using Fig. 0MDPSK describes a new embodiment of the present invention configured to transmit information in one channel. Full complex demodulation capability is required as the Q and Q channels are modulated separately. Cha The first operation in the channel prediction path removes the effect on the data as described above and The goal is to remove the modulation from the signal. Since the modulation is complex, a complete complex demodulator The function must be performed in a complex linear multiplier circuit 196, as will be explained later. , this circuit receives input from the first pre-demodulator.

The output of the complex linear multiplier circuit 196 is a set of preceding sample symmetric filters as described above. filter 208.212 and one-step prediction filter 210.214. For the first and second outputs, phase compensation and amplitude weighting are performed as before. Injuries are administered. The previous output is passed through a multiplier 192.202 to an adder circuit 220.2. 22, the other rake fingers are added together. At this stage, the phase is compensated. and obtain a complex signal that is optimally summed through the rake component. Received message In order to remove modulation from the signal, it is necessary to perform judgment on these outputs. . The outputs of adder circuits 220 and 222 are supplied to circuit 232, which Normalize the amplitude of the signal and threshold to the closest phase within the alphabet. and For example, for 8-phase DPSK, the thresholding is 8 phases with a phase of π/4. This is done for almost the same phase. After said circuit 232 performs this function , the output is sent to a circuit 234, which calculates the complex conjugate of this output. and invert the relevant phase. This circuit 234 inverts the Q channel between passes. let This signal is sent to a complex linear multiplier 196 to remove the modulation. Ru. In the second cycle, the outputs from the multiplier circuits 194 and 206 are again sent to the adder circuit 21. 6.218 is added across these rake fingers to accomplish the original purpose of recovery. For the differential decoding, the output signal is provided to a differential decoding circuit 224, which performs differential decoding. Execute encryption. This behavior is based on the current complex sample and the preceding complex sample. It consists of a complex multiplication with the conjugate complex number, Z, the current complex sample, and the previous complex sample. If the sample is Z, -1, the output is Z, XZ*, . Demodulate the demodulation to the appropriate threshold. A form of error control encoding is provided. If so, this complex signal can be fed directly to the decoder.

Another feature of the invention, as described above, is that the second path in the pre-sample symmetric filter The ability to perform second path data correction for half the content of the Wiener filter. Although this operation is not essential to implementing the invention, it improves performance.

If necessary, the block shown within the outer broken line 242 is used. Addition circuit 21 6. The output of 218 is fed to a circuit 228, said circuit 228 being identical to that previously described. performs the function of Strengthen. Now this signal is modulated and we need to compensate for the signal with the modulation removed. The original (original) stribin of the modulation from the original signal can be It is necessary to remove the original 5tripPin.

Original striving (otiginsl 5ltippln customer) signal is circuit 232 and held by delay circuits 236 and 238. 2 outputs The difference between the side data is calculated by the complex linear multiplication circuit 245. central filter supplement The output of the complex multiplier circuit 245 labeled as the positive line is connected to I COMP OUT , I COMP IN, Q COMP OUT, Q COMP IN (7) each output The phase of the signal within the midpoint of the preceding sample symmetrical filter through the output side and the input side can be applied to compensate. For clarity, these operations are illustrated in Figure 1. 0 is shown separately, here is the output, namely I COMPOUT, 11. BiQ COM How can P OUT be processed with the output from the central filter correction line? It is supplied to the complex linear multiplier, and the I COMP IN line and Q COMP IN line The diagram shows how the signals are fed back to the filter via the respective channels.

Referring to FIG. 11, an alternative configuration of the block diagram shown in FIG. 9 is shown. Re Similar components are given the same reference numerals and similar to the description with reference to FIG. Operate. It turns out that its composition mainly concerns the boxed line marked 242. Karu. Complex linear multiplier circuit 245 no longer produces a signal on the center filter correction line. Although the output signal from the complex conjugate circuit 230 is not used to receive. The complex linear multiplier circuit receives signals from each 1-bit delay circuit 236 and 238. The input side of the circuits 236 and 238 receives the signal, and the input side of the circuits 236 and 238 is The output side of register 190 and the output of signal shift register 204 of the Q signal channel connected to each side. The complex linear multiplier circuit 230 is designated E, F. Generating two output signals, each input side of the pre-sample symmetrical filter 208.212 supplied to

It will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention. It is clear. For example, in FIG. 4, the multiplier 138 is removed from the diagram and the input side be ICOMP OUT, the output side be ICOMP IN, or other except that it is Q CoMP OUT and Q COMP IN for the filter. A configuration that combines a preceding sample symmetric filter and a 1-step predictive filter. can be made as shown in FIG.

Fig, 2 Fig, 4 Special Table Sen7-509113 (12) Continuation of front page (81) Designated countries EP (AT, BE, CH, DE.

DK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), FI, JP, US

Claims (16)

[Claims] 1. each configured to generate a data output signal and a feedback signal. a plurality of circuit means arranged in parallel with each other, and a processing means, the circuit means having a plurality of circuit means in direct contact with the in-phase input signal. In-phase and quadrature channels each configured to receive an alternating-phase input signal the processing means modifying the input signal; a fixed value for determining the cost of said feedback signal to be supplied to each circuit means for For use in equipment that provides a digital radio link between line units and mobile radio units. In devices where the output from each Wiener filter is processed by the processing means, The output from the pre-sample symmetric filter is used to generate the output data signal. device between a fixed wireless unit and a mobile wireless unit, characterized in that it is used for Equipment for forming digital wireless links. 2. Each channel further includes a signal correlator receiving an input signal, said signal correlator has an output connected to a first multiplication means, the output of said first multiplication means being connected to a winner. is connected to the symmetrical filter and the preceding sample symmetric filter, and the second multiplication means multiplying the output from the ner-type filter by the output from the signal phase blocker; The output side of the channel is connected to a first adder circuit, and the first adder circuit is connected to a second input for receiving an output from a second multiplier circuit, said first summing circuit , provides an output signal that is fed back as an input to the first multiplication means. An apparatus according to claim 1. 3. The output side of the preceding sample symmetric filter is connected to the input side of the third multiplication means. and the third multiplication means has a second input side connected to an output side of the signal shift register. and the signal shift register receives the output signal from the first multiplication means. The third multiplication means has an output connected to a second addition circuit. The second adder circuit may include a third multiplier connected to another channel on the second input side. and is configured to receive an output from the circuit and generate a data output signal of the circuit means. An apparatus according to claim 2. 4. The shift register is connected to a signal correlator instead of being connected to the output side of the multiplication means. , said pre-sample symmetric filter has an input connected to an output of another input. Claim 1 connected to receive the output signal from the signal phase switch on the power side. The device according to item 3. 5. The data output signal from each circuit means is supplied to a third adder circuit. The output side of the calculation circuit is connected to a limiter circuit, and the output side of the limiter circuit is connected to a symmetrical Claims 1 to 3 connected to the input side of the pre-sample filter The device according to any one of the items. 6. The processing means has a fourth addition circuit connected to the limiter circuit, and the processing means has a fourth addition circuit connected to the limiter circuit. The output side of the circuit is connected to each first multiplication means and to the input side of the data shift register. the data shift register has an output connected to a fourth multiplier; The fourth multiplier has another input connected to the output of the third adder; The output side of the fourth multiplication means is a differential decoder configured to generate a data output signal. 6. The device of claim 5, wherein the device is connected to a circuit. 7. The processing means has a fourth addition circuit connected to the limiter circuit, and the processing means has a fourth addition circuit connected to the limiter circuit. The output side of the circuit is connected only to the first multiplication means, and the output side of the third addition circuit is connected to the differential reconstruction means. 6. The device according to claim 5, which is connected to the input side of the signal circuit. 8. Wiener-style filters and pre-sample symmetric filters receive the input signal a first shift register configured to: an output stage connected to a first multiplication means, said first multiplication means inverting the sample; a second input for receiving a signal indicative of a second shift register; input side of the star and a second integrated sample and dump. ump) circuit having an output connected to an input of the second lumped sample and an integrate and dump circuit that integrates the second shift register; a first lumped sample and dump (i ntegrate and dump) circuit has a first input and receives an input signal. The second input side thereof is connected to another stage of the first shift register. the first integrated sample and dump (integrate and dump) p) the circuit has an output connected to an input of a third shift register, the circuit having an output connected to an input of a third shift register; The shift register has a plurality of stages connected to a one-step prediction filter, and the shift register has multiple stages connected to a one-step prediction filter. A second integrated sample and dump circuit includes: The output side connected to the input side of the fourth shift register and the input side of the first adder circuit. and the fourth shift register is connected to the input sides of the second, third, and fourth adder circuits. Each of the second, third and fourth adder circuits has a plurality of connected stages, On its other input side said stage of said third shift register and said first lumped sample and and the output side of the integrate and dump circuit, respectively. The second, third and fourth adder circuits are connected to a first input side of each second multiplier. and each second multiplier means has an output connected to a weighting factor at its second input. receiving the signal and said second integrated sample and dump; The adder circuit connected to the output side of the dumq) circuit receives the output from the second multiplier. having an output side connected directly to another summing circuit configured to receive the output; the further summing circuit is configured to generate a symmetric pre-sample filter output signal; Apparatus according to any one of claims 1 to 7. 9. A first multiplier receives at said second input a signal indicative of modulation removal; The shift register is configured to receive half of the input signal, and the shift register is configured to receive half of the input signal; The integrate and dump circuit is a fifth shift register connected at one input side to receive another half of said input signal; The first integrated sample and dump the fifth shift register has a final stage connected to the second input side of the circuit; Claims wherein the first stage is configured to receive the other half of the input signal. Apparatus according to clause 8. 10. The signal shift register is not connected to the first multiplication means, but to the output side of the signal correlator. and the output side of the shift register is connected to the input side of the delay device. is also connected, and the output side of said delay device is connected to another multiplication means, and the output side of said delay device is connected to said another multiplication means. The means receives the output from the third adder circuit via the limiter circuit on its second input side. The output from said further multiplication means is connected to receive the preceding sample symmetric frame. The filter according to claim 3 or 5 is connected to supply input to the filter. equipment. 11. the input signal without using the first shift register and the first multiplication means; said half of said second shift register and said second member sample and dump (integrate and dump) circuit. Claim 9 The device according to item 1 or item 10. 12. Each channel further includes a signal correlator for receiving the input signal, and the signal correlator for receiving the input signal. The multiplier has an output connected to the first complex linear multiplier, and the first complex linear multiplier has an output connected to the first complex linear multiplier. The multiplier circuit consists of a Wiener filter and a prior sample symmetry associated with each channel. a first power line respectively associated with each channel; The calculation means combines the output from the preceding sample symmetric filter and the output from the signal correlator. the first multiplier means configured to multiply an output connected to a first summing circuit; and the first summing circuit has a first circuit means associated with the plurality of circuit means. each first summing circuit is configured to receive the data output signal. and has an output side connected to an input side of a differential decoding circuit configured to supply each A second multiplication means associated with the channel combines the output from the Wiener filter and the signal phase. the second circuit means is connected to the input side of the second adder circuit; said second summing circuit has a second output connected to a plurality of circuit means; The second addition circuit is connected to the output side of the multiplication means, and the second addition circuit is connected to the first normalization means. the first normalizing means is connected to the first complex conjugate means; an output side of the first complex conjugate means, the output side of the first complex conjugate means 2. A device according to claim 1, wherein the device is connected to two inputs of the device. 13. A second normalization means is provided for receiving the signal supplied to the differential decoding circuit. the second normalizing means has an output connected to the second complex conjugate means; and the second complex conjugate means is connected to the input side of the second complex linear circuit. an output side of the second complex linear multiplier circuit, the output side of the second complex linear multiplier in place of the output from the means is connected to the first complex linear multiplier circuit and The output from the first complex linear multiplication means is a symmetrical filter of the preceding samples of each channel. each pre-sample symmetric filter is connected to a separate input side of the filter. Claim 1 having another output side connected to another input side of the elementary linear multiplier circuit. The device according to item 2. 14. A second normalization means is provided and adapted to receive the signal supplied to the differential decoding circuit. the second normalizing means has an output connected to the second complex conjugate means; and the second complex conjugate means is connected to the input side of the second complex linear multiplication means. the second complex linear multiplication means has an output side, and said second complex linear multiplication means has an input side for each channel on its other two input sides. The output signal from the signal shift register that reaches the channel is received via each delay device. , the output side of the second complex linear multiplication means is one of the preceding sample symmetric filters. 13. Apparatus according to claim 12, each connected to a. 15. Claims 1 to 14 wherein the modulation is differential phase shift keying. The device according to any one of the preceding items. 16. The modulation is differential binary phase shift keying. The device according to any one of items 1 to 14.