JPH0750764A - Deflection device of raster scanning cathode ray tube display - Google Patents

Abstract

PURPOSE: To hold the size of a picture to be displayed on a CRT display as constant, even when a display mode is changed. CONSTITUTION: A deflection device is provided with flyback circuits, which are the fly back circuits T2, T4, Ly, Df, Cf with switches T2, T4, including a linear bipolar transistor T4 in its first inductor Ly, by which the switches T2, T4 respond to a line driving signal LINE, to alternately open and close a current path through the first inductor Ly between a first voltage level B+ and a second voltage level 0V lower than the first voltage, to generate a raster scanning current signal and by which amplitude of the signal is decided as a function of frequency of the first voltage level B+ and the line drive signal LINE, feedback circuits D2, R3, D3, C2 to generate a feedback signal F as a function of the electric current from the bipolar transistor T4 and regulators 600 to 630, T3, L, D1, C1 to have a first voltage level Bf fluctuated to hold a raster scanning width as a function of the feedback signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster scanning type CRT (cathode ray tube) display deflecting device for maintaining a constant picture size regardless of variations in raster line scanning frequency.

[0002]

Many raster scan CRT display devices have been designed which can be connected to a wide range of computer systems, each capable of producing one or more different raster display formats. Each raster display format is characterized by a pair of different line and frame scan frequencies. A standard line (horizontal line) scanning circuit for driving a horizontal deflection coil of a CRT display device generates a line scanning current signal in the deflection coil in synchronization with a raster line synchronization signal generated by a host computer. A gradient signal generation circuit is included. The line scan signal is usually in the shape of a sawtooth wave. However, some S-correction is applied to the line scan signal to provide the lines with an angular velocity relative to the arc of the CRT screen to ensure that each electron beam follows each line of the raster at a constant velocity. The degree of this S correction is determined by the S correction capacitance connected in series with the deflection coil.

The amplitude of the line scan signal is inversely proportional to the frequency of the line sync signal. Therefore, the width of the picture displayed on the CRT screen is inversely proportional to the frequency of the line sync signal. In CRT displays capable of displaying different raster display formats, a tilt regulator is typically connected to a tilt signal generating circuit to change the amplitude of the line scan signal as a function of the reference input and feedback signals. This reduces the influence of the fluctuation of the line synchronization frequency on the width of the display picture. The feedback signal is generated as a function of the line scan signal by a feedback circuit connected to the ramp signal generation circuit and the regulator.

[0004]

Typically, the feedback circuit includes a sensing component that is inserted in the path of the line scan signal to generate the feedback signal as a function of the line scan signal. However, the presence of sensing components in the line scan signal path degrades the line scan signal by causing unwanted ringing and energy loss to the slope regulator.

[0005]

According to the present invention, a deflection device for a raster scan cathode ray tube display is realized. The deflection device includes a flyback circuit (T2) having switches (T2, T4) each including a bipolar transistor (T4) connected in series to a first inductor (Ly).
2, T4, Ly, Df, Cf), and the switches (T2, T4) are responsive to the line drive signal (LINE) to output the first voltage level (B +) and the first voltage level (B +).
The second voltage level (0V) lower than +)
A current path passing through the inductor (Ly) is alternately opened and closed to generate a raster scanning current signal flowing through the deflection coil of the raster scanning cathode ray tube display device, and the amplitude of the raster scanning current signal is the first voltage level. (B +) and the flyback circuit (T2, T4, Ly, Df, determined as a function of the frequency of the line drive signal (LINE).
Cf) and the base electrode of the bipolar transistor (T4),
4) A feedback circuit (D2, R3, D3, C2) which produces a feedback signal (F) as a function of the current flowing out of the bipolar transistor (T4) via the base electrode.
And the flyback circuit (T2, T4, Ly, Df,
Cf) and varies the first voltage level (B +) as a function of the feedback signal (F) so as to maintain a constant raster scan width regardless of the variation of the frequency of the line drive signal (LINE). Regulator (600-
630, T3, L, D1, C1).

In accordance with the present invention, the feedback signal is derived from the current flowing out of the base of the switch bipolar transistor so that the feedback signal is generated without introducing energy loss or bad ringing in the current path through the deflection coil. Therefore, the linearity of the line scanning signal is not adversely affected.

The above feedback circuit (D2, R3, D3, C2)
Has a sense resistor (R3) included in a current path between the base electrode of the bipolar transistor (T4) and the second voltage level (0V), and the feedback signal (F).
Is determined by the voltage signal developed across the sensing resistor (R3) as a function of the current flowing from the base electrode of the bipolar transistor (T4) through the sensing resistor (R3) to the second voltage level. The feedback circuit (D
2, R3, D3, C2) has a peak detector (D3, C2) connected to the sensing resistor (R3), and the feedback signal (F) appears across the sensing resistor (R3). The peak detector (D3, C2) in response to a voltage signal
Is determined by the voltage level generated by. Thus, the feedback circuit of the present invention can be implemented with relatively simple and inexpensive electronic components and circuits.

The switches (T2, T4) are emitter switch type and are the bipolar transistors (T4).
Field-effect transistor (T2) connected in series to
A gate electrode of the field effect transistor (T2) is connected to receive the line drive signal (LINE), and is between the first voltage level (B +) and the second voltage level (0V). The current path passing through the first inductor (Ly) is alternately opened and closed. In the preferred embodiment of the present invention, the bipolar transistor (T4).
Is an NPN transistor, the collector electrode of the bipolar transistor (T4) is connected to the first inductor (Ly),
The emitter electrode of 4) is the field effect transistor (T
2), and in response to turning off of the field effect transistor (T2), current flows from the first inductor (Ly) into the collector electrode of the bipolar transistor (T4) and the bipolar transistor (T4). It flows out from the base electrode of T4).

The above regulator (600-630, T
3, L, D1, C1) are the flyback circuits (T
2, T4, Ly, Df, Cf) has a boost circuit (T3, L, D1, C1) connected thereto, and the boost circuit (T3, L, D1, C1) includes a second switch (T
3) It has a second inductor (L) connected in series, and the second switch (T3) has the line drive signal (LIN).
E) in response to the pulse signal (PWM) synchronized with the second voltage level (0V) and the second voltage level (0V).
Alternating current paths through the second inductor (L) between a third voltage level (Vin) higher than V) to generate the first voltage level (B +), The level (B +) is determined as a function of the third voltage level (Vin) and the pulse width of the pulse signal (PWM), and the regulator (600-630, T3, L,
D1, C1) is the boost circuit (T3, L, D1,
C1) for changing the pulse width of the pulse signal (PWM) as a function of the amplitude of the line scan signal. This boost circuit provides an inexpensive solution to the problem of operating the deflection circuit over a wide frequency range without dead band.

In a particular preferred embodiment of the invention,
The first inductor includes a raster deflection coil. This simplifies the deflection device and thus reduces manufacturing costs.

The boost circuit (T3, L, D1, C
1) has an S straightening capacitor that performs S straightening on the scanning current signal. This alleviates the requirement for a conventional S straightening capacitor at the output of the ramp signal generator circuit, thus further simplifying the circuit.

The inductor (Ly) has a raster deflection coil.

In a preferred embodiment of the present invention, the regulator (600-630, T3, L, D1, C1) is connected to the feedback circuit (D2, R3, D3, C2) and the feedback signal (F). An error amplifier (600) for generating an error signal as a function of the difference between the reference level and the reference level, and the error amplifier (600) and the boost circuit (T).
3, L, D1, C1) and a pulse width modulator (R1, 610, 620) for modulating the width of the pulse signal (PWM) as a function of the error signal. The pulse width modulator (R1, 610, 620) is connected to the boost circuit (T3, L, D1, C1) for current sensing to generate a ramp signal as a function of the current through the second current path. (R1), the error amplifier (60
0) to generate an output signal when the tilt signal exceeds the error signal, and to the boost circuit (T3, L, D1, C1) and the comparator (610). Then, the pulse signal (PWM) is applied to the control electrode of the second transistor switch (T2).
A latch (620) for generating
0) is set in response to the leading edge of the line drive signal and reset in response to the output signal from the comparator (610). This significantly improves the transient response of the regulator.

The regulator is adapted to vary the pulse width of the pulse signal as a function of the left-right (East-West) pincushion distortion correction signal. The regulator also
It can be adapted to give width adjustments and presets.

According to the present invention, a CRT display device having the above-described deflection device is realized. With this deflector, the CRT display can be driven by different computer system units, each with different display formats.

Further in accordance with the invention, a processor for generating a raster sync signal and changing at least one frequency of the raster sync signal to produce various display modes and a display device responsive to the raster sync signal. A computer system is provided having a picture above and a cathode ray tube display as described above for keeping the size of the picture approximately constant in various display modes.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a CRT (cathode ray tube) display device includes a high voltage (EHT: Extra High Tension) generating circuit 30.
And a CRT 10 connected to the video amplifier circuit 60. Line and frame deflection coils 80 and 70 are disposed around the neck portion of CRT 10, respectively.
The deflection coils 80 and 70 are connected to the line scanning circuit 40 and the frame scanning circuit 50, respectively. The power supply circuit 20 is connected to the high voltage generation circuit 30, the video amplification circuit 60, the line scanning circuit 40, and the frame scanning circuit 50 via the power supply lines Vin and 0V, respectively.

To explain the operation, the high voltage generating circuit 30 is
An electric field is generated within the CRT 10 that accelerates the electrons onto the beam toward the screen of the CRT 10. Line and frame scanning circuits 40 and 50 generate line and frame deflection currents in deflection coils 70 and 80, respectively. The line and frame scan currents are in the form of gradient signals and produce a time-varying magnetic field for raster-scanning the electron beam across the screen of the CRT 10. Line and frame scan circuits 40 and 50 synchronize the line and frame scan signals to the input line and frame sync signals, Hsync and Vsync, generated by a host computer system (not shown).
The video amplifier circuit 60 produces an output display on the CRT 10 as a function of the input video signal produced by the host computer system.

Next, referring to FIG. 2, the line scanning circuit 40 includes a gradient signal generating circuit 210 connected to the horizontal deflection coil 70. The tilt regulator 230 is a CRT
It is connected to a ramp signal generating circuit to cause 10 to display various picture formats. The output of the gradient signal generating circuit is connected to the input of the gradient regulator 230 via the feedback circuit 220.

The operation will be described. The gradient signal generating circuit 21
0 produces a line scan current signal in the deflection coil 70. The line scan current signal is synchronized with the line sync signal from the host computer. Inclination regulator 23
0 produces an error signal for controlling the line scan current signal and thus the width of the picture displayed on the CRT 10. The width of the picture can be adjusted by adjusting the reference input value R. The feedback circuit 220 applies the feedback signal F generated from the amplitude of the line scanning current signal to the tilt regulator 230. The error signal E is determined by the slope regulator 230 as a function of the difference between the reference value R and the feedback signal F. The gradient signal generation circuit 210, the gradient regulator 230, and the feedback circuit 220 thus form a negative feedback control loop that operates to keep the width of the picture displayed on the CRT constant regardless of the fluctuation of the horizontal scanning frequency.

Referring to FIG. 3, in the preferred embodiment according to the present invention, the ramp signal generation circuit 210 comprises a field effect transistor (FET) T2, the gate of which is in line, synchronized to the input line sync signal. Connected to a line oscillator (not shown). The drain of the FET T2 is connected to one end of the line choke inductor Lc, and the source of the FET T2 is 0 from the power supply.
It is connected to the bolt supply line. Two diodes Df
And Dmod are connected in series across the channel of FET T2. A capacitor Cf is connected across the diode Df, and another capacitor Cfmod is connected across the diode Dmod. The line deflection coil Ly is connected in series with the S correction capacitor Cs at both ends of the diode Df. The inductor Lmod is
Both ends of the diode Dmod are connected in series with the capacitor Cmod. The collector-emitter junction of the bipolar transistor T1 is connected across the capacitor Cmod. The base of the transistor T1 is a parabolic signal formed from the frame scanning signal. FET
The terminal of the inductor Lc on the side opposite to the drain of T2 is connected to the cathode of the diode D1 at the connection point B +. The anode of the diode D1 is connected to the drain of the FET T3. The capacitor C1 is connected to the cathode of the diode D1 and 0.
Connected between V. The source of FET T3 is connected to 0V. The drain of the FET T3 is connected to the high voltage supply line Vin via the inductor L. The gate of FET T3 is connected to the pulse width modulated (PWM) square wave output from the slope regulator 230. A preferred example of the tilt regulator 230 will be described later with reference to FIG.

In operation, T2, Lc, Df and Cf form a flyback circuit which produces a gradient current signal in the deflection coil Ly. The operation of the flyback circuit is well known in the field of electronic circuit design and thus will not be described in detail, but in short, when the FET T2 is alternately turned on and off, electrical energy is generated. Are alternately stored in the inductor Lc and the capacitor Cf. The line scan current signal is produced by energy transfer. The peak-to-peak amplitude of the line scan signal, and thus the width of the picture displayed on the CRT screen, is
It is a function of the voltage of the inductor Lc, ie the connection point B. Dm
od, Cfmod, Lmod, Cmod, and T1 are used to correct the line scanning signal in the lateral direction of the pincushion distortion correction (EWPCC).
Modulate with the signal to form a diode modulation circuit that reduces lateral pincushion distortion of the raster. The EWPCC signal is
It has a parabolic shape resulting from the frame scan tilt signal.

The voltage at node B + is controlled by the boost circuit formed by T3, C1, D1 and L.
The pulse width of the PWM signal at the base of the FET T3 is the voltage Vi.
Along with n, the voltage at the connection point B + is determined. Therefore, B +
Is varied by changing the pulse width of the PWM signal at the gate of FET T3 to change the amplitude of the line scan signal or picture width at a particular line sync frequency, or more importantly, The width of the picture is kept constant even if the line sync frequency fluctuates over a wide frequency range.

By varying the voltage at node B as a function of the EWPCC signal, the ramp signal generating circuit of the present invention is simplified. The reason is Lmod, Cmod, T
1, Dmod and Cfmod are no longer needed and can therefore be removed. For example, referring to FIG. 4, in the preferred variation of the ramp signal generation circuit shown in FIG. 3, both adjusting the width of the picture and correcting the lateral pincushion distortion changes the voltage at node B. It is achieved by In particular, the tilt regulator 230
The parabolic EWP of the PWM signal of the gate of the FET T3
Modulate as a function of CC signal. This allows Cmo
Since d, T1, Dmod, and Cfmod are no longer needed, the ramp signal generation circuit of FIG. 3 can be simplified. Df can be integrated into T2.

In operation, choke Lc isolates the voltage at node B + from the high voltage flyback pulse (typically 1.2 Kv peak) at the drain of FET T2. However, the voltage across Cs is
It is the same as the + voltage. Thus, the line choke L
c can be replaced by a deflection coil Ly.
The capacitor C1 of the boost circuit also acts as an S straightening capacitor, which further simplifies the ramp signal generation circuit. For example, referring to FIG. 5, in the modification of the gradient signal generating circuit shown in FIG. 4, the deflection coil Ly is used.
Is connected between the connection point B + and the drain of the FET T2 and the S correction capacitor Cs is connected between the connection point B + and 0V.

As described with respect to FIG. 2, the slope regulator 230 adjusts the width of the picture as a function of the feedback signal F from the output of the slope signal generation circuit 210.
The feedback signal F is determined by the peak current in the deflection coil 80 and thus represents the width of each scanned raster line. Referring again to FIG. 3, when FET T3 is turned on, current begins to flow in inductor L, thus establishing the magnetic field. However, the current resulting from this current does not flow in the flyback circuit. In conventional circuits,
Only the feedback signal F is returned from the ramp signal generation circuit 210 to determine when the FET T3 is on. However, the feedback signal F is derived from the line scan signal during the preceding cycle. In other words, the feedback signal F corresponds to the preceding line scanning period. FETT3 is turned
It is turned off, and a current flows through the diode D1 to the flyback circuit due to the decaying electric field of the inductor L. And this cycle is repeated. Thus, the feedback signal F is delayed by one line period. Thus, in conventional circuits, regulator 230 takes more than one line period to recover from a step input. Thus, the error signal E is present for at least one line period. Thus, in the conventional circuit, since the transition response of the slope regulator 230 is poor, if the reference input R fluctuates, the line frequency fluctuates, or, in the worst case, both fluctuate at the same time, the recovery time depends on the slope signal generator circuit. Long enough to damage.

The above problem is solved in the preferred embodiment of the present invention using the ramp regulator 230 shown in FIG.

Referring now to FIG. 6, in the preferred embodiment of the present invention, the ramp regulator 230 has a set reset (SR) latch 620. SR latch 6
The output Q of 20 is connected to the gate of FET T3. A resistor R1 is connected between the source of T3 and 0V. The set input S of the SR latch 620 is connected to the line drive signal (line). The reset input of SR latch 620 is connected to the output of comparator 610. The negative input of comparator 610 is connected through feedback loop I to the source of FET T2, and comparator 6
The ten positive inputs are connected to the output of the differential amplifier 600. The positive input of differential amplifier 600 is connected to reference voltage level Vref. Additive connection point (sum circuit network)
630 is a reference input R and a horizontal pincushion distortion signal EW.
The reference voltage level Vref is determined as the sum of PCC.
The negative input of the comparator is fed through the feedback loop F (see FIG. 2) to the output of the ramp signal generation circuit (FETs of FIGS. 3, 4 and 5).
Drain of T2).

In operation, at initial turn on, the output Q of SR latch 620 is at a low level. Therefore, FET T3 is turned off. Latch 620 at the rising edge of the line drive signal (line)
When the input S of is high, the output Q is high. Therefore, FET T3 is turned on. Therefore, L and F
The current flowing through the channel of ETT3 increases linearly.
Thus, the voltage across resistor R1 and thus the voltage at the negative input of comparator 610 increases linearly. When the voltage on the negative input of comparator 610 reaches the voltage on the positive input of this comparator 610, the output of comparator 610 goes high. Therefore, the reset input of latch 620 goes high. Thus the output of this latch 620 goes low and FET T3 turns off. When the FET T3 is turned off, the resistance R
The voltage across 1 returns to 0V. The voltage at the positive input of the comparator 610 is determined by the differential amplifier 600 as a function of the difference between the reference voltage level at the positive input of the differential amplifier 600 and the feedback signal F at the negative input of the differential amplifier 600. It is determined. The feedback signal F from the gradient signal generating circuit 210 can be replaced with the current feedback I.

Referring again to FIG. 2, the width adjustment in the line scanning circuit is such that the temperature stable feedback signal F accurately represents the peak current flowing in the deflection coil 70 from one raster line to the next. Return circuit 22 to return
Depends on 0.

Referring to FIG. 7, the line scanning circuit of the present invention includes a bipolar transistor T4 which is of the emitter switch type and is connected to the switching transistor T2. The collector of the transistor T4 is connected to the deflection coil Ly. The emitter of the transistor T4 is connected to the drain of the transistor T2 via the primary winding of the current transformer Tr1. One end of the secondary winding of the current transformer Tr1 is connected to the emitter of the transistor T4, and the other end is connected to the base of the transistor T4. The base of the transistor T4 is connected to the constant voltage source Vb via the resistor R2. The cathode of Zener diode D2 is connected to the base of transistor T4. The anode of Zener diode D2 is connected to the 0 volt potential through a 1 ohm resistor R3. The peak detector formed by the diode D3 and the capacitor C2 is connected to the node S which is the connection point between the resistor R3 and the diode D2. The cathode of diode D3 is connected to the negative input of amplifier 600 to complete the negative feedback loop.

In operation, the transistor T4, the transistor T2, the diode Df and the capacitor Cf form a flyback circuit as described below. However, according to the present invention, the diode D2, the resistor R3, the diode D3 and the capacitor C2 are operatively associated with
To form.

When the transistor T2 is turned on, the current path from the constant voltage source Vb to the 0 volt potential through the resistor R2, the base-emitter junction of the transistor T4, the primary winding of the transformer Tr1 and the transistor T2. Was first established. The primary winding of the transformer Tr1 and so that the current flowing through the primary winding of the transformer Tr1 when the transistor T2 is turned on results in the secondary winding current of the transformer Tr1 flowing into the base of the transistor T4. The polarities of the secondary windings are arranged to boost the current flowing from the constant voltage source Vb and the resistor R2 into the base of the transistor T4. Then, the transistor T4 starts to turn on. Therefore, current begins to flow from node B + through the deflection coil Ly, the transistor T4, the primary winding of the transformer Tr1 and the transistor T2 to a 0 volt potential. The increased current flowing through the primary winding of transformer Tr1 as transistor T4 turns on increases the current flowing from the secondary winding of this transformer Tr1 into the base of transistor T4, which causes transistor T4 to turn further.・ Turn on. Thus, the transformer Tr1 provides positive feedback which, in response to the turn-on of the transistor T2, rapidly drives the transistor T4 into saturation. The transformer Tr1 also reduces the demand on the constant voltage source Vb during the turn-on of the transistor T2,
Then, the resistor R2 is set to a constant power consumption (lower power rating).

When the transistor T2 is turned off,
The current path through the deflection coil Ly, the transistor T4 and the primary winding of the transformer Tr1 is interrupted almost instantaneously.
Thus, from the secondary winding of the transformer Tr1 to the transistor T
The current to the base of 4 immediately goes to zero. However, the current in the collector of the transistor T4 is highly inductive due to the deflection coil Ly, and the transistor T4
To continue flowing in the opposite direction through the base of this.
Diode D2 clamps the base of transistor T4 above a few volts, thus preventing the voltage at the base of transistor T4 from rising too much as a function of collector current when transistor T4 is turned off. The collector current flowing through the base in the opposite direction flows to the ground potential through the diode D2 and the resistor R3. This current continues to flow until the charge stored in the parasitic capacitance of the base-collector junction of transistor T4 is zero. The time until this parasitic capacitance is depleted is known as the storage time of the transistor T4. The voltage drop across resistor R3 is directly proportional to the Zener current of diode D2. Diode D2
The Zener current of is directly proportional to the collector current of transistor T4 during the storage time. Also, the collector current of the transistor T4 during the storage time is the peak scanning current flowing in the deflection coil Ly. Therefore, the voltage dropped across the resistor R3 is directly proportional to the peak scanning current of the deflection coil Ly. In reality, the voltage signal across resistor R3 is a trapezoidal waveform at the line scan frequency. The peak of the trailing edge of this waveform is proportional to the peak current of the deflection coil Ly. The diode D3 and the capacitor C2 detect the peak of the trailing edge of this waveform and are proportional to the peak current of the deflection coil Ly.
A feedback signal F in the form of a C voltage level is provided to the negative input of amplifier 600. Thus, the present invention does not introduce significant energy loss into the current path through the deflection coil Ly and without compromising the linearity of the line scan signal.
Feedback signal F as a function of peak current in deflection coil Ly
Generate. Furthermore, according to the invention, this feedback signal F
Can be generated by relatively simple and inexpensive circuit components.

FIG. 8 shows a computer system including a CRT display device 400 having a line scanning circuit according to the present invention. The computer system includes a CRT display device 400 and an input device 42 such as a keyboard.
It has a processor 410 connected to 0. The processor may be, for example, a microcomputer such as the IBM Personal System / 2 Model 70 microcomputer or a mainframe computer. Personal System / 2 is a trademark of International Business Machines Corporation. In operation, the CRT display device 400 includes a red (R), green (G) and blue (B) video signal, a line sync signal (H sync signal) and a frame sync signal (V sync signal) generated by the processor 410. To generate a picture. The processor 410 may operate the CRT display device 400 in various display modes by changing the frequency of one or more sync signals.
To control. However, according to the present invention, the size of the picture displayed by the CRT display device 400 is
Can be maintained almost constant even if the display mode changes

[0036]

According to the present invention, a CRT display device 400 is provided.
The size of the picture displayed by can be kept almost constant even if the display mode changes.

[Brief description of drawings]

FIG. 1 is a block diagram of a CRT display device.

FIG. 2 is a block diagram of a line scanning circuit of a CRT display device.
It is a diagram.

FIG. 3 is a diagram showing a circuit diagram of a gradient signal generating circuit for a line scanning circuit.

FIG. 4 is a diagram showing a circuit diagram of a gradient signal generating circuit for a line scanning circuit.

FIG. 5 is a diagram showing a circuit diagram of a gradient signal generating circuit for a line scanning circuit.

FIG. 6 is a circuit diagram of a gradient regulator for a line scanning circuit.

FIG. 7 is a diagram showing a circuit diagram of a line scanning circuit of the present invention.

FIG. 8 is a side view of a computer system having a CRT display device of the present invention.

[Explanation of Codes] 10 ... CRT 20 ... Power Supply Circuit 30 ... High Voltage Generation Circuit 40 ... Line Scan Circuit 50 ... Frame Scan Circuit 60 ... Video Amplification Circuit 70, 80 ... Deflection coil 210 ... Inclination signal generation circuit 220 ... Feedback circuit 230 ... Inclination regulator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Frederick Samuel Jackson England 77.5 Cutie Glasgow, Newton Mean, 41 Hazelwood Avenue

Claims (12)

[Claims] 1. A flyback circuit having a switch including a bipolar transistor connected in series with an inductor, the switch being responsive to a line drive signal.
A raster scan current signal flowing through a deflection coil of a raster scan cathode ray tube display device by alternately opening and closing a current path through the inductor between a first voltage level and a second voltage level lower than the first voltage level. Connected to the flyback circuit and the base electrode of the bipolar transistor, the amplitude of the raster scan current signal being determined as a function of the first voltage level and the frequency of the line drive signal. A feedback circuit, which generates a feedback signal as a function of the current flowing out of the bipolar transistor through the base electrode of the bipolar transistor, and a constant current which is connected to the flyback circuit and which is constant regardless of the frequency variation of the line drive signal. A variable that varies the first voltage level as a function of the feedback signal to maintain the raster scan width. Deflection device for the raster scan type cathode ray tube display device and a Regulator. 2. The feedback circuit has a sense resistor included in a current path between the base electrode of the bipolar transistor and the second voltage level, the feedback signal from the base electrode of the bipolar transistor. 2. The deflection device of claim 1, wherein the deflection device is determined by a voltage signal developed across the sensing resistor as a function of current flowing through the sensing resistor to the second voltage level. 3. The feedback circuit includes a peak detector connected to the sense resistor, the feedback signal being generated by the peak detector in response to a voltage signal developed across the sense resistor. Deflection device according to claim 2, characterized in that it is determined by the voltage level that 4. The switch comprises a field effect transistor of the emitter switch type, which is connected in series to the bipolar transistor, the gate electrode of the field effect transistor being connected to receive the line drive signal. Deflection device according to claim 1, 2 or 3, characterized in that it alternately opens and closes a current path through the inductor between the first voltage level and the second voltage level. 5. The bipolar transistor is an NPN.
A transistor, the collector electrode of the bipolar transistor is connected to the inductor, the emitter electrode of the bipolar transistor is connected to the field effect transistor,
5. The deflection device of claim 4, wherein in response to turning off, current flows from the inductor into the collector electrode of the bipolar transistor and out of the base electrode of the bipolar transistor. 6. The regulator has a boost circuit connected to the flyback circuit, and the boost circuit has a second inductor connected in series with a second switch, the second switch having the second switch. Alternatingly opening and closing a current path through the second inductor between the second voltage level and a third voltage level higher than the second voltage level in response to a pulse signal synchronized with the line drive signal. , The first voltage level is generated, the first voltage level is determined as a function of the third voltage level and the pulse width of the pulse signal, and the regulator is connected to the boost circuit to perform the line scanning. Deflection device according to claim 1, 2, 3, 4, or 5, characterized in that the pulse width of the pulse signal is varied as a function of the signal amplitude. 7. The deflection device according to claim 6, wherein the boost circuit has an S correction capacitor. 8. The deflection device according to claim 1, wherein the inductor comprises a raster deflection coil. 9. The regulator is connected to the feedback circuit to generate an error signal as a function of the difference between the feedback signal and a reference level, and to the error amplifier and the boost circuit. 3. A pulse width modulator for modulating the width of the pulse signal as a function of the error signal.
Deflection circuit of 3, 4, 5, 6, 7 or 8. 10. The pulse width modulator is connected to the boost circuit to generate a slope signal as a function of current through the second current path, a current sensor, and the error amplifier is connected to the slope. A comparator for producing an output signal when the signal exceeds the error signal, and a latch connected to the boost circuit and the comparator for producing the pulse signal at the control electrode of the second transistor switch, 10. The deflection device of claim 9, wherein the latch is set in response to a leading edge of the line drive signal and reset in response to an output signal from the comparator. 11. Claims 1, 2, 3, 4, 5, 6, 7,
A cathode ray tube display device having 8, 9 or 10 deflection devices. 12. A processor for generating a raster sync signal and changing at least one frequency of the raster sync signal to produce various display modes and a picture on a display device in response to the raster sync signal. A cathode ray tube display according to claim 9 for causing and keeping the size of the picture substantially constant in different display modes.