JPH0750666A - Routing system - Google Patents

Abstract

PURPOSE:To attain the high speed routing of packet data by providing a load distributing means having a queue for storing a processed result in a routing processor in a communication equipment in which networks are mutually con nected. CONSTITUTION:Modules on an LAN connected with a communication control part 5a are connection-controlled, and routing for operating a packet processing is operated by a routing processor 3. This processor 3 is equipped with a load distributing means 4, and the means 4 is equipped with the queue for storing the processed result in a packet buffer 33 corresponding to the ports of the communication control part 5a or the like, and a data sequence number ID from the control part 5a is fetched. Then, each header is reconstituted from data coexistingly inputted from the plural ports, the ID is added to each packet, and the routing of the established routing information in the packet in the buffer 3 is operated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internetwork device for interconnecting networks, and more particularly to a routing method for performing high-speed routing of packet data.

[0002]

2. Description of the Related Art Conventionally, the configurations of routers and gateways are
It has two or more communication ports and a processor that performs routing protocol processing. The routing is performed as follows. The packet received from one of the communication ports is stored in the buffer, and the processor performs the routing process to know the destination (direction). Further, the packet is relayed by transmitting the packet from the corresponding port.

There are several techniques for routing between networks, such as IP (Internet Pro).
tocol) is well known. In this IP protocol, an IP address is used as an internetworking address. Then, it has a route information table describing the MAC address of the adjacent route corresponding to the destination IP address, and refers to this to perform routing.

For example, as a technique for performing high-speed routing, as disclosed in Japanese Unexamined Patent Publication No. 3-132131, message routing, a means for performing routing specifies a plurality of inputs for accepting a message packet, and each range of destination node identification. It has a plurality of outputs, a switch circuit for connecting an input to one of the plurality of outputs, and the like. When fetching a packet from a certain input, the header reading circuit reads the header part and the header F
Before receiving all packet data in the IFO, the destination node identification is determined based on the information in the header,
Select one of the outputs with the node identification range and connect the input to it. In this way, packets are routed at high speed.

[0005]

When the relay means has a plurality of ports in the network, the packet data arrives in the relay means in a temporally mixed manner while competing between the ports, but in the conventional method, the header is used. Although there is a means for extracting and storing the data in a buffer, no consideration has been given to the temporal mixing of data from a plurality of transmission sources. That is, when the packet data is fetched into the packet buffer and the header is fetched into the header buffer to obtain the routing information, it is not clear due to competition between ports which routing information of data is completed sooner. In order to carry out the routing as soon as the routing information is completed, it is necessary to manage the queue while associating the data in the packet buffer with the routing information.

[0006]

A routing means is provided with a path from a communication control section for interfacing with a network to a packet buffer, and a path for a means for load distribution of routing processing. It is assumed that data arrives via the department.

The communication control unit is provided with means for generating a channel signal indicating from which of a plurality of sources the data is received, and packet ID generating means for generating an ID for identification for all packets. . The ID generated by the packet ID generation means is added to the packet data stored in the packet buffer and is also passed to the speed-up means.

The load distribution means is provided with a header detection circuit, a buffer for only the header, a DMAC dedicated to the header FIFO corresponding to the port corresponding to the channel signal, and a data sequence number (ID) fetching means. , Receives the packet ID from the communication control unit. Further, a queue for leaving the result of analyzing the header is provided for each port, and a register for registering and comparing sequence numbers, a comparator, and their control means are provided.

[0009]

The packet ID generating means is provided in the routing means, and the packet data in the packet buffer is provided with this ID.
By adding a means for adding the ID to the load balancing means, the packet data in the packet buffer and the routing information in the load balancing means are associated with each other for each packet. As a result, it is possible to route the packet having the completed routing information among the packets in the packet buffer.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

First, the overall architecture of the router device will be described. The features of the router device according to the present embodiment are:
It is to adopt an architecture that has multiple modules that perform routing and that can easily improve performance by adding modules. Each module has a routing processor, and each routing processor is configured to have one or more communication ports. The block diagram shown in FIG. 1 is a block diagram of the entire router. In FIG. 1, 1 is, for example, 20
A router bus having a throughput of 0 MBytes / sec, and a management unit 2 having a function of managing the entire device and a function of collecting and distributing routing information is connected to the router bus. A routing processor 3 having a function of performing high-speed routing can be connected to the router bus 1 from 1 to 8 modules. The management unit 2 sets the routing information in the routing processor 3,
A router is realized by each routing processor 3 performing a routing operation based on this.

Further, each routing processor 3 has
Various communication control units 5a to 5d are connected. Here, for example, if there is a high-speed communication port, basically only one is connected, but medium and low-speed communication can be supported by the capability of one routing processor even if a plurality of them are connected.

The configuration of the routing processor 3 and the routing process will be described with reference to FIG. In FIG. 1, 5a to 5d are communication control units for controlling various types of communication, 3
Reference numeral 1 is a processor for performing a routing process, 33 is a memory having a packet buffer for storing packets and a routing table, and 32 is a control circuit for controlling the memory 33 and the processor 31 to interface with the communication control unit 5.

The flow of routing will be described. As a premise, the management unit 2 distributes the routing information table to all the routing processors 3 so that each routing processor 3 has the routing information in the memory 33. For example, the management unit 2 collects the routing information from other routers by R
It is performed by exchanging information by using a routing protocol such as IP or OSPF, or by a user statically setting in advance. The communication control unit 51 transfers and stores the packet received from the LAN 71 to the memory 33. The processor 31 looks at the header portion of the stored packet and performs the routing process. For example, when the destination is the line 72, the packet is transferred from the routing processor 3a to the routing processor 3b. Also, for example,
If the destination is the next device, it is transferred to the management unit 2. For example, the destination is the LAN 71, that is, its own routing processor 3a
Discard if below.

Next, based on the above flow, in the case of having a plurality of medium and low speed communication, the communication source 61 and the communication source 62
An example of sending data will be described. In FIG. 1, reference numeral 4 denotes a routing load distribution processing unit for distributing the load of routing processing.

First, a device 61 connected to the communication control unit 5
Makes a request for data transfer. At this time, the device 61 outputs a request signal 61r to indicate that there is a transfer request. The arbitration block 51 of the communication control unit 5 shown in FIG. 2 receives this request signal and outputs a permission signal 61g to indicate that the device 61 is in a state in which data transfer can be permitted. As a result, the device 61 that has received the permission transfers the data. However, since it is quite possible that the transfer unit amount at this time is less than the length of the packet data, at the stage when one transfer access is completed, the device that has transferred still has the rest of the packet data. I shall. When the device 61 passes the data to the communication control unit 5, the communication control unit 5 fetches the data in the latch 53, outputs the data to the control circuit 32 via the interface unit 52, and the control circuit 32 writes the data in the packet buffer 33. . On the other hand, the load distribution processing unit 4 knows the valid timing of the data by detecting the write enable signal, and reads the data from the data line 321 shared with the packet buffer 33. The data taken in from the data line 321 is commonly input to the delay buffers 421a to 421d that make time for header detection, and is also read to the header detection circuits 411a to 411d. These detect the header by monitoring the data and comparing it with the data set in advance by a method such as register setting, and the comparison result is stored in the register 41.
2a to 412d, only the ones corresponding to the channel signals 511 to 514 output from the communication control unit 5 among the plurality of detection circuits 411a to 411d actually operate, and 42a to 42d. An ON / OFF signal is output to buffer gates 43a to 43d that pass data. In the case of this example, the communication control unit 5a outputs the channel signal 511 to indicate that the data is from the device 61. As a result, the header detection circuit 41
Only 411a of 1a to 411d operates, and the header F
A part of the header of the data from the transfer source 61 is stored in the IFO 423a.

Here, it is assumed that the device 62 similarly issues a transfer request and outputs a request signal 62r. Device 61
When the transfer access is completed, the arbiter 5 outputs the permission signal 62g indicating the permission of the transfer to the device 62. This causes the device 62 to transfer the data. Here, the communication control unit 5 outputs the channel signal 512. As a result, 41b of the header detection circuit operates and the data is output to the header FIFO 44b. However, even at this time, it is fully possible that the transfer unit amount will be less than the actual data amount to be transferred, so at the stage when one transfer access is completed, the transferring device still has the rest of the packet data. It is assumed that Subsequently, when the transfer source 61 again issues a transfer request to perform the transfer, the control circuit 32 writes the data in a position in the packet buffer 33, which is connected to the data previously written at the write access of the transfer source 61. As the method, it is sufficient that the control circuit 32 has a plurality of address buffers like a normal multi-channel DMAC, and the last written address can be held each time writing is performed in each channel.

Similarly, when a transfer from the transfer source 61 or the transfer source 62 occurs similarly, the header FIFOs 44a and 44
A header is sequentially input to b.

The header FIFO has a pointer,
In FIG. 4, when the pointer of the header FIFO 423a indicates that the header parts are aligned according to the value, the header DMA
The C43a issues a transfer request to the DMA arbiter 45. The request and the permission here are made through the signal line 45a. Upon receiving the permission, the header DMAC 43a stores the header in the DRAM 46 provided for buffering the header,
And the contents of the comparison result registers 412a-412d are transferred. The comparison result here relates to a MAC header check, an LLC header check, a SNAP header check, an IP header check, and a status check, taking IP routing as an example. After this,
The processor 47 of the load distribution unit 4 writes the result sequence in the interface memory 48 in order from the oldest one at an arbitrary timing.

As described above, the load distribution means 4 has the header and the routing information. Here, the transfer source devices 61 and 62 continue the transfer of the packet body (the part after the header), and this is written in the packet buffer 33 as described above. Then, at the end of the packet, the communication control unit 5a detects the end delimiter included in the packet by the frame end detection unit 54 to find that it is the end, and the counter update signal 5
41 to 544 are output to update the value of the counter provided for each channel, and this value, that is, the sequence number and the timing signal 5511 indicating that this is being output.
~ 5541 is output. As a result, the sequence control unit 4
The sequence number is registered in the register SQN register 444 of No. 4 for the corresponding port, and the routing information is prepared in the queue of the interface memory 48.

The processor 31 fetches the packet ID from the area corresponding to any port of the buffer memory 33 by the scheduling of the built-in controlware, and requests S at a certain point in time when the instruction is executed.
The sequence number and the port number are written in the QN register 441. As a result, the sequence number control unit 4
The comparator 4 compares the requested sequence number with the registered sequence number, and leaves the result in the status register 442. The processor 31 places the number of cycles required for the above comparison in the status register 442.
, And if there is a match, the routing information is read from an arbitrary address of the preset port area (this address is managed as a pointer by the controlware of the processor 31). If they do not match, the packet is considered to be discarded, and the processor 31 performs the same operation to route the next packet.

Next, an interrupt type embodiment in which the amount of hardware is reduced will be described with reference to FIG. In this embodiment, the request SQN registration register 441 also serves as an interrupt register from the processor 31 to the load distribution means 4. That is, the processor 31 requests the request SQN registration register 4
When the data is written to 41, this causes an interrupt to the processor 47 of the distribution means 4, and the processor 47 uses this as an opportunity to output the data in the DRAM 46 corresponding to the requested sequence number to the interface memory 48.
Then, the status register 442 is written that it is ready. The processor 31 knows the preparation completion from the status register 442 and reads the interface memory. The status register 442 is cleared by writing to the request SQN register 441. In this embodiment, the amount of registers and the capacity of the interface memory are very small, and future expansion can be dealt with by changing the controlware.
However, it is necessary to consider that if the header fetching overlaps during the transfer of the result in the load distribution unit 4, the arbitration in the load distribution unit 4 becomes heavy and the throughput is affected.

Packet transfer from the routing processor to the destination routing processor is performed as follows.

As shown in FIG. 6, the processor 31 adds a transfer header including a transfer length, a destination interface number, a source interface number, a protocol, a media type, and a next hop to the packet, and sends the packet to the destination via the router bus 1. Forwarding to the routing processor.

[0025]

As described above, according to the present invention, even if a plurality of input ports are connected to a device for interconnecting networks, the packet headers from them are taken into the internal header FIFO without being mixed. In addition, the sequence number is used to know the discarding of packets and the completion of the routing processing result, and the routing is speeded up.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a high-speed router.

FIG. 2 is a diagram showing communication control means to which a plurality of input ports are connected.

FIG. 3 is a diagram showing a routing load distribution unit.

FIG. 4 is a diagram showing an operation example in a routing load distribution unit.

FIG. 5 is a diagram illustrating an operation example in a routing load distribution unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Router bus, 2 ... Management part, 3 ... Routing processor, 31 ... Microprocessor, 32 ... Control circuit, 321 ... Data line, 33 ... Packet data memory, 4 ... Routing acceleration device, 411a-411d ... Header detection Circuits, 421a to 421d ... Delay buffers, 422a to 422d ... Header output gates, 423a to 423d ... Header buffers, 43a to 43d ... Header DMACs, 45 ... Header DMA arbiters, 45a ... Header DMAC arbitration signals, 46 ... DRAM, 47 ... Local processor, 48 ... Interface dual port memory, 49 ... ID latch, 5a-5b ... Communication control unit, 51 ... LAN arbiter, 511-514 ... Channel signal, 52 ... Interface circuit, 53 ... Switch circuit, 54 ... Frame end detection unit, 541-544 ... Counter update signal, 551-554 ... Packet ID generation counter, 5511-5541 ... ID on signal, 6 ... Medium low speed LAN, 61-64 ... Medium low speed LAN Upper module, 61r to 64r ... Request signal, 61g to 64g ... Grant signal.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Ken Ken Watanabe, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd. Inside the Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inoue Sawada 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Address Stock Company, Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Hiroshi Sato 810 Shimoimaizumi, Ebina City, Kanagawa Prefecture Office Systems Department, Hitachi, Ltd. (72) Masahito Sasaki 1 Horiyamashita, Hadano City, Kanagawa Prefecture Hitachi Computer Electronics Co., Ltd.

Claims (2)

[Claims] 1. A communication device for interconnecting networks, wherein the communication device has a load distribution means for routing processing, and the means has a queue for storing a processing result corresponding to a port of the communication apparatus. A routing method characterized by having. 2. The routing system according to claim 1, wherein the load distribution unit has a unit for generating and registering a sequence number indicating old and new data, and the unit and the queue are used together.