JPH0750437B2 - Data processing device - Google Patents

Description

The present invention relates to a data processing device controlled by a microprogram stored in a control memory.

[Conventional technology]

FIG. 5 is a block diagram of the main part of a conventional example of this type of data processing apparatus, FIG. 6 is a block diagram of the branch determination logic 4 in FIG. 5, FIG. 7 is a flow chart of a microprogram, and FIG. 7 is a timing chart of the conventional example.

The control memory 1 stores a micro program,
It is accessed in the part except the least significant bit of the register 2 which holds the microprogram address. Further, the control memory 1 is divided into two, that is, a microprogram having an even number of addresses and a microprogram having an odd number of addresses, which is selected by the selection signal 101 output from the branch determination logic 4. The output is held in the register 3. The output of each field of the register 3 directly controls individual circuits (not shown) at the same time,
It will execute a micro program. Register 3
One of the fields of 1 to 3 further pulls the decoder 5, the output of which is held in register 6, the output of each field of register 6 simultaneously controlling other individual circuits (not shown). The register 7 holding the branch condition is controlled by one of the fields of the register 6. The next address in the microprogram accessed by the address held in the register 2 is set at the next timing, whereby the microprogram is sequentially executed.

The branch determination logic 4 is, as shown in FIG. 5, an AND gate that takes the logical product of the branch determination commands C _{0 to} C ₃ held in the register 3 and the outputs S _{0 to} S ₃ of the register 7.
21 to 24, an OR gate 26 that ORs the outputs of the AND gates 21 to 24, an AND gate 25 that receives the least significant bit of the register 2 as an input, and an OR of the outputs of the AND gate 25 and the OR gate 26 It is composed of OR gate 27,
OR gates 26 and 27 modify the least significant bit of register 2. As a result, the least significant bit of the microprogram address (register 2 (address CSA)) = "0"
If set to, CSA and CSA + 1 depending on the values of C _{0 to} C ₃ and S _{0 to} S _3.
You can branch to. When not branch C ₀ -C ₃ will not be modifying and CSA least significant bits are all "0".

Next, the operation of the conventional example will be described with reference to FIGS.

When the command to update the register 7 is issued at the timing T ₁ , the register 7 is actually determined at the timing of T ₄ . In order to branch under the condition of the register 7 determined at T ₄ , the branch determination command is issued at timing T ₃ .
That is because the _value of C _{0 to} C ₃ on the register 3 at the timing of T ₄ and the value of S _{0 to} S ₃ on the register 7 determines whether the register 3 at the timing of T ₅ becomes D or D + 1. is there.

In this conditional branching method, the branch judgment command is waited until the branching condition is fixed, so NOP is executed at the timing of T _2.
It is necessary to issue (No Opration: Command that does nothing), which slows down the branch process and increases the number of useless microprogram steps.

[Problems to be Solved by the Invention]

In the conventional conditional branching method described above, a branching determination command is issued at the timing when the branching condition is determined, and the branching is performed.
In the case of updating the branch condition and branching with the result, there is a drawback that the branch judgment must be waited until the branch condition is fixed and the branch processing becomes slow, and the number of unnecessary steps for waiting increases. There is.

[Means for Solving the Problem] When a microprogram sequence branches under a certain condition, the data processing device of the present invention issues a branch determination command at the timing next to the issuance of a command that determines the branch condition, and makes a prediction. A branching direction, a means for holding the branch judgment command at a timing when the branch condition is fixed, and an output from a means for holding the branch judgment command at a timing when the branch condition is fixed A means for determining whether the branch direction is correct, a register holding a branch microprogram address for executing the branch again, and if the predicted branch direction is incorrect, the processing of the predicted direction is invalidated, and the register And means for starting processing from the correct branching direction.

[Action]

Since a branch judgment command is issued and branching is executed before the branch condition is fixed, in the case where the branch condition is updated and branching is performed as a result, there is no need to wait for the branch judgment until the branch condition is fixed, and the branch can be executed one timing earlier. It is possible to reduce unnecessary steps for meeting.

The register is provided to branch to a correct branch destination at the next timing when branch prediction is performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of a data processing apparatus of the present invention, and FIG. 2 is a branch judgment logic 4, 10 of FIG.
FIG. 3 is a flow chart of the microprogram in the present embodiment, and FIG. 4 is a timing chart when the microprogram of FIG. 3 is executed.

This embodiment has a configuration in which registers 8 and 9, a branch determination logic 10 and a selector 11 are added to the conventional example shown in FIG.

The register 9 is a register that receives a branch determination command, and holds the branch determination command at the timing when the register 7 is determined. As shown in FIG. 2, the branch decision logics 4 and 10 have an AND gate 28 and an input signal V added to the conventional circuit of FIG. 6, and when the value of the input signal V is "1", The branch determination logic is the same as that of FIG. 4 and the least significant bit of the selector 2 is not modified when the value of the input signal V is "0".

Further, in FIG. 1, the register 8 is a register that holds the value of the register 2 one timing before, and the selector 11 uses the output 102 from the branch determination logic 10 in the register 2
Either the register 8 or the register 8 is selected.

Next, the operation of this embodiment will be described with reference to FIGS. 3 and 4.

(1) When branch prediction is successful (FIG. 4 (a)).

When register 7 update command is issued at timing T ₁ ,
Register 7 is determined at timing T ₄ . When the branch determination command is issued at timing T ₂ , it is set in the register 3 at timing T ₃ . Originally, the command, the value of the register 7 not yet determined, and the branch determination logic 4 determine which of step C and step C + 1 shown in FIG. 3 is set in the register 3 at the timing of T ₄ ( That is, the branch is executed), but since the branch determination command is executed at the timing of T ₅ after the register 9 once received, step C is unconditionally set in the register 3 at the timing of T _4. . This means that the branch was predicted on the side of step C. The branch commands in the register 9 with the timing of T ₄ is the branch condition is determined in the register 7, the branch decision logic at the timing of T ₅
10 shows whether the branch prediction succeeded or failed. The output of branch judgment logic 10 will be "0" if it branch prediction succeeds, T ₅ by inputting the output "0" of the branch decision logic 10 as the input signal V in branch judgment logic 4
The branch executed at the timing of is suppressed, and the step X subsequent to the step C is set in the register 3 at the timing of T ₅ . As a result, branching can be executed one timing earlier than in the conventional case.

(2) When branch prediction fails (Fig. 4 (b)) As described above, it is possible to know whether the branch prediction succeeded or failed at the timing of T ₅ , but if the output of the branch determination logic 10 is "1". The branch prediction has failed. The reason why the output of the branch decision logic 10 is "1" is to modify the least significant bit of the register 2 to "1".
This is because the process branches to step C + 1 shown in FIG. Branch judgment logic when branch prediction fails
Disable immediately control signals of each field of the register 3 at the output 103 of the 10, to suppress the execution of Step C branch prediction fails to disable the control signals of each field of the register 6 at the next timing T _6. At the same time as the invalidation of step C, at the timing of T ₅ , the value of the register 7 confirmed as the branch determination command is correctly re-branched by the branch determination logic 4, but at the timing of T ₄ , the register 2 is set to the step X. Is held and the branch destination address becomes X + 1. The register 8 is provided to avoid this. The register 8 holds the value of the register 2 one timing before (C at the timing of T ₄ ), and the signal line 10 is used when the branch is performed correctly at the timing of T _5.
By selecting the register 8 with 2 and the selector 11, it is possible to correctly branch to step C + 1.

As described above, if the branch processing is successfully predicted, it can be executed at a high speed by one timing, and unnecessary microprogram steps are not required.

In general, it is often easy to predict a branch destination as a microprogram. For example, when a microprogram forms a loop, there are cases where a branch that exits the loop is less frequent than a branch that continues the loop. In this case, if the branch destination address that continues the loop is set to an even number and the branch destination address that exits from the loop is set to an odd number, branch prediction will succeed with a high probability.

In the present embodiment, the case where the bifurcation is in two directions has been described.
Similarly, in the case of multi-directional branching, the speed can be increased.

〔The invention's effect〕

As described above, according to the present invention, by issuing the branch determination command before the branch condition is fixed, the branch processing of the microprogram can be executed at high speed, and the wasteful steps of the microprogram can be deleted. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a data processing apparatus of the present invention, and FIG. 2 is a branch judgment logic 4, 10 of FIG.
FIG. 3 is a flow chart of the microprogram in the present embodiment, and FIG. 4 is a timing chart when the microprogram of FIG. 3 is executed.
FIG. 5 is a block diagram of a main part of a conventional example of a data processing device,
FIG. 6 is a block diagram of the branch decision logic 4 in FIG.
FIG. 7 is a flow chart of the microprogram, and FIG. 8 is a timing chart of this conventional example. 1 ... Control memory, 2,3,6,7,8,9 ... Register, 4,10 ... Branch judgment logic, 5 ... Decoder, 11 ... Selector, 101 ... 103 ... Signal line, 21 ... 25,28 …… And gate, 26,27 …… OR gate.

Claims (1)

[Claims] 1. In a data processing device controlled by a micro program stored in a control memory, when a micro program sequence branches under a certain condition, a branch judgment command is issued at the timing next to the issuance of a command for fixing the branch condition. From the means for holding the branch determination command at the timing when the branch condition is fixed, and the means for holding the branch determination command at the timing when the branch condition is fixed, Depending on the output, a means to determine whether the predicted branch direction is correct, a register holding the branch microprogram address to execute the branch again, and if the predicted branch direction is not correct, the processing of the predicted direction is performed. Means for invalidating and starting processing from the correct branch direction using the register The data processing apparatus characterized by having.