JPH07502635A - Small logic cell for field programmable gate array chip - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] field programmable gate Small logic cell for array chip l Anal standing and five upper level 1 The present invention provides a programmable or writable circuit formed within an integrated circuit semiconductor chip. Logic devices, more particularly fields. Regarding logic cells that form part of the programmable gate array chip. It is.

1 bean skin Programmable devices currently exist in several different architectures. It is possible to obtain it. The very first programmable device was a programmable robot. logic array (PLA) device, it can program multiple OR gates. It has a plurality of AND gates connected by.

These devices are capable of generating arbitrary combinatorial logic functions. Because For example, any combinatorial logic function can be written as a sum of products, and the product is A is generated in the ND array and the sum is generated in the OR array. this These two levels of logic (i.e., AND level and OR level) can be easily It is easy to predict the time delay for a write to occur and produce an output. It's simple.

However, the silicon area required to compute complex logic functions is undesirably large. It may become something.

More recently, it has been called a field programmable gate array, or FPGA. A programmable logic device was developed. These devices emit complex logical functions. multiple devices that can be interconnected by programmable interconnect lines to It has an array of several programmable logic cells.

In FPGA devices, functions must be computed as the sum of products of two levels. It's not important. This is because the output of any one logic cell is can be fed to the input of a logic cell, forming a chain, This is because it is possible to generate functions with multiple levels of logic. Therefore , it is possible to implement complex logic within a smaller physical area. It is Noh.

The architecture of some of these field programmable logic devices is Available today.

Various devices differ in the complexity of a single logic cell. One manufacturer uses e.g. For example, as shown in Figure 1, which has an extremely small size (fine-grained architecture), The company provides devices with logic cells.

Other manufacturers are much larger and have more power within a single logic block. A robot like the one shown in Figure 2 that handles large functions (coarse-grain architecture) A device with a gic cell is provided.

A small logic cell like the one shown in Figure 1 is completely controlled by the user's logic. It has the advantage of being able to fill the cell with unused space. Logic resources will not remain as they are. Multiple small logic cells It is possible to generate either combinatorial or ordinal functions from . However A fine-grain architecture consisting of small logic cells. In some cases, a large number of logic cells are required to generate complex logic functions. be done. Functions that require the use of more than one logic cell must be programmable interconnects must be used to enable . Capacitive and The time delays associated with resistive and resistive interconnect lines significantly slow down the response of the Ru.

Logic devices that consist of larger cells (coarse grain) have a single logic block. It is possible to quickly generate complex functions within a block. However, Users can identify a set of functions that do not completely use large logic cells. In this case, some of the logic cells remain unused. Also, quite large Some of the logic cells are used to generate combinatorial functions and to generate ordinal functions. have separate resources. The cell in FIG. 2 is such a cell. the user Place a circuit that uses many combinatorial functions but only a few ordinal functions. If desired, resources for multiple ordinal functions remain unused. Similarly, you If a user has a circuit that uses many ordinal functions but only a few combinatorial functions, If desired, many combination functions remain unused.

Another silicon-intensive thing faced by designers is that the signal is inverted. If necessary, and a configuration lab is required to form the inverter. When using cells that are capable of configuring cells, This consumes resources that could be used for more powerful functions. Dedicated for inverting functions Efforts have been made in the past to provide hardware for Published in May 1991 rpASIC(TM) l family via link technology ultra-high speed CMO3FBGA The structure described by QuickLogic in the publication entitled J. Here we use a two-person AND gate with one inverting input and one non-inverting input. A programmable construct is shown. Therefore, this construct inverts the signal giving the choice of applying to the input or non-inverting input. This solution is It is possible to apply a signal to both force and non-inverting inputs, but it is not possible to simply This solution is not needed when used to provide option reversal. double the number of input lines. Therefore, to get an optional inverter Using the structures described above requires significant silicon area and Increase complexity.

I got up next time The object of the present invention is to provide flexible, high-density, and high-speed logic cells; That is, it can implement many useful functions and convert the user's logic into a small silicon It can be realized within a certain area and also generates an output signal at high speed in response to an input signal. The objective is to provide logic cells that generate

There are two families of digital logic functions with different logic properties. example For example, functions such as AND, NAND, OR, and NOR all have selective inputs and outputs. It can be generated from an AND gate by inverting . example Functions such as sum of products, product of sums, XOR, and XNOR selectively invert inputs and outputs. It can be generated from a sum of products function generator by It cannot be made equivalent to the function generated from the ND gate. The novelty of the invention A regular cell is one in which two cells cannot be made equivalent by reversing their inputs or outputs. It offers options between types of functions.

The novel cell of the present invention is enabled or ready to perform an ordinal function. It is also possible to disable, i.e. It has an internal feedback loop that can be disabled. child The internal aspect of the feedback loop is that for feedback The resource consumption and delays associated with using general purpose interconnects are avoided. The fee Optional aspect of the back loop allows the use of higher chip densities It is said that This is because the resources dedicated to combinatorial and ordinal functions are This is because there is no wastage of area due to having a ratio. This cell further includes 1 An optional feedforward from the output of a cell to the input of an adjacent cell It has a cord connection. The speed of generating a wide range of functions and certain ordinal functions is This feed forward or cascade connection is improved. This cell is In addition, it has optional inverters on all inputs for easy reversal. Eliminating the need to consume more powerful programmable chip resources for inversion functions It is being removed. In one embodiment of the present invention, pump-type manual buffer control and pump-type Provides 3-state output control.

Possible functions that can be generated by a single cell of the present invention include Plexer, exclusive OR and exclusive NOR gate, two input sum of two forces, clear latches, set/reset latches, and 2 to 4 manual AND functions, etc. Ru. Inverting any combination of inputs to any of these functions is possible. Combine adjacent cells using the cascading feature described below. It is possible to generate larger functions by

The large function is a generic phase used to form the large function in the case of conventional cells. It is also possible to use interconnect structures. For example, JK flip-flops are Can be formed using three adjacent cells and one general purpose interconnect line. be.

Obscene. Fu　−゛ba・・ To form a latch, enable the internal feedback loop. the second combination section as an input to the feedback section. The output signal is supplied from the an input signal is supplied to the cascade section, and A clock signal selects between these two sections. Therefore, the clock If the signal selects the feedback section, the input signal latched within the section. This optional internal feedback loop If any programmable interconnect means or any input or output buffers It is possible to form an ordinal function without placing it in a path, resulting in a high The order function of the small configuration is obtained at speed. Feedback option is used If not, this cell can be used as a decoder, multiplexer or other combinatorial function. What interconnection means or what input or output cover software in the signal path can occur? multiple adjacent cells to perform a function without inserting any It is possible to combine The output of one cell can be programmed to input/output buffer means. this thing without adding significant delay beyond that of using a single cell. Allows the designer to generate a wide range of functions. One source and one destination This improvement is effective when realizing a logic gate with why If so, the gate is implemented in adjacent cells connected via a cascade path. This also avoids input/output buffering methods. . Therefore, gate delay can be minimized. Therefore, this cascade The features provide significant speed and density improvements.

The Obscene Room This cell is a buffer that passes signals to and from interconnect lines. have. The input buffer for each input to the logic cell of the present invention is optional. It is an inverted type depending on the version. This selective inversion can be used for other functions Allows designers to use inverters without consuming possible resources and eliminates the need for an output inverter. Any to this cell Since it is possible to invert the number input, this cell is also fast and can handle arbitrary addresses. 0 and 1 in the address ( when necessary to decode an address regardless of its placement and ratio (inverted and non-inverted) It is possible to depend between Also, fan out from the output port and some The present invention facilitates the generation of signals that are inverted at one destination and not at another. It is possible to handle The reason is that inverters must be installed on all inputs. This is because it allows complete flexibility. Combination of cascade and inversion features Most connections can be made without the use of programmable interconnects in the signal path. It is possible to generate a wide range of pool functions.

Roji・Fumi +4 This cell has an optional feedback option to select between 0 and 7 mm. Receives human input signals, including clock signals and cascade signals, and uses NOR functions or can be programmed or written to implement any of the NAND functions. a first stage NAND gate that provides an output that is received by a second stage circuit; ing. When configured to implement a NAND function, this second stage is similar to the first stage. Combine to realize functions in the sum of products (SOP) category.

If configured to implement a NOR function, the combination is in the AND category. This function realizes functions that can be used.

Impence, Lubafu The output buffer stage controls the connection of the cell output signal to one or more interconnect lines. It has high impedance capability for High impedance output electrically isolating the cell from the interconnect structure, e.g. (during the antifuse programming or write period) and when the cell output is connected to the bus. This is useful for both logic control of cell outputs when connected (the bus (receives multiple output signals from the cell, but only one at a time).

Both electrical and logical isolation is provided by the output buffer stage.

Pro lamin cell... Shitsu Array Tessuru Uni... The novel cell of the invention is preferably one of many cells in an array. be. The plurality of cells of the array are preferably field programmable integrated circuits. with programmable antifuse interconnect structures to form circuit devices. are interconnected. In such devices, this cell is configuration control unit (CCU), and its configuration The control unit not only stores the data for establishing the function of the cell, but also Controls programming of Chihyuse interconnect constructs and capture of array status (Array status is used to test the array or debug the design.) ). The CCUs are connected to each other in the form of a shift register. Continued. Additionally, each CCU supports the application of voltage to one horizontal or vertical interconnect line. Control. Intersections of horizontal and vertical interconnect lines shall be provided with antifuses. Ru. One CCU to control the voltage to the horizontal lines and one to control the voltage to the vertical lines By loading logic l into two CCUs consisting of CCUs, these two It is possible to address the antifuse at the intersection of two interconnect lines. Ru.

Therefore, in order to program or write the antifuse, the It is possible to supply a voltage difference to the two terminals of the chihyuse. This Ann The programming information is shifted through the CCU's shift register. be done. After programming all or one set of antifuses, Shift the configuration information into the CCU and configure the cell. Establish the application, form or composition. These same CCUs can be used to It is possible to sample the logical state of each of the connecting lines, and each CCU Sample one signal present on the connecting interconnect line. The collected data is , the same system that initially shifted the configuration information into the CCU. It is possible to shift output via a shift register.

Pro ゛Lamine　′ The invention particularly provides that the interconnect structures are interconnected by antifuses and The shape is configured by the memory cell that controls the pass transistor. Useful for configured arrays. However, the present invention also applies to other programs. It can also be applied to ramming technology and can also be applied to other interconnect technologies. maintain much of the efficiency of transistors, continuous diodes, floaties, etc. gate (EEPR, OM) transistors and mask-programmed vias There are connectors etc.

゛'s day FIG. 1 shows a conventional logic cell with small cell dimensions.

Figure 2 shows a large cell such as that used in Xilinx 3000 series parts. 1 shows a conventional logic cell with standard dimensions.

FIG. 3 shows a logic cell according to the invention.

Figure 4 shows a very small field programmable collection consisting of the cells in Figure 3. An integrated circuit device is shown.

Figures 5A and 5B illustrate its implementation using a two-person multiplexer and the cell of Figure 3. A current example is shown.

6A and 6B are examples of its implementation using an exclusive OR gate and the cell of FIG. 3. It shows.

7A and 7B show an exclusive NOR gate and its implementation using the cell of FIG. 3. An example is shown.

8A and 8B show an example of the sum of products circuit and its implementation using the cell of FIG. ing.

Figures 9A and 9B show a latch with clear and its effect when using the cell of Figure 3. An example of implementation is shown.

FIG. 90 shows an equivalent circuit formed by the circuit of FIG. 9B.

Figures 9D and 9E show clears with opposite tarok polarity than those in Figures 9A-9C. A latch is shown.

FIG. 9F shows an equivalent circuit formed by the circuit of FIG. 9E.

Figure 10A and IOB show the results when using the set/reset latch and the cell of Figure 3. An example of its implementation is shown.

11A and IIB show a four-person AND gate with one inverting input and a An example of its implementation using cells is shown.

Figures 12A and 12B show an 8-person AND gate with several inverting inputs and a An example of its implementation using two cells in Figure 3 interconnected using the cade feature. It shows.

Figures 13A-13C are interconnected using D flip-flops and cascade features. When using two cells in Figure 3 and using the cell feedback feature An example of its implementation is shown.

14A-14C show a JK flip-flop and its master Using cascade features and feedback features to form the slave part and a general-purpose interconnect to form one function of the flip-flop and another function of the flip-flop. This is the case when using the three cells in Figure 3 using a third cell connected through the body. An example of implementation is shown.

FIGS. 15A and 15B show configurations that configure the cell, that is, its form. A first embodiment of the cell of FIG. 3 with a regulation control unit and a second output buffer shows the circuit.

FIG. 16 shows an alternative output buffer for circuit 340 of FIG. 15A.

17A-17C illustrate the three-state buffer, the cell of FIGS. 15A and 15B or the cell of FIG. 16. This example shows an example of implementation using a module and an equivalent circuit.

Figures 18A and 18B are commonly used with three-state buffers on their outputs. 1 shows an example of a D flip-flop and its implementation using the present invention.

FIG. 19 shows the read and write control lines and A register file with data lines is shown.

FIG. 20 shows how to generate a QOE signal to control the output buffer circuit 340 of FIG. A quad output enable circuit is shown.

E1 branch 1 five standing construction and standing up Dan The logic cell of FIG. 3 has seven major sections:

(1) Programmable input inverter stage 300, (2) Cascade-in first combination Combination stage 310, (3) Feedback first combination stage 320, (4) Second combination stage Setan 330, (5) output driver stage 340, (6) Selective global reset circuit 350, (7) Configuration of this cell a set of configuration controls to control the configuration Seven sectors of units CCU1 to CCU7゜'3 The input buffer stage 300 has four input buffers 301 to 304. Each of these can be selected by the user to be inverted or non-inverted. . Optional inverters on all inputs reduce interference at the output. It is possible to remove the inverter and simply use it for the purpose of inverting the signal. It is not necessary to use combinatorial logic resources for this purpose.

The cascade-in first combination stage 310 is a 3-man powered NAND gate 311 and a 2-man powered NAND gate 311. It has an OR gate 312. OR gate 312 is cascade enable control Receives manpower 313 and cascade manpower 314 from adjacent cells. OR gate 312 provides an input to NAND gate 311. Also, selectively inverting input bar Outputs from buffers 301 and 302 are provided as inputs to NAND gate 311. It is being

Feedback first combination stage 320 also includes input buffers that are selectively brought into an inverted state. 3-power NAND gate 3 fed by output signals from 303 and 304 It has 21. NAND gate 321 further receives input from OR gate 322. The OR gate 322 receives the feed at one of its input terminals. receives the buck signal 332 and enables feedback on another input terminal. Receive bull control human power 323.

A second combination stage 330 receives the outputs from the cascade combination stages 310 and 320. It is possible to program or write to give a NAND or NOR function. be. The second combination stage 330 provides an output signal 332 and the output signal 332 can be fed back to AND gate 321 by OR gate 322. Cascade OUT is possible and becomes a cascade IN signal to further adjacent cells. can be supplied as a signal, and it is supplied to the output driver stage 340. where it can be driven onto an interconnect structure and used as an input to other cells. is possible.

Output driver stage 340 is represented in FIG. 3 by interconnect lines It and I2. buffer 341 of sufficient strength to drive the output signal onto the interconnect structure. are doing. Connections from cell outputs to interconnect lines should be made with high impedance to the interconnect lines. It has means 349 for providing a power source. Such an embodiment allows the interconnection lines to A common configuration in type circuits that alternately receive signals from multiple sources. It is possible to function as a bus. In one embodiment, the second means l5OB presents a high impedance to the interconnect lines.

Global reset circuit 350 can be used as a latch or flip-flop. This allows the cell to be reset when Circuit 350 is a global In response to the reset signal, output 332 of second combinational stage 330 is driven low. have the means. used as a latch or flip-flop in an array It is necessary to reset only the cells that are Therefore, circuit 350 Only if the feedback stage 320 is configured as a latch; Clock cycle when the cell is latched and not in data receiving mode Provides reset voltage only in part of the module. This circuit is in an inactive state In some cases, only the minimum capacity is added and the array is pulled out when resetting. Power is minimal.

The configuration control units CCtJ1 to CCU7 serve three purposes. It is used for

That is, first, applying a programming voltage to the antifuse within the interconnect structure. and second, to configure the cell, i.e. its form, during normal operation. This is to store the configuration information that makes up the The user can collect the status of all signals on the interconnect lines and transfer them to the chip. This is to enable the user to output the shifted data and inspect it.

As shown in FIG. 4, the cells of FIG. 3 preferably include eight cells CELL l to CE. Group into multiple blocks consisting of LL 8, and the 9th cell CELL 9 has multiple CCUs. The nine cells in one block can be programming to interconnect cells with each other to achieve the desired circuit design. antifuse interconnect structure (antifuse interconnection structure) capable of (represented by black dots). Figure 4 shows four cell blocks. There is. A typical integrated circuit array has 100 to 1000 These cell blocks, peripheral I10 circuits, clock oscillators, and and other overhead circuitry located along the periphery of the cell.

The logic realized in each cell CELL 1 to CELL 8 is as follows. Controlled by the CCU as explained below.

'5B 14B's 6 5A 14A Sad Yul Tachisha J1 5A to 11A are functions that can be realized in a single cell in FIG. Showing some of the features. Figures 5B to 11B show how to realize each function. 4 shows configuration control bits applied to the cell of FIG. 3; Figure 3 It is possible to understand by tracing the signal path through the cell However, none of the functions implemented in the cells of Figure 3 are antifuses or those that use signal paths through other interconnect configuration means. isn't it. Therefore, this cell provides a fast implementation of these functions.

For example, FIG. 5A has two inputs INO and INI and a selection input SEL. The figure shows a two-person multi-plexer. Figure 5B shows this two-person multi-brancher. An example of implementation is shown. Input INO is applied to line AI and input INI is applied to line AI. Applied to IN4. A selection input SEL is applied to lines A2 and A3. con stored in a memory cell that controls the configuration control unit CCU3. The logic O in (The configuration control unit will be explained in detail later). Therefore, IN The value of O is determined by the optional inverter 301 at the B input of the NAND gate 311. Power is supplied. Memo for controlling configuration control unit CCU4 The logic l stored in the recell is activated by an optional inverter 302. The SEL selection signal on gate A2 is inverted and the inverted signal is sent to NAND gate 3. 11 to the A input. The logic 0 controlling the optional inverter 303 , the SEL signal is allowed to be applied to the A input of the NAND gate 321. last , the logic 0 controlling inverter 304 causes input INI to be inverted without being inverted. Passage to B human power of NAND gate 321 is allowed.

CCUI, CCU2. Three more memory cells as represented by CCU7 controls the cell of the invention. Logic 0 in CCUZ is input to OR gate 312 is inverted on line 312, causing OR gate 312 to go high regardless of the signal on line A signal is applied to NAND gate 311. Therefore, the NAND gate 311 is As shown in Figure 5A, two-person NAND gates can be configured as logically equivalent entities. In other words, the form is constructed. A logic O in CCU7 is the input to NAND gate 321. is reversed in force, disabling the feedback loop Therefore, the NAND gate 321 is configured as shown in FIG. 5A (two-man NAND game). Operates as a client. Finally, the logic l in the CCUI performs the second combination stage 330. to operate as a NAND gate. According to De Morgan's theorem, the inverted input is A NAND gate with is equivalent to an OR gate, thus NAND gate 311 and 321 are combined with the NAND gate 330 to form the AND gate shown in FIG. and form an OR gate. Therefore, a diagram configured as shown in FIG. 5B. 3 implements the multiplexer to FIG.

6B 78 8B 6A 7A 8AO)XORXNOR(7) (7) Figures 6B, 7B, and 8B are Figures 6A and ? Realize the functions shown in A and 8A, respectively. In order to There is. These implementations can be understood from the detailed discussion of multiplexers above. It is possible to understand.

19A 9F: Rear Ru-...Chibisuta...One mouth...Ru゛ FIG. 9A shows a latch with a rear that can be realized by the circuit of FIG. are doing. Figure 3 shows the configuration in several ways to achieve static latching. It is possible to construct a figure or form, but only in one way. This will be explained below. As shown in Figure 9B, the D (data) input in Figure 9A is connected to the line in Figure 3. is provided on the online AI. The latch enable signal LE in FIG. 9A is connected to lines A2 and A. 3. Optional inverter 302 is set to the inverted state and turned on. The optional inverter 303 is set to a non-inverting state. Reset input in Figure 9A Power is supplied to line A4. Feedback control unit CCU7 outputs logic l. It is possible to set the field by applying a logic 0 to the C input of OR gate 322. enable the backup path. Therefore, the Q output signal is Feedback to NAND gate 321 via D input of R gate 322 . The AND gates ANDl and AND2 and the OR gate OR1 in FIG. 9A are the second The combination stage 330 can be configured as a NAND gate. (by De Morgan's theorem).

FIG. 9D shows a latch with clear, in which case the latch enable Signal LE has the opposite polarity as in FIG. 9A. For example, flip-flop Both polarities are needed when sequential latching is required, such as in a chip. be done. 9E shows an implementation of the latch of FIG. 9D in the circuit of FIG. 3, and FIG. 9F shows the resulting equivalent circuit. Optional inverter 3 02 is a controller to pass the LE multiplied signal through the A input of the NAND gate 311. A figure or form is configured, and the optional inverter 303 is A configuration is configured as an inverter, and the complement of A3 is NA The signal is passed to the A input of the ND gate 321.

In the circuits of Figures 9A to 9C, the input signals are the data input signal and the latch enable signal. This is the bull signal LE.

Se... 1 se... -... FIG. 1OA can be realized using the cell of FIG. 3 as shown in FIG. 10B. Showing set/reset latch.

4AND - Figures ILA and IIB show a four-person AND gate with one inverting input and the cell of Figure 3. An example of how this can be achieved is shown below. It should be noted that the second group Combiner stage 330 is configured as a NOR gate by a logic zero from CCU1. A form is constructed. For two inverting inputs (i.e. NAND gate 311 and 321), the second combination stage provides an AND function. Figure 11 In the example of A, A2 manual power is reversed. Therefore, the logic 1 in CCU4 is , and optional inverter 302 to act as an inverter. clearly , it is possible to select any combination of inverting inputs.

Cascaded 12A and IIB 6AΣm±1 FIG. 12A shows input A2. A3. A6. A8 shows an inverted 8-person AND gate. ing. As shown in Figure 128, this 8-person AND gate has a cascade feature. This is realized by using two cells shown in FIG. 3, which are connected together. Users are more more than two adjacent to form a broader or larger function It is possible to cascade cells together. Lines AI to A8 are 8 pieces , while the AND function is given as the X output.

The logic O in the cascade-in control unit CCUZa is self-a and the line 3 The signal on 14a is ignored. The optional inverter 301a is inside the CCU3. The logic O of A1 gives a non-inverted state of A1.

Optional inverter 302a causes the A2 signal to gives the inversion of . Logic l in CCU5a, CCU4b, and CCU6b is also A3. A6. Generates a reversal of A8. The feedback control unit CCU7a is provides a logic l, which causes 320a to ignore Q output signal 332a. control unit The logic 0 control signal from the unit CCU1a passes through the second combination stage 330a to 310a and 320a are given. Therefore, by de Morgan's theorem, , the output signal provided on line 332a is an AND function of A] through A4. Ko The configuration control unit CCU2b carries a logic 1, which is The cascade 332a output signal from self-a is sent to cascade unit 3 of self-b. 10b. Therefore, the cascade unit 310b has three It is a NAND function of the AND outputs of two inputs, namely A5, A6 and self a.

Importantly, the AND output of self-a can be used with either programmable mutual Reaching the input of cascade unit 310b without passing through the connector do. Therefore, this cascading reduces delay and saves interconnection resources. I have a contract. Self b further has logic O in CCU l b and CCU7b. are doing. The result is that the output B2 of self b is the AND of eight inputs A1 to A8. It is a function. In particular, the following equation holds.

B2=A1*A*A3*A4*A5*Aτ*A7*Xl Cascade path connecting output line 332a to cascade inline 314b avoids delays in output buffer 340a and input buffer 300b, but e.g. Speed of the system using wide AND gates as realized in Figure 12B In order to maximize It is desirable to apply This is because these signals reach the output at B2. This is because it is not necessary to process through two cells before reaching the cell.

It is possible to use an extra cascade-in input signal, so the AND Receive output from 332a (AND function of AI-A4) to calculate function It is not necessary to use one of the inputs A3-A3 to Therefore, 8 manual AND using 2 cells each with 4 inputs (or any other ) function. Performance is better when there are no cascading paths. Not only is it slow and some of the interconnection resources are used, but all These two cells with 8 inputs are capable of calculating 7 human functions It's nothing more than that. This is because one input is required to transfer the output of the first stage. This is because

13A-13c of D Free Pflo... Figures 13A, 13B, 13c are D An example of its implementation using a flip-flop and the cell of FIG. 3 is shown. child The flip-flop uses two cells of FIG. 3, each connected to dotted lines 7a and 7b. It is shown by . This flip-flop combines two transparent latches. 9A-9C. The latches in Figures 9O-9F form the slaves. Ru. The illustrated implementation illustrates several possible formations with the pair of cells shown in FIG. This is just one of the aspects. The D input in Figure 13A is on the line Al in Figure 13B. Supplied. The clock CK in FIG. 13A is on line A2. A3. A6. on A7 Buffer 3 is supplied and inverted by buffers 302a and 303b. Not inverted by 03a or 302b. Reset human power R is on line A4. A 5. AB and outputs 304a, 301 . b, all 3 pieces of 304b is reversed by In both cells, second combination stages 330a and 33 0b is configured as a NAND gate. Kasuke The mode enable unit 312b carries the logic l and the flip-flop The output signal on line 332a from the master section is passed through OR gate 312b. This allows the signal to pass through to the NAND gate 311b. feedback The logic l signal from control unit CCU7a and CCU7b is Enable the link path.

Therefore, the circuit of FIG. 13B formed from the two cells of FIG. It realizes Pflo Knob. This circuit should use generic interconnect structures. is formed from two cells connected by a direct connection path and therefore The signal path is connected to any input or output buffer or any programmable interconnection means. It is not something that passes through.

JK Furi, Pflo... 14A-14C Figure 14A-14c is JK Flip An example of a flop and its implementation is shown. This flip-flop converts the cells in Figure 3 into 3 14B, each of which is indicated by dotted lines 7a, 7b, and 7c in Figure 14B. Ru. Cells b and 7c realize a D flip-flop, and the cells in FIG. 13B It has a configuration similar to the shapes a and 7b. Self a is A multiplexer is implemented as in FIGS. 5A-5C.

The multiplexer connection to the D flip-flop is initiated by 1 in CCUZb. is configured through a cascade connection between self a and 7b as shown in FIG. . However, the connection L7 between the first cell and the last cell provides a Q output to self a. is required for feedback and can be shaped using general purpose interconnects. has been completed. Therefore, the general purpose interconnect line L7 can be programmed to connected to the output line B3 of self c at the grammable interconnect I71; and to input lines A2 and A3 in programmable interconnects I72 and I73. is connected to self a at As in the case of other examples, each of the CCUs 0 and l are each part of each cell to obtain the JK flip-flop in FIG. 14A. It shows the configuration of minutes.

Ba...fu 340's Output buffer stage 340 is preferably configured to provide a high impedance output signal It has a plurality of means for Electrical during anti-fuse programming Both isolation and logical isolation during cell operation are provided by output buffer stage 340. I can give it to you.

・　−Rangister Figures 15A and 15B illustrate one embodiment of a cell of the present invention. Corresponds to the elements in Figure 3 Elements in FIG. 15 that are shown in FIG. 15 have the same reference numerals. Figure 15A shows the output driver stage 340 shows details of one embodiment of buffer 341 and high impedance has an ance control unit 349.

In the first embodiment shown in FIG. 15A, electrical isolation and logical isolation are controlled separately. be controlled. Electrical isolation transistor 342 connects antifuses within the interconnect structure. from high voltages present on the interconnect structure during programming or writing of the adjacent to the interconnect line for the purpose of isolating transistors 343 and 344. It is well located. Transistor 342 is programmed with a higher voltage. When used with an antifuse interconnect structure where This allows registers 343 and 344 to have the minimum channel length. Ru.

Transistor 343 is a P-channel transistor, so it is an anti- Must be separated from the interconnect structure during fuse programming. what Therefore, the interconnect structure must be able to receive the IOV signal (or other programming voltage), but the drain of transistor 343 The PN junction between the pin and the substrate forms a forward biased diode, which The odes pull down the interconnect voltage and the programming voltage is applied. This is because it prevents The isolation transistor 342 is connected to the global control supply source S It is possible to turn off from OB.

Transistor 342 remains on during normal operation of the device. operating period During this period, the voltage on the control terminal of transistor 342 is pulled to a level higher than the supply voltage. and thus a complete rail-to-rail voltage switch of the logic signal on line 332. propagates through transistor 342. Therefore, a complete rail-to-rail A voltage swing can be applied to the input of the next cell in the logic design.

・　・　2　No transistor Figure 16 is used with an antifuse interconnect structure that reduces interconnect voltage. 3 shows another embodiment of an output buffer 340 that performs the following steps. In the embodiment of FIG. , no isolation transistor 342 is provided. Electrical isolation and logical high impedance - both of the transistors are connected by a pair of N-channel pull-up and pull-down transistors 363 and 364.

11 standing 1 In either embodiment (FIGS. 15A and 15B or FIG. 16), during cell operation, For logical control, this cell can operate as a three-state buffer. or the cell is capable of performing the selected function or functions, and The high impedance state can be controlled by the enable signal QOE. Ru. This QOE enable signal preferably controls multiple cells and It can be used to control multiple cells connected to.

Referring to FIG. 15A, during operation of this cell, transistors 343 and 344 are turned simultaneously by a high signal from high impedance control unit 349. It is possible to turn it off. On the other hand, the low output signal from the control unit 349 The Q output signal on line 332 indicates whether transistors 343 or 344 are on. Therefore, either power or ground connects transistor 342 as output signal X. Allows you to decide what will be supplied through. This second embodiment has a similar configuration. It works like this.

Cell Winter 3, Bafu 2, The NAND gate 348 controls a specific combination of configuration control signals; Preferably used to set up useful configurations and decode combinations without this configuration signal. output buffer (transistor 343 and 344) to provide a high impedance output.

In the embodiment shown in FIGS. 15A and 15B, the logic cells When configured, the output of CCU 7 is logic l. be. a pair of input lines, one for each of sections 310 and 320; Use to supply clock signals of opposite polarity. For example, connect A2 and A3 and an optional inverter 30. 2 and 303 with opposite values so that one is inverted and the other is non-inverted. It can be loaded into CCU3 and CCU4. CCU4 and CCU Since the outputs of 3 are always of opposite polarity, they are decoded by NAND gate 348. combinations that are otherwise not used.

NAND gate 348 is connected to configuration control unit CCU4. C.C.U. 3. Receives three configuration control signals from CCU7 and selectively One enable signal is received from an inverter 304 . NAND gate 348 is one condition, namely CCU4. CCU3. CCU7 output and optional input generates a low output signal in response to when the outputs of inverter 304 are all logic l; (generates high impedance output). Therefore, this configuration The combination of numbers configures the cell to be a three-state buffer. Configure. NAND gate 348 requires a separate input signal for this cell. It provides high impedance control of individual cells without having to do so.

In the embodiment of FIGS. 15A and 15B, a three-state buffer configuration is used. If the order function is to be used (CCU 7 holds logic l) and the line Both signals on pins A2 and A3 (usually used for clock signals) are reversed. triggered by a configuration signal indicating that the Ru. NAND gate 348 decodes this combination of configuration signals. Enable or disable the high impedance state by response to an input signal on line A4. On the other hand, the high impedance output Other configuration signal combinations may also be used to It is possible.

3. Logic as a buffer... Figures 17A to 17C of the cell are three-state buffers. An implementation example of this logic cell is shown. Figure 17A is a three-state buffer circuit It shows. 17B is realized with the circuit of FIGS. 15A and 15B or the circuit of FIG. 16. An example is shown. FIG. 17C shows an equivalent circuit formed by the circuit of FIG. 17B. ing. An input signal IN is applied to line AI and the configuration control A logic 0 in the control unit CCUa indicates that the optional inverter 301 is a non-inverting type. Therefore, the input signal is passed to NAND gate 1-311. Line A2 and A3 are connected to ground, and the configuration control unit CC Logic l in TJ4 and CCU3 sets them both to inverted type. enable faith EN is applied to line A4 and CCU6 is set to invert type by logic l. (In the case of an active low enable signal, CCU6 is ). The logic l in CCU7 is the logic l in CCU4 and CCU3. and the NAND gate 348 in response to the EN signal output from the inverter 304. make it possible to answer.

Therefore, when EN is in the low state, the high impedance state is enabled or When enabled and EN is low, signal IN is on the output line. Passed to X. The signal to be buffered is a function of the input signal on line A4. and a three-state control is provided on line A4. Therefore, the circuit of FIG. It operates as shown in 17A. Feedback of the Q output signal is a side effect of this implementation. This occurs as a function and does not affect the three-state output signal X in any way.

C, Cu2. CCU3. Specific combination of configuration lane states within CCU7 The configuration enables the feedback. Unit CCU 1 must be set to logic 1 (NAND) , so this cell feeds the IN signal through when the output is enabled. Ru.

The novelty here is to provide a three-state buffer with minimal additional resource usage. The objective is to detect unused CCU configuration patterns.

3. Cell as a buff Figures 18A and 18B illustrate commonly used circuits and their implementation. figure 18A shows a D flip-flop with a three-state buffer on its output. Ru. As shown in FIG. 18B, in this implementation, three adjacent logic cells 22a to 22c are used. Cells 22a and 22b are D flip-flops. cell 22c forms the master and slave portions of the three-state buffer. form.

It should be noted that the flip-flop Q output is connected to the 3-state buffer input. A cascading feature is used to

3, The individual logic cells constitute a figure or form as a three-state buffer. In addition to the ability to control logic cells using a single three-state control line, the present invention Provides the ability to disable groups. this child means that the cells in that group can be used to perform any selected function or function. It is possible to construct a figure or form, while at the same time for three-state control. This allows three-state control of cell output without using additional cells.

Returning to FIG. 15A, NAND gate 346 connects transistors 343 and and 344 to accept the low signal from NAND gate 348 or the low output enable signal. high impedance in response to either signal QOE. This QOE signal is Configuring the cell so that it generates the desired logic function and, if selected, feed the output of that function onto the bus. possible.

As shown in Figure 4, these logic cells are divided into multiple blocks of eight cells. CELL-4 to CELL-4 and four cells CELL-5 to CELL-5 to the bottom. CELL 8 is provided. A single QOE signal can simultaneously enable four cells. enable operation. Cells CELL 1 to CELL-4 are one Enabled by the QOE signal, and cells CELL 5 to CELL 8 are Enabled by another QOE signal. These QOE signals are connected to the cell CELL is generated within Q, and the cell is connected to multiple configuration control units. has a set of

FIG. 20 shows the circuitry within cell CELL-9 for generating the QOE signal.

NOR games 1-NORl 3 have a global three-state signal GTS and a selectable input signal. Receive the issue. The high global tri-state signal GTS always outputs the cell with the QOE signal. Provides high impedance on the power source. If GTS is low, QOE The signal is a selectable function. The circuit shown in FIG. 20 includes interconnect lines 1. upper As controlled by the signal and configuration control unit CCU13 , a constant signal shown as ground, and the configuration control unit CCU14 to selectively invert the signal.

Each QOE line controls 4 logic cells, so the same QOE line The logic cells controlled by the word are used to realize the bits of the same word. (addressed by the same read and write enable lines) .

Regis the restaurant 31st anniversary 1 plate One example of the usefulness of this feature is register files. Figure 19 shows read and write control 3 shows a register file with lines and data lines. ■One 5-bi Tsuto bus has 3 address lines Ao-A2. 1 write enable line WE , and one read enable line RE. Figure 19 shows 8 words It represents a cell consisting of eight columns, columns 0 to 7, for storing . in this case , three address bits Ao-A2 address eight columns. 8 columns The AND gates ANDWO to ANDW7 each have a different address. programmed to decode (configure the cell as an AND gate and 11A-11C and 12A-120 for inverting selected inputs. Please refer to ). programmed into high WE signal and AND gate ANDWO In response to the address matching the output line WRITE-WORD The output of the AND gate ANDWO on line D. It's too late. the data above Allows writing into each latch from 00 to LOn. Grounded type 3-state function The force is useful for read operations.

In the case of reading, the three-state buffer TOO to Ton is connected to the signal READ WORD. 0 and in response to a high READ WORDO signal, the latch L Data from OO to LOn is provided onto data lines Do to Dn. QOE The feature is that both the latch and the tri-state buffer can be placed within a single logic cell. This makes it possible to achieve this goal. The circuit of Figure 19 is similar to the high impedance circuit of Figure 15A. effectively implemented with the cell of the present invention using a buffer control unit 349. Is possible. A cell like the one shown in Figure 15A is called a one logic cell. . Each latch and its three-state output buffer are implemented within one logic cell. each Write enable gates ANDWO to ANDW7 are in one logic cell. and each read enable gate ANDRO to ANDR7 is realized in one logic. It is realized by the cell.

To implement such a circuit, antifuses within the interconnect structure are programmed. The lines shown in FIG. 19 are formed by ramming. The AND gate is shown in FIGS. 11A and II. It is formed as described above in connection with B.

The latch is formed as described in connection with FIG. 9B.

If one of the three-state output controls in FIG. 15, that is, the QOE signal, is used, the Three-state output buffers TOO to T7n are implemented.

Robal Lycée...350; Stage 350 includes global reset transistor 3511 transistor 352, N It has a series of transistors including an OR gate 353. global lycee The set signal GR5T is supplied to all cells, and the configuration of this cell is It is accepted regardless of the condition. The same command controls whether feedback is given or not. configuration control unit, i.e. whether the latching feature of this cell is used. Selectivity is achieved by controlling the transistor 352 from a control unit that controls the Given. The reset signal is activated only when this cell is used as a latch. is applied to pin 332. Furthermore, even if this cell is used as a latch, , a master or slave that is not in latch mode can be reset to overwrite the current value. need to be cut. The clock signal passes through line 332 and onto line Al. A global reset signal is received and the supplied D input signal is received. If the D input signal is a logic 1, then the signal provided by combinational stage 330 (logic 1) by a reset stage 350 that connects the generated pull-up and line 332 to ground. If there is a conflict between the given pulldown (reset signal) and the reset signal is present draws high current during the period. Therefore, if line 332 carries the D input signal, It is not desirable to provide a reset signal in this case. Two connected D racks In a D flip-flop with a gate (as in FIG. 13B), given At a given clock level, one latch is transparent. Yes, one is in the latching state. The GR5T signal is in a latched state (off). If the output of the optional inverter 302 is in a low state) only the latch is reset. do. If the master (Figure 13B, self a) is latched, it set and this low value is passed through the slave in the transparent state. and propagate to the output. If the slave (Figure 13B, self b) is latched , it is reset and causes the output to go low. Therefore, in the cell of Figure 3 In this case, the cell is in a feedback (latch) configuration. In some cases, the logic IGR5T signal to all transistors 351 of the array is When a reset is necessary and not unnecessary or when the power drain is high In such cases, circuit 350 allows line 332 to be pulled to ground. Ru. NOR gate 353 turns on transistor 352 only when necessary. Therefore, the latch and flip-flop configuration A selective reset for the components is achieved.

The global reset signal is preferably applied to transistor 3 adjacent line 332. 51.

This is because the global reset signal is turned off during most of the operating period of this circuit. (logic low) and the capacitance added by circuit 350 is This is because it is only one source/drain region of 51.

The specific embodiments of the present invention have been described in detail above, but the present invention The invention should not be limited to specific details, but should not be limited to anything other than the technical scope of the present invention. Of course, various modifications are possible without the above.

FIG.3 FIG.5B FIG. 6A FTG, 6B 1”IG, 8A FI, 9A FIG, 9C I"IG, 9B I"1.G, 9E FIG, l0A FIG, IOB FIG, IIA FIG, IIC FIG, IIB FIG. 14B FIG. 16 FIG. 17B Continuation of front page (72) Inventor: Trinberger, Stephen M.

Ramstad, San Jose, California 95127, United States live

Claims (14)

[Claims] 1. Receives and outputs multiple input signals in programmable logic cells Means are provided for providing a signal; Means are provided for generating two functions of said input signal, said two functions being cannot be made equivalent by inverting the selected input or output signal. is a function, making a selection between said two functions and selecting one of said two functions; A program characterized in that a function selector is provided to supply the output signal as the output signal. Logrammable logic cell. 2. In claim 1, the two functions are an AND function and a sum function of products. Features a programmable logic cell. 3. In claim 2, the means for generating the two functions comprises two NAND games. each receiving some of said inputs and generating an intermediate output signal. two NAND gates, and a NAND gate and a NOR receiving the intermediate output signal; A gate that can be programmed as a gate and generates the output signal. A programmable logic cell comprising: 4. In claim 1, further: whether one of said input signals is applied to a first one of said NAND gates; means are provided to control the The output signal is a second one of the NAND gate as another one of the input signals. characterized in that means is provided for controlling whether or not the voltage is applied to the object. programmable logic cell. 5. 5. According to claim 4, one of the input signals is connected to the first NAND gate. the means for controlling whether the output signal is applied to the second NAND Each of said means for controlling whether or not to be applied to the gate has a two-input OR gate. one input receives said input or output signal and another input receives the configuration signal. A program characterized in that it receives a signal from a regulation control memory means. Mable logic cell. 6. In claim 5, each of the configuration control means includes a shift lever. A programmable memory cell characterized in that it is a memory cell connected as part of a register. Lulogic Cell. 7. 6. In claim 5, each of said configuration control means has a high or low Characterized by being a line connected by programming to the supply voltage programmable logic cell. 8. Multiple forms, each capable of performing both combinatorial and sequential logic In a reset control circuit for an array of configurable logic cells, the option feedback loop (332, 322), said optional feedback loop (332, 322); means for enabling the clock loop (CCU7); means (350) for connecting said feedback loop to a reset voltage; means for supplying a reset control signal (GRST), means for controlling the connection means; means for enabling said optional feedback loop (CC U7) is enabled and the reset control signal (GRST) is supplied. control means comprising means (353) for enabling said connecting means only when the A reset control circuit comprising: 9. 9. Each of the logic cells includes means for receiving a clock signal. and the clock means clocks the logic cell to clock the feedback clock. Transparent mode and latched mode when loop is enabled and the control means is further configured to switch the mode between The connection means is enabled only when the logic cell described above is operated in latch mode. 1. A reset control circuit comprising means for disabling the reset control circuit. 10. A means of executing selected logic functions in programmable logic cells , output buffer (340), to provide a high impedance output or to provide said selected logic function. means (CCU1-CCU7.348) for configuring the form of the logic cell; A programmable logic cell characterized by: 11. 11. The means for executing the selected logical function comprises a plurality of It has logical units (300, 311, 321, 330), each of which has a small be configured to execute the selected unit function of at least one input signal; and the unit is configured such that the selected unit function is connected to each other to cause the selected logic cell function to be executed. A programmable logic cell characterized by: 12. According to claim 11, further comprising: for causing the selected unit function to be executed. and means (CCUI-CCU7) for configuring each of the units. Features a programmable logic cell. 13. 13. The output of claim 12 to provide the high impedance output. The means for configuring the force buffer has a plurality of inputs and in a first state. said logic cell to provide a high impedance output and said logic cell in a second state. To provide an output signal that does not cause a logic cell to provide a high impedance output. logic gate (348), the unit (CCU4, CCU5, CCU7) at least one signal from at least one of said means for configuring each of the means for supplying as an input to said logic gate, one of said input signals (13); providing at least one signal related to the logic gate as an input to the logic gate; means, wherein the logic gate controls each of the units. said at least one signal from one of said means for configuring and said input signal. in response to a combination with said at least one signal related to one of said A programmable logic cell characterized by taking a first state. 14. In the programmable logic cell, the first and second programmable logic A network unit is provided, each having a plurality of inputs for receiving an input signal. each having an output terminal for providing an output signal. a third programmable logic having two input terminals and one output terminal; A dock unit is provided, and the input terminal is connected to the first and second programmable blocks. receives a signal from the output terminal of the third program logic unit; a programmable logic unit in front of the first and second programmable logic units; means for calculating a NAND function of the signal on the output terminal; and said first and second program means for calculating a NOR function of the signal on the output terminal of the rumble logic unit; and converting the NAND function to the output of the third programmable logic unit. select between applying the NOR function on the output terminal and applying the NOR function on the output terminal. A programmable logic cell characterized in that it has means for selecting.