JPH0749371A - Gps receiving system - Google Patents

Abstract

PURPOSE:To provide a GPS receiving system to perform highly accurate position measurement without increasing the load of a processor and making a circuit larger. CONSTITUTION:The title system is composed of a PN-code generation means 54 which outputs a PN code of a desired GPS satellite, an epoch signal per one cycle of the PN code and a value indicating the PN code order outputting in the PN codes, a shift means 56 which generates a plurality of PN codes that are selected by a selector and are given by a specified phase difference, a phase difference detection circuit 52 for performing relative processing for received PN code and a plurality of selected PN codes, and a measurement computing part 400b which tracks the signal and measures the position based on the relative processing results of the circuit 52, the PN code order and epoch signal count value held in a holding means 58, and the selected step position of a shift register by the use of the selector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GPS receiver used in a Global Positioning System (GPS), and more particularly to a GPS receiver. The present invention relates to a GPS receiving device that receives a radio wave, processes information superimposed on the radio wave, and measures the position of a reception point.

[0002]

2. Description of the Related Art A GPS receiver receives GPS radio waves transmitted from a plurality of GPS satellites, and a pseudo noise signal (hereinafter referred to as a PN code) superimposed on the radio waves and 5
The position where the GPS receiver is placed is measured based on the navigation data of 0 bit / sec.

As is well known, the PN code is a code string composed of a chip rate of 1.023 MHz and a period of 1023 chips, and has a code string unique to each satellite. The repetition cycle of the PN code is 1 msec, the epoch signal is output at the start position of the PN code, has the cycle of the PN code, and is synchronized with the changing point of the navigation data.

As is well known, the measurement of the position of the receiving point in the GPS receiver is performed by receiving GPS radio waves from four or more satellites and measuring the distance between each satellite and the receiving point. For the measurement of, it is necessary to track the PN code peculiar to each satellite superimposed on each radio wave and demodulate the navigation data.

Usually, in the GPS receiver, the GPS
Correlation processing is performed between the PN code in the received signal from the satellite and the PN code generated in the GPS receiver to obtain both PN codes.
By matching the codes on the time axis, the PN code is despread and the navigation data can be demodulated. At the same time, the satellite time can be measured based on the time in the GPS receiver. , The pseudo distance can be measured.

FIG. 6 shows a configuration of a PN code tracking circuit of the conventional GPS receiver 2. The GPS reception signal 4 received by the reception antenna and converted into a signal having a predetermined amplitude and frequency by the high frequency conversion means is input to the mixer 6. On the other hand, the GPS receiver 2 has a carrier generator 8
The carrier signal output from the carrier generator 8 serves as the other input of the mixer 6. The output of the mixer 6 is the spectrum despreaders 10a, 10b,
It is input to each of 10c.

Further, the GPS receiver 2 has a PN code clock generator 12, and a clock signal having the same frequency as the chip rate frequency of the PN code, that is, a frequency of 1.023 MHz (hereinafter, this clock signal is PN code clock) is generated. Further, the PN code clock generator 12 outputs the phase information of the PN code clock, and the phase output of the PN code clock is sent to the pseudo distance measuring means 14.

The PN code generator 16 outputs three codes which are the same PN code, a P code, an E code and an L code, using the PN code clock as a drive clock signal. E code is for P code, and P code is for L
A 1/2 chip phase is advanced for each code. The PN code chip phase information is also output from the PN code generator 16, and this PN code chip phase output is also sent to the pseudo distance measuring means 14.

The P code, the E code, and the L code are the other inputs of the spectrum despreaders 10a, 10b, and 10c, respectively, and the spectrum despreading processing of the GPS reception signal 4 is performed. Each of the results of spectrum despreading is input to the low-pass filters 18a, 18b, 18c,
Correlation signals V (p), V (e), V (l) are obtained as the outputs of the low-pass filters 18a, 18b, 18c. The correlation signals V (e) and V (l) are subtracted by the subtractor 20 to obtain a correlation signal V (e-1). These correlation signals V
(P) and V (e-1) are input to the tracking control means 22.

The tracking control means 22 controls the frequency and phase so that the carrier signal coincides with the modulated signal of the frequency-converted GPS reception signal 4. Here, the calculation and processing performed by the subtractor 20 and the tracking control means 22 can be easily performed by the processor, and at the present time when the processor is available at a low price, it is generally configured using the processor. There is.

FIG. 7 shows the correlation characteristic thus obtained, and here, the correlation characteristic of the correlation signal V (e-1) is shown. In FIG. 7, the vertical axis represents V (e-
l), the horizontal axis represents the chip phase shift value. If the PN code clock phase is delayed, tracking control means 2
When the PN code clock generator 12 is driven via 2 and the correlation signal V (e-1) works to accelerate the PN code clock, and conversely, when the PN code clock phase is advanced, , The correlation signal V (e-1) acts to slow the PN code clock.

By the above-mentioned operation, the GPS speed can be increased or decreased by increasing or decreasing the speed of the PN code.
The PN code generated on the receiving device 2 side is the received GPS
To match the PN code of the received signal 4, that is,
It is controlled so that it is always located at the tracking point P in FIG.

The pseudo range measuring means 14 receives the PN code clock phase information and the PN code chip phase information from each of the PN code clock generator 12 and the PN code generator 16, that is, the tracking satellite time information. By receiving the time, the time is compared with the time of a clock (not shown) built in the GPS receiving device 2, the time difference is detected, and the pseudo distance between the tracking satellite and the GPS receiving device 2 is obtained. And measure the position of the receiving point.

[0014]

However, in the above-mentioned conventional GPS receiver, it is necessary to finely control the tracking accuracy of the PN code clock in order to always maintain the position measurement accuracy at a high accuracy. Since the processing for finely controlling the tracking accuracy is performed by the processor, there is no choice but to place a heavy load on the processor. Therefore, it is essential to use a processor having a sufficient processing capacity for processing a large load, and as the processing load increases, the capacity of the memory equipped in the processor also increases.

That is, in the conventional GPS receiver, in order to perform highly accurate position measurement, it is necessary to use a processor with high processing capability, in other words, a high-priced processor and a large-capacity memory. It was inconvenient. Further, it is necessary to equip a PN code clock generator capable of high resolution control, which causes a problem that the circuit scale of the PN code clock generator becomes large. Due to these inconveniences, there has been a problem that the price reduction and size reduction of the GPS receiving device are hindered.

Therefore, an object of the present invention is to eliminate the above-mentioned inconvenience, and to perform highly accurate position measurement without increasing the load on the processor and without increasing the circuit scale. It is an object of the present invention to provide a GPS receiver which can be manufactured at low cost and can be downsized.

[0017]

In order to achieve the above object, the present invention according to claim 1 is a GPS receiving apparatus for receiving radio waves from a plurality of GPS satellites and measuring the position of the receiving point. PN code generating means for inputting a received signal obtained by frequency-converting a GPS satellite signal, generating a desired PN code, an epoch signal for each cycle of the PN code, and a value indicating the order of PN codes to be output, P
Maximum of 2 epoch signals output from N code generation means
An epoch counter which counts to 0, a shift register which receives a PN code output from the PN code generating means and outputs a plurality of PN codes having a predetermined phase difference, and a plurality of PNs from the shift register. A code is input, and a first PN code serving as a center and a second PN having a phase advanced by a predetermined value with respect to the first PN code.
A third PN code whose phase is advanced by a predetermined value and a fourth PN code whose phase is delayed by a predetermined value with respect to the code;
The sixth PN code whose phase is advanced by a predetermined value and the seventh PN code whose phase is delayed by a predetermined value with respect to the fifth PN code whose phase is delayed by a predetermined value with respect to the N code are output, and the shift register Of the first PN code, the selector for outputting the information of the stage position at which the first PN code is output, the first PN code output from the selector, and the third P
N code, 4th PN code, 6th PN code, 7th
Of the PN code, and a phase comparator for performing a phase comparison between each of the PN codes and the frequency-converted reception signal, and a phase comparison output of the reception signal and the third PN code and a reception signal. Two subtractions that output the difference in the phase comparison output with the sixth PN code, and the difference in the phase comparison output between the received signal and the fourth PN code and the phase comparison output between the received signal and the seventh PN code Error detection circuit having a controller, a first holding circuit for holding a value indicating a stage position where the first PN code is output from the selector, and an order of the PN code output from the PN code generating means. And a third holding circuit for holding the count value from the epoch counter,
It is characterized by comprising a fourth holding circuit for holding the output of the phase error detection circuit.

Further, in the GPS receiving apparatus according to the first aspect, a value indicating a stage position at which the PN code output from the selector is output by the first to third holding circuits, and P
It is characterized in that the value indicating the order of the PN codes output from the N code generating means and the output of the epoch counter are simultaneously held at an arbitrary time in the receiving device.

Further, in the GPS receiving apparatus according to the first aspect, from the conversion table which inputs the value held in the second holding circuit and outputs the value indicating the order of the PN code being output from the epoch signal as a base point. It is characterized by being configured.

In the GPS receiver according to the second aspect, the pseudo distance between the satellite and the receiving point is calculated from the outputs of the first holding circuit, the conversion table, the third holding circuit, and the fourth holding circuit, It is characterized by comprising a positioning calculation unit for measuring the position of the reception point.

[0021]

The GPS receiving apparatus according to the present invention is used for a desired GPS.
Satellite PN code, epoch signal for each cycle of the PN code, and P output from the PN code
It has a PN code generating means for outputting a value indicating the order of N codes, and P outputted from the PN code generating means.
The N code is shifted by the shift register, and five PN codes having a predetermined phase difference are selected by the selector and output.

The plurality of PN codes are input to the phase error detection circuit and subjected to correlation processing with the received GPS satellite signals. On the other hand, a value indicating the order of the PN codes in one cycle output from the PN code generating means, the count value of the epoch signal, and the value indicating the stage position of the PN code of the shift register output by the selector are held by the holding circuit. , To the positioning calculation section of the signal tracking means. On the other hand, the value indicating the order of the held PN codes is input to the conversion table, and P is set with the epoch as the base point.
A value indicating the order of the N code, that is, the chip number of the PN code is output.

Similarly, the phase error output of the PN code in the phase error detection circuit is sent to the positioning calculation section of the signal tracking means via the holding circuit, and in the positioning calculation section, the step position of the held PN code is indicated. Each GP based on the value, the chip number obtained by the conversion table, the held epoch counter value, and the held phase error output.
The time difference between the S satellite and the GPS receiver is calculated,
The pseudorange is calculated. From this result, the position at the reception point of the GPS receiver is measured.

With such a configuration, in the GPS receiving apparatus according to the present invention, the PN code generated in the GPS receiving apparatus is highly accurate with respect to the PN code received from the GPS satellite as in the conventional case. It is not necessary to perform control and tracking so that they always coincide with each other, and control and tracking may be performed with rough accuracy so that the PN code received from the GPS satellite is not lost. Therefore, the load on the processing processor for tracking the GPS satellites is reduced, and it is not necessary to use a high-resolution PN code clock generation circuit.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A GPS receiver according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1A is a block diagram showing a schematic configuration of a GPS receiver 50 according to the present invention, and FIG. 1B is a block diagram showing a schematic configuration of a signal processing means 300a in FIG. 1A.

In FIG. 1A, the GPS receiver 50 is
Radio waves from GPS satellites are received from the antenna 100 and converted into electric signals. The high frequency signal conversion means 200 receives the GPS signal from the antenna 100 as an input and converts it into an intermediate frequency band signal that is sufficiently lower than the frequency of the carrier wave signal, and at the same time converts it into a signal having a predetermined amplitude. The intermediate frequency band signal output from the high frequency signal conversion means 200 is a modulated wave of the intermediate frequency band signal, and has a PN code and 50B.
The signal becomes a signal modulated by the navigation data of PS (bits / second), and the N signal processing means 300a, 300b, ...
It is input to each of 300n.

The signal tracking means 400 receives signals from the respective signal processing means 300a, 300b, ..., 300n as input and performs calculation for tracking each GPS satellite signal,
Based on the result, each signal processing means 300a, 300
, 300n are controlled to demodulate navigation data from each GPS satellite and a signal tracking unit 400a that performs signal tracking, and pseudo distances from each GPS satellite are obtained to measure the position of the receiving point. The positioning calculation unit 400b includes a holding circuit 3 described later.
The conversion table 4 storing the chip number of the PN code corresponding to the output state of the holding circuit 362 with reference to the output of 62.
00c is provided. This signal tracking means 400 is
For example, it can be physically composed of a processor and a memory attached to it, and is composed of processing for signal tracking and positioning calculation and control program routines stored in advance in the memory.

Signal processing means 300a, 300b, ..., 3
In each of 00n, the GPS satellite signals different from each other are captured and tracked, but the method is the same as that of each signal processing means. Hereinafter, the signal processing means 300a shown in FIGS. 1A and 2 will be described.

In FIG. 1B, the signal processing means 300a.
Is a predetermined PN code, an epoch signal for each cycle of the PN code, a PN code generation means 54 for generating a value indicating the order of the PN code being output, and an output of the PN code generation means 54 as inputs, 5 Ps in phase
Shift means 56 for outputting N code, and shift means 56
A holding means 58 for holding the stage position of the specified PN code output from the PN code, a value indicating the order of the PN code in one cycle output from the PN code generating means 54, and a count value obtained by counting the epoch signals; The PN code in the input reception signal obtained by frequency-converting the GPS satellite signal and the five PN codes in a predetermined phase relationship output from the shift means 56 are input, and the plurality of PN codes are input.
Each of the codes is subjected to correlation processing with the PN code in the GPS received signal, and a plurality of correlation processing results are output, and a phase error detection circuit 52 for detecting a phase error is configured.

The output of the holding means 58 is the signal tracking means 40.
0, and the positioning calculation unit 400b measures the position of the reception point by the GPS receiving device 50.

FIG. 2 is a diagram showing a more detailed structure of the signal processing means 300a. The intermediate frequency band signal received from the GPS satellite signal and output from the high frequency signal converting means 200 is a phase comparator 311, 321. 323, 331, 3
It is input to each of 33. The intermediate frequency band signal is a hard-limited digital signal, and the subsequent processes are processed as digital signals, and the phase comparators 311 and 32 are processed.
1, 323, 331, and 333 are usually constituted by exclusive OR circuits.

On the other hand, the clock signal SCK is a clock signal having a frequency that is an integral multiple (N times in this embodiment) of the chip rate of 1.023 MHz of the PN code, is input to the PN code generating means 372, and is input to the PN code generating means. 37
In 2, the desired PN code (PN corresponding to the PN code of the GPS satellite to be tracked is controlled by the signal tracking means 400.
Code), and has a function of generating an epoch signal synchronized with this PN code.

The PN code generated by the PN code generating means 372 is input to the shift register 391. The shift register 391 is composed of M stages of registers and is sequentially shifted by 1 / N chip by the clock signal SCK. The output of the M-stage shift register 391 is input to the selector 392.

Under the control of the signal tracking means 400, the selector 392 outputs a plurality of PN codes from the M outputs of the shift register 391, that is, a first PN code, a P code, and a second PN code. E code, (E +) code that is the third PN code, (E-) code that is the fourth PN code, L code that is the fifth PN code, (L +) code that is the sixth PN code, 7th P
It has a function of selecting an (L-) code which is an N code and outputting five signals other than the E code and the L code. In the present embodiment, the relative phase relationship of the PN code is such that the E code is advanced by 1/2 chip phase with respect to the P code, and the L code is delayed by 1/2 chip phase with respect to the P code. It is in. The phase of the (E +) code is advanced by dt with respect to the E code, and the phase of the (E-) code is delayed by dt. Similarly, the phase of the (L +) code is advanced by dt with respect to the L code, and the phase of the (L-) code is delayed by dt.

In the selector 392, P code, E code, (E
The relative phase relationship among the + code, the (E-) code, the L code, the (L +) code, and the (L-) code is always maintained. 5 selected PN codes P code, (E +) code, (E-) code, (L +)
Each of the code and the (L-) code is a phase comparator 311.
And a phase comparator 321 in the phase error detection circuit 320,
PN from the GPS satellite signal included in the intermediate frequency band signal that is input to each of 323, 331, and 333.
Correlation processing with the code is performed.

Further, the carrier generator 350 has two signals CA which have a desired frequency and are 90 ° out of phase with each other.
0, CA90 is output. The frequency can be finely changed by the control of the signal tracking means 400. The signals CA0 and CA90 are supplied to the phase comparators 312, 313, 322, 324, 332 and 33, respectively.
4 and the frequencies of the signals CA0 and CA90 are controlled to match the carrier frequency in the intermediate frequency band signal.

The outputs PI and PQ of the phase comparators 312 and 313, respectively, are input to counters 351, 352 which act as low pass filters, while the outputs (EI +) and (LI +) of the phase comparators 322, 332 are It is input to the subtractor 341 [(E−L)
+], That is, the difference between (EI +) and (LI +) is calculated, and the result is input to the counter 353. Similarly, the outputs (EI−), (LI) of the phase comparators 324, 334
-) Is input to the subtractor 342, [(EL)-], that is, the difference between (EI-) and (LI-) is calculated, and the result is input to the counter 354. Counter 35
Similarly to the counters 351 and 352, the reference numerals 3 and 354 act as a low-pass filter.

These phase comparators 321, 322, 32
3, 324, 331, 332, 333, 334, subtractors 341, 342 and counters 351, 352, 35
The phase error detection circuit 320 is composed of 3, 354.

Counters 351, 352, 353, 354
And the holding circuit 355 respectively have an epoch signal (E
POCH) is input, and the holding circuit 355 holds the added value of the counters 351, 352, 353, 354 up to that point, and immediately after that, each counter 351,
352, 353, 354 are reset. Holding circuit 3
The added value held in 55 is sent to the signal tracking means 400.

On the other hand, the holding circuit 361 receives the stage position information of the register outputting the P code from the shift register 391, that is, the value indicating the number of shift stages of the P code in the shift register 391, and the holding circuit 362.
Then, the order of the PN codes output from the PN code generating means 372 within one cycle, that is, a value indicating the position of the chip of the PN code with the epoch signal output time as the base point is input.

The configuration of the PN code generating means 372 in this embodiment will be described below with reference to FIG.

As is well known, the PN code (generally referred to as the C / A code) in the GPS receiver 50 is the G1 generator and the G2 generator.
The Gold code is formed by the product of two 1023-bit PN codes (pseudo noise codes).

In FIG. 3, the frequency divider 501 is 1.023.
The frequency divider 501 is a frequency divider that performs a frequency division by N with a clock signal SCK having a frequency N times that of MHz, and the output of the frequency divider 501 is a clock signal having a frequency of 1.023 MHz. 5
It becomes the input of 03. Further, the frequency divider 501 has a function of changing the frequency division ratio under the control of the signal tracking means 400, and controls the phase delay of the PN code by changing the frequency of the output clock. be able to.

On the other hand, G1 generator 502 and G2
As is well known in the GPS receiver 50, the generator 503 is a 1023-bit P code generator,
Each is composed of a shift register of 10 stages. In the G1 generator 502, P1, P2,
..., P10 is an output from each stage, and similarly, S
, S10 are outputs from the respective stages of the G2 generator 503, and are input to the phase selector 504. In the phase selector 504, two outputs are selected from S1, S2, ..., S10 under the control of the signal tracking means 400, and an output g obtained by multiplying the selected two outputs is taken.
2 is output. The selection of the PN code corresponding to each GPS satellite depends on two signals selected by the phase selector 504, as is well known.

On the other hand, in the integrator 506, the product of the output P10 of the G2 generator 503 and the output g2 of the phase selector 504 is taken and output as a PN code corresponding to each GPS satellite. Normally, the integrator 506 is formed by exclusive OR.

The outputs P1, P2, ..., P10 from the G1 generator 502 are input to the holding circuit 362 and the epoch generating circuit 505.

On the other hand, the combination of the states of P1, P2, ..., P10 changes every clock of 1.023 MHz.
Twenty-three states are repeated. That is, P1, P2,
The state of P10 indicates the position of the chip of the PN code output at that time.

In the epoch generating circuit 505, PN
The state of the start of the code, that is, P1, P2, ..., P1
All 0's detect the state of "1" and output it as an epoch signal.

The epoch counter 373 is a counter for counting up to 20 epoch signals (EPOCH) (up to 20 msec for each 1 msec epoch signal).
The count value of the epoch counter 373 is input to the holding circuit 363.

The epoch counter 373 counts up to 20 epoch signals because 20 epoch signals correspond to one bit of navigation data and are handled as one unit.

A hold pulse HCK is input to each of the holding circuit 361, the holding circuit 362, and the holding circuit 363, and at any time of the GPS receiving device 50,
Each input value can be held, and the held value is sent to the signal tracking means 400. Therefore, the time information included in the data held in the holding circuits 361, 362, and 363 is the coarsest in the holding circuit 363 that increases by “1” in 1 msec, and the second holding circuit 362 that changes based on the 1.023 MHz clock. Coarse, clock signal H
The holding circuit 361 that changes based on CK is the most precise (F
INE).

In the signal tracking means 400, the signal tracking section 400a operates so as to track the PN code and the carrier signal in the intermediate frequency band signal. That is, the PN code generating means 372 and the selector 392 are controlled so that the P code output from the selector 392 comes closest to the received PN code, and the carrier generator 350 with respect to the carrier signal. The carrier generator 350 is controlled so that the frequency and phase of the output CA0 from the output signal CA0 match.

On the other hand, the signal tracking means 400 is provided with a positioning calculation section 400b, and counters 353 and 354 for giving the output of the holding circuit 361, the holding circuit 362 and the holding circuit 363 and the phase information of the phase error detection circuit 320. Using as an input, the time of the GPS satellite at an arbitrary time of the GPS receiving device 50 can be obtained, and the pseudo distance can be obtained from the time difference from the GPS receiving device 50.

In particular, the positioning calculation unit 400b has a conversion table 400c, and the conversion table 4 stores the S1, S2, ..., S10 held by the holding circuit 362.
00c is input, and the chip number of the PN code corresponding to the input state is output. In other words, the PN code start state, that is, the chip number counted from the epoch signal output time is output.

By performing this processing for a plurality of GPS satellites, the position at the receiving point of the GPS receiving apparatus 50 is measured.

Next, a method of obtaining the time of the GPS satellite will be described. Correlation characteristics S (P) and S [(E
-L) +] and S [(E-L)-] are output PI of the phase comparator 312 and outputs [(E-L) +] and [(E-L) + of the subtracters 341 and 342 of FIG. 2, respectively. L)-], the (S +) and (S-) include the phase error between the PN code in the input GPS satellite signal and the P code output by the selector 392. There is.

On the other hand, since the frequency of the shift clock SCK of the shift register 391 is 1.023 MHz × N, the tracking resolution is [1 / (1.023 MHz × N)], and the P code is the input PN code. It cannot be an exact match. In FIG. 4, Sa, Sb, Sc
Are correlation characteristics S (P), S [(E−L) +], S [(E−
L)-] shows the tracking point of the PN code above, and (S)
+) And (S-) indicate the added values of the counters 353 and 354, respectively.

Td, that is, the phase difference between the input PN code and the P code which is the output of the selector 392 can be obtained by the following equation.

Td = [((S +) + (S-)) / ((S
+) − (S −))] × dt × T where T = 1 / [1.023 × 10 ⁶ ].

Therefore, the value held in the holding circuit 361 at the time T _i of the GPS receiver 50, the holding circuit 362.
The value converted by the conversion table 400c in the positioning calculation unit 400b based on the value stored in the holding circuit 3
The values held in 63 are respectively K, PN (T _i ), E
If P (T _i ), then GP measured at time T _i
The time T _{sv of the} S satellite can be expressed as follows.

T _sv = 0.001 × EP (T _i ) + 1 / [1.023 ×
10 ⁶ ] × PN (T _i ) + [1 / (1.023 × 10 ⁶
× N)] × K + Td (T _sj-1 ) + [Td (T _sj ) −Td
(T _sj-1 )] × [PN (T _sj-1 ) + (K / N) / 102
3] However, the time at which the epoch signal (EPOCH) that is the timing for holding the added value is output as shown in FIG. 5 does not match the time Ti of the GPS receiving device 50, so
Interpolation is performed using the Td values at the EPOCH timings T _sj-1 and T _sj that sandwich the time Ti.

As described above, the time of the GPS satellite can be known at any time of the GPS receiver 50, and the same applies to the other signal processing means 300b to 300n. The distance to the GPS receiving device 50 can be measured, and the position at the receiving point of the GPS receiving device 50 can be measured.

[0063]

According to the GPS receiver of the present invention,
The following effects can be obtained. That is, as in the past, GP
There is no need to control and track the PN code generated in the GPS receiver with the PN code received from the S satellite with high accuracy and at all times, so that the PN code received from the GPS satellite is not lost. Moreover, it is sufficient to control and track with rough accuracy. Therefore, the load on the processing processor for tracking the GPS satellites is reduced, and
Since it is not necessary to use a high-resolution PN code clock generation circuit, it is possible to provide a GPS receiver capable of performing highly accurate position measurement without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a GPS receiver according to the present invention.

FIG. 2 is a configuration diagram of signal processing means in the GPS receiving device.

FIG. 3 is a block diagram showing a configuration of PN code generating means of the GPS receiving apparatus according to the present invention.

FIG. 4 is a diagram showing a correlation characteristic by the GPS receiving apparatus according to the present invention.

FIG. 5 is a time chart showing the relationship between the epoch signal and the time of the GPS receiver.

FIG. 6 is a diagram showing a configuration of a conventional GPS receiver.

FIG. 7: PN code and G in a conventional GPS receiver
It is a figure which shows the correlation characteristic with the PN code received from a PS satellite.

[Description of Codes] 50 ... GPS receiver 52 ... Phase error detection circuit 54 ... PN code generation means 56 ... Shift means 58 ... Holding means 100 ... Antenna 200 ... High frequency signal conversion means 300a-3
00n ... Signal processing means 311 to 313, 321 to 324, 331 to 334 ... Phase comparator 320 ... Phase error detection circuit 341, 34
2 ... Subtractor 350 ... Carrier generator 351-35
4 ... Counter 355, 361, 362, 363 ... Holding circuit 372 ... PN code generating means 373 ... Epoch counter 391 ... Shift register 392 ... Selector 400 ... Signal tracking means 400a ... Signal tracking section 400b ... Positioning calculation section 400c ... Conversion table 501 … Divider 502… G1
Generator 503 ... G2 generator 504 ... Phase selector 505 ... Epoch generation circuit 506 ... Accumulator

Claims (4)

[Claims] 1. A GPS receiver that receives radio waves from a plurality of GPS satellites and measures the position of the receiving point,
PN code generating means for inputting a received signal obtained by frequency-converting a PS satellite signal, a desired PN code, an epoch signal for each cycle of the PN code, and a value indicating the order of the PN code to be output; An epoch counter that counts up to 20 epoch signals output from the code generation means, and a shift register that receives a PN code output from the PN code generation means and outputs a plurality of PN codes that are deviated by a predetermined phase value. A plurality of PN codes from the shift register are input, and a first PN code at the center and a second PN code whose phase is advanced by a predetermined value with respect to the first PN code, A third PN code whose phase is advanced by a predetermined value and a fourth PN code which is delayed by a predetermined value, and a phase is delayed by a predetermined value with respect to the first PN code. For the fifth PN code,
Information on the stage position at which the sixth PN code whose phase is advanced by a predetermined value and the seventh PN code which is delayed by a predetermined value are output, and from which the first stage of the shift register is used as a base point, the first PN code is output. And a first PN code, a third PN code, a fourth PN code, a sixth PN code, and a seventh PN code output from the selector, and each of the PN codes is input. And a phase comparator for performing a phase comparison between the frequency-converted reception signal and a phase comparison output between the reception signal and the third PN code and a phase comparison output between the reception signal and the sixth PN code. , And a phase error detection circuit including two subtractors for outputting a difference between a phase comparison output of the received signal and the fourth PN code and a phase comparison output of the received signal and the seventh PN code, and the selector. A first holding circuit for holding a value indicating the stage position at which the first PN code is output, and a second holding circuit for holding a value indicating the order of the PN codes output from the PN code generating means. A GPS receiving device comprising a third holding circuit for holding a count value from the epoch counter and a fourth holding circuit for holding an output of the phase error detection circuit. 2. The GPS receiver according to claim 1, wherein
By the first to third holding circuits, a value indicating the stage position at which the PN code output from the selector is output, a value indicating the order of the PN code output from the PN code generating means, and the output of the epoch counter. The GPS receiving device is characterized in that the GPS receiving device is simultaneously held at any time in the receiving device. 3. The GPS receiver according to claim 1, wherein
A G is characterized in that it is composed of a conversion table for inputting the value held in the second holding circuit and outputting a value indicating the order of the PN code being output from the epoch signal as a base point.
PS receiver. 4. The GPS receiver according to claim 3,
First holding circuit, conversion table, third holding circuit, fourth
A GPS receiving device comprising a positioning calculation unit that calculates a pseudo distance between a satellite and a receiving point from the output of the holding circuit and measures the position of the receiving point.