JPH0746488A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To allow the device to cope with occurrence of a new defect picture element with simple circuit configuration without need for the measurement of a defective picture element in advance. CONSTITUTION:Defect detection circuits 30, 40 compare a signal charge transferred in time series with a reference value to detect a defective picture element. A reset block circuit 33 uses a detection signal of the defect detection circuit to block a reset signal for resetting a charge detection capacity at the detection of a defective picture element and allows the charge detection capacitor to store the signal charge of the picture element just before the defective picture element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device using a solid-state image pickup device having a large number of pixels.

In recent years, a solid-state image pickup device having a photoelectric conversion element section in which a plurality of light receiving elements are two-dimensionally arranged on a semiconductor substrate and a circuit section for reading out a photoelectrically converted signal has been increasing the number of pixels and achieving high resolution. Has been. With the increase in the number of pixels,
It is difficult to manufacture a pixel without defective pixels over all pixels, and a technique for reducing the influence of defective pixels is required.

[0003]

2. Description of the Related Art FIG. 5 shows a circuit diagram of an example of a conventional device.
In this example, a CCD solid-state image pickup device having 4 × 4 pixels will be described as an example. In the figure, 4 composed of photodiodes
The signal charges output from each pixel 11 of the × 4 pixel array are transferred vertically by a CCD (charge coupled device) 1
2 _{1 to} 12 ₄ are supplied to each of the CCDs 12 _{1 to} 12 ₄ according to the vertical transfer control clock and are supplied to the horizontal transfer CCD 15, and further are transferred to the inside of the CCD 15 according to the horizontal transfer control clock. Then, the charges are stored in the charge detection capacitor 17 for each pixel from the final stage 151 of the CCD 15 through the output adjustment gate 16. The charge detection capacitance 17 is 1
Before starting the above-mentioned accumulation for each pixel, the reset gate 18 is made conductive to reset the accumulated charge of the previous time. The charge detection capacitor 17 is composed of a floating diffusion layer. The output amplifier 19 converts the signal charge accumulated in the charge detection capacitor 17 into a voltage signal and outputs the voltage signal as an image signal. At this time, the voltage V _G applied to the output adjustment gate 16
Is adjusted so that the charge accumulated in the charge detection capacitor 17 does not flow back to the final stage 151 of the CCD 15.

A part of the pixels 11 of the solid-state image pickup device 10 described above.
When a defect occurs in the image, the image signal becomes as shown in FIG. Here, the pixel is a defect in which the signal charge is not detected at all due to disconnection or the like, and the pixel is a defect in which the signal charge is generated up to full scale due to the leak current of the photodiode or the like.

A defective pixel replacement circuit 20 is provided to compensate for such a pixel defect. The image signal output from the output amplifier 19 is supplied from the transmission cable to the buffer amplifier 21 in the replacement circuit 20 and from here to the sample hold circuit 22. The defective pixel position measured in advance is stored in the memory circuit 23, and the sample and hold control circuit 24 stops the sampling operation of the sample and hold circuit 22 at the defective pixel position read from the memory circuit 23 to perform the normal operation immediately before. The value of the image signal of the pixel is held and replaced and output from the terminal 25.

[0006]

In the conventional device, the memory circuit 23 and the sample hold control circuit 24 must be provided, which causes a problem that the circuit scale becomes large and complicated. Further, since the defective pixel position is different for each solid-state imaging device 10, the defective pixel position must be measured and registered in the memory circuit for each device. If a new defective pixel occurs after this measurement, There was a problem that we could not respond.

The present invention has been made in view of the above points,
The circuit configuration is simple, there is no need to measure defective pixels in advance,
It is an object of the present invention to provide a solid-state imaging device capable of coping with the generation of new defective pixels.

[0008]

A solid-state imaging device according to the present invention sequentially transfers signal charges photoelectrically converted in each pixel of a pixel array in vertical and horizontal directions, and transfers the signal charges transferred in time series to pixels. In the solid-state imaging device that resets each time and accumulates in the charge detection capacitance, converts it into a voltage signal by the output amplifier, and outputs it, compares the signal charge amount transferred in time series with the reference value to detect the defective pixel. A defect detection circuit for preventing the reset signal for resetting the charge detection capacitance when the defective pixel is detected by the detection signal of the defect detection circuit, and holding the signal charge of the pixel immediately before the defective pixel in the charge detection capacitance. And a reset blocking circuit.

[0009]

In the present invention, the transferred signal charge amount is sequentially compared with the reference value to detect a defective pixel, and the defective pixel is prevented from resetting the charge detection capacitance so that the signal charge amount of the pixel immediately before is detected. Since the data is held, the storage circuit, the sample hold control circuit, and the like, which are conventionally required, are unnecessary, and the compensation can be performed by replacing the newly generated defective pixel.

[0010]

1 is a circuit diagram of a first embodiment of the device of the present invention. 5, those parts which are the same as those corresponding parts in FIG. 5 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 1, the final stage 151 of the horizontal transfer CCD 15 is a comparator 30 as a defect detection circuit.
It is connected to the. The comparator 30 is also supplied with a first reference voltage Vref1 from a DC power supply 31.
The comparator 30 performs the comparison operation when the timing output from the final stage 15l of the CCD 15 is instructed by the timing signal supplied from the terminal 32, and when the output charge amount of the final stage 15l is almost 0, the final stage 15l.
Since the potential of is higher than the first reference voltage Vref1, 0 is output, otherwise 1 is generated and held and output until the arrival of the next timing signal. The output signal of the comparator 30 is supplied to the AND circuit 33.

A reset signal and a signal φReset are supplied from the terminal 34 to the AND circuit 33. When the output of the comparator 30 is 0, that is, when the output voltage of the final stage 15l is zero, the AND circuit 33 is a defective pixel. The AND circuit 33 blocks the reset signal. The reset signal output from the AND circuit 33 is supplied to the gate of the reset gate 18.

As described above, in the defective pixel having the output charge amount of zero, the reset signal is blocked and the reset of the charge detection capacitor 17 is stopped, so that the charge of the immediately preceding pixel is charged.
Held in. Therefore, the pixel shown by the broken line in FIG. 2 in which no signal charge is detected is compensated as shown by the solid line by holding the charge of the immediately preceding normal pixel.

In this embodiment, the comparator 30 and the AND circuit 33 are simply provided, and it is not necessary to measure the defective pixel position in advance, and the above compensation operation is started from the time when the defect occurs. .

FIG. 3 shows a circuit diagram of a second embodiment of the device of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 3, the final stage 151 of the horizontal transfer CCD 15 is connected to the defect detection circuit 40. The defect detection circuit 40 has the configuration shown in FIG.
The terminal 41 connected to is connected to each of the comparators 30 and 42. Similar to FIG. 1, the comparator 30 outputs 0 when the output charge amount of the final stage 15l is almost 0,
Otherwise, 1 is output.

The comparator 42 includes a second DC power source 43 and a second
Is supplied with the reference voltage Vref2. Comparator 42
Performs a comparison operation at the timing of the charge output from the final stage 15l of the CCD 15, and outputs 0 because the potential of the final stage 15l is below the second reference voltage Vref2 when the output charge amount of the final stage 15l is almost full scale. However, at other times, 1 is generated and held until the arrival of the next timing signal.

The OR circuit 44 performs an OR operation on the outputs of the comparators 30 and 42 to generate a signal X of 0 and output it from the terminal 45 when the output charge amount of the final stage 15l is a zero or full-scale defective pixel. The output signal Y of the comparator 42 is inverted by the inverter 46 and output from the terminal 47.

Returning to FIG. 3, the defect detection circuit 4 will be described.
The signal X output by 0 is supplied to the AND circuit 33, and the signal Y is supplied to the AND circuit 48. The AND circuit 33 blocks the reset signal when the output charge amount of the final stage 151 is a defective pixel of zero or full scale, and supplies the reset signal to the reset gate 18 when the pixel is a normal pixel. The AND circuit 48 is supplied with the signal Y of 1 when the output charge amount of the final stage 15l is full scale, takes out the reset signal from the terminal 34, and supplies it to the gate of the reset gate 50. The reset gate has a drain and a source connected to the power supply V _DD and the final stage 15l, respectively, and is turned on by a reset signal when a full-scale defective pixel is present, causing the output charge of the final stage 15l to flow to the drain power supply V _DD and zero. Reset to.

As described above, in a defective pixel having an output charge amount of zero or full scale, the reset signal is blocked and the reset of the charge detection capacitor 17 is stopped, so that the charge of the immediately preceding pixel is held in the charge detection capacitor 17. Therefore, the pixel shown by the broken line in FIG. 2 and the pixel in which no signal charge is detected and the full-scale pixel are compensated as shown by the solid line by holding the charges of the immediately preceding normal pixel.

This embodiment also has a simple structure in which the comparators 30 and 43, the OR circuit 44, and the AND circuits 33 and 48 are provided, and it is not necessary to measure the defective pixel position in advance, and the above-mentioned operation is performed from the time when the defect occurs. The compensation operation of is started.

[0020]

As described above, according to the solid-state image pickup device of the present invention, the circuit configuration is simple, it is not necessary to measure defective pixels in advance, and it is possible to cope with the generation of new defective pixels. It is useful.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a device of the present invention.

FIG. 2 is a waveform diagram for explaining the present invention.

FIG. 3 is a circuit diagram of the device of the present invention.

FIG. 4 is a circuit diagram of a defect detection circuit.

FIG. 5 is a circuit diagram of a conventional device.

FIG. 6 is a waveform diagram for explaining a conventional device.

[Explanation of Codes] 11 Pixels 15 Horizontal Transfer CCD 16 Output Adjustment Gate 17 Charge Detection Capacitance 18,50 Reset Gate 19 Output Amplifier 30,42 Comparator 33,48 AND Circuit 40 Defect Detection Circuit 44 OR Circuit

Claims (4)

[Claims] 1. A charge detection capacitance (17) for sequentially transferring signal charges photoelectrically converted in each pixel of a pixel array in vertical and horizontal directions and resetting the signal charges transferred in time series for each pixel. In the solid-state imaging device which stores the signal charge amount in the above, converts it into a voltage signal by the output amplifier (18) and outputs the voltage signal, the defect detection circuit (30) for detecting the defective pixel by comparing the signal charge amount transferred in time series with a reference value , 40), and a reset signal for blocking the reset signal for resetting the charge detection capacitance when the defective pixel is detected by the detection signal of the defect detection circuit and holding the signal charge of the pixel immediately before the defective pixel in the charge detection capacitance. And a blocking circuit (33). 2. The solid-state imaging device according to claim 1, wherein the defect detection circuit (30) detects a defective pixel having a signal charge amount of almost zero. 3. The solid-state imaging device according to claim 1, wherein the defect detection circuit (40) detects a defective pixel having a signal charge amount of almost zero and a full-scale defective pixel. . 4. The solid-state imaging device according to claim 3, further comprising a reset circuit that discards and resets the signal charge transferred when a defective pixel having a full-scale signal charge amount is detected by the output signal of the defect detection circuit. A solid-state image pickup device comprising: