JPH0746406A - Method and device for picture coding - Google Patents

Abstract

PURPOSE:To realize a multi-access/dual access function and a coding processing corresponding to high speed communication and high speed reading with simple configuration and control at a high speed and a buffer memory of a small capacity. CONSTITUTION:Serial picture data received from a picture read section 111 in the unit of lines are converted into parallel data by an S/P conversion section 101 and the data are stored in a memory 110 via a memory control section 109. Then the data are read from the memory 110 based on a line synchronizing signal and coded into a compression code at a compression code generating section 102 based on a parameter 1 or 2 of a parameter storage circuit 103 or 104 selected by a selector 105 and packed by a packing circuit 107 selected by a selector 106 and the result is provided as an output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding method and apparatus, and more particularly to an image coding method and apparatus for coding input image data into a compression code.

[0002]

2. Description of the Related Art In recent years, G3 facsimile machines have rapidly penetrated into companies and have established themselves as OA devices essential for business. Currently, functional expansion and price reduction are progressing,
A full lineup from high end to low end has been developed. In addition, the transmission speed has been dramatically improved, and some of them have exceeded 20 kbps.

Further, in recent years, the service of the ISDN line, which is a digital communication network, has started to replace the conventional telephone line, and G4 facsimiles connecting to the ISDN network are gradually becoming popular. 400d for G4 facsimile
High resolution of pi and high speed communication of 64 kbps are major features. Further, there is a high demand from the user regarding the reading speed, and for example, a model capable of reading 30 sheets of an A4 size document having a resolution of 3.85 mm / line in the sub-scanning direction per minute has been developed. Therefore, by high-speed communication and high-speed reading, so-called quick response facsimile transmission can be realized, which is a very attractive function for the user.

Now, in many of the facsimile machines currently being developed, advanced functions such as multi-access and dual-access, which have not been heretofore developed, can be provided to provide better operability to the user. ing. Here, the multi-access function means ISDN.
In a facsimile connected to a line or the like, this refers to a function such as "transmission is possible during reception" or "reception is possible during transmission." Further, the dual access function refers to a function such as "a transmission reservation can be made during reception" and "a copy or transmission reservation can be made during memory transmission."

[0005]

However, in a facsimile apparatus having such a function and capable of high-speed reading and high-speed communication, it is necessary to perform encoding into a compressed code for a plurality of pages at the same time. In addition to the above, it is required to perform these processes at high speed, which causes the device configuration to be complicated, the control to be complicated, and the device cost to be increased.

The present invention has been made in order to solve the above-mentioned problems, and is capable of performing a coding process corresponding to a multi-access / dual-access function or high-speed communication / high-speed reading with a high-speed and simple configuration / control, and An object of the present invention is to provide an image encoding method and device that can be realized with a small capacity buffer memory.

[0007]

In order to achieve the above object, the structure of the image coding apparatus of the present invention is such that an image coding apparatus for coding input image data into a compression code is input line by line. Storage means for storing image data; first encoding means for encoding the image data stored in the storage means into a compression code in accordance with a first synchronization signal; and image data stored in the storage means Second encoding means for encoding a compressed code in accordance with the second synchronizing signal, and selecting means for selecting either the first or second encoding means.

In order to achieve the above object, the image encoding method of the present invention is a storage step of storing image data input line by line, and a first synchronization signal for storing the image data stored in the storage step. A first encoding step of encoding into a compressed code in accordance with the second encoding step, and a second encoding step of encoding the image data accumulated in the accumulating step into a compressed code in accordance with a second synchronization signal; And a selection step of selecting any one of the two encoding steps.

[0009]

In this structure, the image data input in line units is accumulated, and the accumulated image data is encoded into a compression code according to the first or second synchronization signal.
Alternatively, one of the second encoding means is selected to operate for encoding.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the arrangement of the image coding apparatus according to this embodiment. In the figure, 101 is a serial / parallel (S / P) converter, which converts serially input image data into parallel data. The converted parallel data is accumulated in the memory 110 through the memory control unit 109. The memory control unit 109 includes a DMA controller, a timing control unit, and the like, and writes data sent from various devices to the memory or reads data from the memory in response to memory access requests sent from various devices. Or send it to. 110 is dynamic R
The memory is an AM memory or the like and stores data under the control of the memory control unit 109.

Reference numeral 102 denotes a compressed code generation unit, which converts the raw image data stored in the memory 110 into a memory control unit 109.
Read through and execute the encoding process. The compressed code data generated by the compressed code generation unit 102 is, for example, the CCITT-recommended MMR / MR / MH code, and the code length is indefinite. 1 for some 1 bit
Some are 6-bit. Therefore, the encoded compressed code data is sent to the packing circuit 107 or 108 through the selector 106, packed in units of a positive multiple of bytes, and stored in the memory 110 via the memory control unit 109.

Parameter storage circuits 103 and 104 store necessary parameters in the compressed code generator 102. The parameters include, for example, the number of bits of one line to be encoded and the encoding method. Reference numeral 105 denotes a selector, which selectively outputs the parameter 1 or the parameter 2 stored in the parameter storage circuit 103 or 104 to the compressed code generation unit 102. An image reading unit 111 outputs serial image data to the S / P conversion unit 101.

Next, an outline of the operation of the embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 shows the image data stored in the memory 110. In the figure, two pages of image data are accumulated, and the timing chart of FIG. 3 shows how these are encoded in a time division manner. Here, the SYNC1 signal is a line synchronization signal output from the image reading unit 110. In accordance with this synchronization signal, serial image data is input to the S / P conversion unit 101 and sequentially stored in the image memory 110 like N lines and N + 1 lines. The SYNC2 signal is a line synchronization signal and is generated inside the compressed code generation unit 102.
With the SYNC2 signal, the compressed code generation unit 102 executes the encoding process in the order of N-1, N, N + 1 line by line. In addition, the compressed code generation unit 102 executes the encoding process in the order of M, M + 1, and M + 2 on a line-by-line basis by the SYNC2 signal. The parameters required for the encoding process are the parameter storage circuit 10 according to the encoding process 1 / enable signal or the encoding process 2 / enable signal.
Parameter 1 or parameter 2 of 3, 104 is switched and read. Further, the compressed code generated by the compressed code generation unit 102 is also selected and packed in the packing circuits 107 and 108 by the encoding process 1 / enable signal or the encoding process 2 / enable signal and output.

Next, with reference to the detailed diagrams of the compressed code generation unit 102 shown in FIGS. 4 and 5, the process of switching the encoding process for each line will be described. Incidentally, here, the encoding process 1 is a synchronization signal input from the outside, that is, SYNC1.
It is assumed that the encoding process 2 is activated according to (451), and the encoding process 2 is activated according to a synchronization signal internally generated, that is, SYNC2 (481).

Reference numeral 451 denotes a SYNC1 signal, which is a synchronizing signal input from the image reading section 111. When one pulse of this synchronizing signal is input, it goes through 4 gate means 401.
The 02 up / down counter counts up by one. As a result, the output of the gate means 403 is 45.
2 is turned on, the JK flip-flop 404 is turned on, and 453, that is, the EX1 signal is turned on. This EX1 signal controls the selector circuit 105, enables the parameter 1 of the parameter storage circuit 103, controls the selector 106, and operates the packing process 1 of the packing circuit 107. Reference numeral 473 is a code data bus, and 474 is a code data code length bus. In the packing circuits 107 and 108, 43
The code data of indefinite length is packed according to the code length output from the second encoding processing unit. Encoding processing unit 43
Reference numeral 2 is, for example, a virtual change point detection circuit of the reference line of the compression code encoding device disclosed in Japanese Patent Laid-Open No. 62-31259 and a portion from the coding line change point detection circuit to the packing circuit.

The EX1 signal is also sent to the memory control unit 109 described above, and a coding line which is one line of raw image data to be encoded and a reference line which is raw image data to be referred to at the time of encoding are stored on the memory 110. Request to read from the area stored for encoding processing 1. Similarly, the encoded code data is also requested to be stored in the area allocated for the encoding process 1. The EX1 signal is also input to the D flip-flop 405, and a signal obtained by extracting the first pulse of the EX1 signal is generated by the gate means 454. This signal is passed through the gate means 401 to the up / down counter 4
Count down 02 by one. At the same time, 40
Turn on 409 JK flip-flops and 415 JK flip-flops through 6,408 gate means. The output signal 455 (CDRQ) from this 409 is
It is sent to the memory control unit 109 to request the data of the coding line. Also, the output signal 456 from 415
(RSRQ) is sent to the memory control unit 109 and requests the data of the reference line. 455 CDRQ
In response to the data transmission request of the signal and the RSRQ signal of 456, the memory control unit 109 outputs the CDACK signal of 457 and the RF of 458 at the timing when the data can be read.
Respond to data requests by enabling the ACK signal. JK flip-flop 40 is generated by these signals.
9, 415 are turned off, and at the same time, data is written in the parallel-serial conversion registers 430, 431, respectively.

In this circuit example, the response to the CDRQ signal is R
It is assumed that the priority is higher than the response to the SRQ signal and that the CDACK signal is always responded earlier than the RFACK signal. Therefore, when the data of the reference line is written in the register 431 in response to the RFACK signal, it is assumed that the data of the coding line is written in the register 430. Further, in this circuit example, the data of the coding line and the reference line are written in the registers 430 and 431 in 16-bit units.

Depending on the response of the RFACK signal, J of 420
The K flip-flop turns on. This gives 421
The JK flip-flop is turned on, and the counter 422 becomes the count enable state. When the value of the counter 422 becomes "1", the gate output of 461 is turned on, the JK flip-flops 409 and 415 are turned on again through the gate means of 407 and 408, and the data of the reference line and the coding line are requested. The output of the JK flip-flop 421 becomes a shift signal to the serial-parallel conversion registers 430 and 431, and the data loaded by the output signal of the gate means 426 is serially output from the serial-parallel conversion registers 430 and 431 to the encoding processing unit 432. To be done.

FIG. 6 shows the serial-parallel conversion registers 430 and 43.
1 shows an example of the circuit. 501 and 502 are, for example, LS37
It is an 8-bit register such as 4 and latches data by inputting a pulse signal of 457 or 458.
The latched data 470 is stored in the shift registers 503 and 504 capable of parallel input such as LS299 by the pulse signal output from the gate unit 426. The stored data receives the signal 460, is converted into serial data, and is sent to the encoding processing unit 432.

The carry-up signal 462 of the counter 422 is turned on in 16-bit units, and the counter 425 is incremented by "1". These counters 4
25 and 422 count the number of bits in one line.
Therefore, when the output signal of the gate means 424 is turned on, one line is completed and the JK flip-flop 404 is turned off.

Next, a synchronizing signal (SYNC) generated internally is generated.
2) The encoding process 2 started according to 481 will be described. Reference numeral 480 is an enable signal for the counter 410, which is set by a control unit (not shown). When the signal 480 is in the ON state, the counter 410 counts a predetermined count value, and outputs a carry-up signal, that is, a synchronization signal 481 each time the counter counts up. When the synchronization signal 481 is turned on, the JK flip-flop 411 is turned on. At this time, the output O of the up / down counter 402 becomes O
Whether the gate means 403 for outputting the R signal is on or J
If the K flip-flop 404 is not turned on, the JK flip-flop signal of 413 is turned on through the gate means of 412. That is, if the gate means 416 is on, the gate means 412 causes the JK flip-flop 411.
Will be prohibited. This is a means for preferentially performing the encoding process 1 operated by the line synchronization signal, and when an unprocessed line activated by the line synchronization signal still remains, the line is preferentially processed. It is for doing.

When the JK flip-flop 413 is turned on, the 483, that is, the EX2 signal is turned on. This EX2
The signal controls the selector circuit 105, enables the parameter 2 of the parameter storage circuit 104, controls the selector 106, and operates the packing process 2 of the packing circuit 108. The EX2 signal is shown in FIG.
The coding line, which is one line of raw image data to be encoded, and the reference line, which is the raw image data to be referred to at the time of encoding, are also stored in the memory 110 for the encoding process 2 and are also transmitted to the memory control unit 109 Read from the area. Similarly, the encoded code data is also requested to be stored in the area allocated for the encoding process 1. The EX2 signal is also input to the D flip-flop 414, and the first one pulse of the EX2 signal is extracted by the gate means 475 485.
Signal is generated. This signal is the gate means 406,
Turn on JK flip-flops 409 and 415 through 408.

The signal (CDRQ) of 455 which is the output of the JK flip-flop 409 is sent to the memory control unit 109 to request the data of the coding line. Also,
The signal (RSRQ) of 456 which is the output of the JK flip-flop 415 is sent to the memory control unit 109 and requests the data of the reference line. This CDRQ signal 4
In response to the data transmission request of 55 and the RSRQ signal, the memory control circuit 1-9 enables the CDACK signal 457 and the RFACK 458 signal at the timing when the data can be read and responds to the data request. By these signals, JK flip-flops 409 and 41 are respectively provided.
5 is turned off, and at the same time, data is written in the parallel-serial conversion registers 430 and 431, respectively. Subsequent operations are the same as the above-described operations synchronized with the line synchronization signal, and the JK flip-flop 413 is turned off when the processing for one line is completed.

As described above, the compression code encoding process of different image data is switched line by line depending on the line sync signal and the internal sync signal. Further, timing charts of the above-described operation are shown in FIGS. Next, with reference to FIGS. 9 to 12, an operation of adding the header information to the image information by thinning out the line synchronization signal for a certain line will be described.

FIG. 9 is a diagram showing a state of header information and image data stored in the memory 110. Assuming that the image data is stored in the format as shown in FIG. 10A, if the header information is added to the image area, the image data as shown in FIG. When the header information is stored outside the image area, the image data is as shown in (c) of FIG. For example,
By adding the circuit as shown in FIG. 11 in the preceding stage of the gate means 401 shown in FIGS. 4 and 5, the encoding of image data as shown in FIG. 10B can be realized.

In FIG. 11, reference numeral 601 denotes a counter, which is used to thin out the set first line.
When the signal is counted and the set value is counted up, the carry output is turned on and the JK flip-flop 602 is turned on. As a result, the gate signal of 603 is turned on for the first time, and the SYN signal is passed through the gate means of 604.
The C1 signal can be output as the SYNC1 'signal. When the CUT signal is off, SYNC1 = SYNC1 ′ signal regardless of the signal 602.

FIG. 12 is a flowchart showing a processing procedure for adding the header information shown in FIG. 10B under the control of a microprocessor circuit (not shown). First, in step S101, the header information is expanded in the memory 110 as shown in FIG. 9, and when the expansion is completed (step S1
02), proceeding to step S103, the header information is compressed and coded by the internal synchronization signal. Next, when the compression code encoding of the header information is completed (step S10)
4) Proceed to step S105, set the coding start address (= b), turn on the coding cut signal (CUT = 1) at step S106, and start coding by the line synchronization signal at step S107. When the image reading is started in step S108, the first N lines of the read image data are thinned out, that is, the address b (N +
The compression code encoding is started from the image data of one line).

When the compression code encoding is completed as described above (step S109), the compression code data of the image data as shown in FIG. 10B can be obtained. Further, when the encoding start address = a, the encoding cut signal is set to OFF, and the compression code encoding is performed in the same manner, as shown in FIG.
It is also possible to obtain compressed code data to which header information is added, as in (c) shown in 0.

In this embodiment, a means for converting serial data into parallel data and storing it in the memory, and a compression code encoding for encoding the data read from the memory into a compression code and storing the encoded compression code in the memory. The apparatus has means for starting an encoding process in accordance with a line synchronization signal of image data serially input line by line. By this means, for example, it becomes possible to automatically perform the compression code encoding of the image data input from the reading device.
Further, since it has no line memory, it is easy to absorb the speed.

Also, means for storing the number of unprocessed lines, a means for increasing the number of unprocessed lines by a line synchronization signal, and a means for decreasing the number of unprocessed lines by the end of the coding process for one line. By including, even if there is a case where the encoding process cannot catch up with the image input, line omission can be prevented. Further, by having a means for counting the line synchronization signal, prohibiting the input of the line synchronization signal to the encoding device until the line synchronization signal reaches a certain number or more, and not performing the encoding processing of the certain line, the header information When adding to the read image data, the image data for the number of lines to be added can be automatically deleted.

Further, the image data is read from the memory,
It has a means for encoding into a compressed code and a means for packing the encoded compressed code, and has at least two sets of means for storing encoding parameters and means for packing the compressed code, and switching them in line units. In a device that time-divisionally encodes multiple image data,
An image is read by starting encoding by means of starting the encoding processing according to the line synchronization signal of the image data serially input line by line and by means of starting the encoding processing according to the synchronization signal generated by the counting means. It is possible to realize multiple encoding processes and other encoding processes.

Further, by preferentially processing the means for starting the encoding process in accordance with the line synchronization signal of the image data serially input line by line, the encoding process of the read image which requires immediacy is given priority. It is also possible to reduce the capacity of the buffer memory that stores the read image data. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.

It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0034]

As described above, according to the present invention, the encoding process corresponding to the multi-access / dual-access function and high-speed communication / high-speed reading can be performed at high speed with a simple configuration / control and a small capacity buffer. It can be realized with memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a device configuration in a first embodiment.

FIG. 2 is a diagram showing a state in which image data to be encoded is stored in a memory.

FIG. 3 is a time chart in which compression code encoding is performed by switching in line units.

FIG. 4 is a diagram showing a detailed configuration of a compressed code generation unit in FIG.

5 is a diagram showing a detailed configuration of a compressed code generation unit in FIG.

FIG. 6 is a diagram showing a detailed configuration of the shift register shown in FIGS. 4 and 5;

FIG. 7 is a timing chart showing the operation of FIGS. 4 and 5.

FIG. 8 is a timing chart showing the operation of FIGS. 4 and 5.

FIG. 9 is a diagram showing a state of a memory storing header information and image data.

FIG. 10 is a diagram showing an example of adding header information to a read image.

FIG. 11 is a diagram showing a circuit configuration for thinning out a line synchronization signal.

FIG. 12 is a flowchart showing a processing procedure for adding header information.

[Explanation of symbols]

 101 S / P conversion unit 102 Compressed code generation unit 103 Parameter storage circuit 104 Parameter storage circuit 105 Selector 106 Selector 107 Packing circuit 108 Packing circuit 109 Memory control unit 110 Memory 111 Image reading unit

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Claims (6)

[Claims] 1. An image coding apparatus for coding input image data into a compression code, wherein a storage unit for storing image data input line by line and a first synchronization of the image data stored in the storage unit. First encoding means for encoding a compressed code according to a signal; second encoding means for encoding the image data accumulated in the accumulating means into a compressed code according to a second synchronization signal; An image coding apparatus comprising: a selection unit that selects one of the second coding units. 2. The image coding apparatus according to claim 1, wherein the first coding unit is processed with priority. 3. A packing means for packing the compressed code from said output means, further comprising at least two sets of a packing means and a storage means for storing a coding parameter, and a plurality of them are switched for each line. 2. The image coding apparatus according to claim 1, wherein the image data is encoded in a time division manner. 4. A counting means for counting the number of unprocessed lines is further provided, said counting means being counted up (or down) by a predetermined synchronizing signal, and counted down by the start or end of the encoding by said encoding means. Or up)
The image coding apparatus according to claim 1, wherein 5. A counting means for counting a predetermined synchronization signal is further provided, and until the counting means counts up by a fixed number,
The image coding apparatus according to claim 1, wherein coding by the coding means is controlled. 6. An image encoding method for encoding input image data into a compression code, wherein an accumulating step of accumulating the image data input in line units, and a first synchronization of the image data accumulated in the accumulating step. A first encoding step of encoding a compressed code according to a signal; a second encoding step of encoding the image data accumulated in the accumulating step into a compressed code according to a second synchronization signal; And a selection step of selecting any of the second coding steps.