JPH0746262A - High-speed lan equipment - Google Patents

Abstract

PURPOSE:To suppress a frequency of a communication line to be low and to attain the system of multiplexing the token passing system by using each pair of UTP cables for reception and transmission private lines and a communication line for both transmission and reception. CONSTITUTION:One pair of 4 pairs of unshielded twisted pair cables used for communication lines of a communication equipment is used for a reception exclusive line RXD, one pair is used for a transmission exclusive line TXd, and the remaining two pairs are used for transmission reception communication lines SC0, SCH1. Furthermore, a transmission line 13 sends a signal through the three pairs of the reception exclusive line RXD and the transmission reception communication lines SCH0, SCH1 simultaneously in parallel. Furthermore, the reception circuit 1 receives signals simultaneously through the three pairs of the reception exclusive line RXD and the transmission reception communication lines SCH0, SCH1 in parallel. By this constitution, a communication speed per each signal line is reduced and the communication data are sent at a high speed entirely. Thus, the frequency of the communication lines is set low and the high-speed LAN equipment employing the system multiplexing the token passing system with high communication efficiency is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed LAN device capable of increasing the communication speed of a LAN.

[0002]

2. Description of the Related Art In recent years, a local area network (LAN) mainly composed of personal computers has been remarkably popularized, and a LAN device is required to have a high speed in response to the improvement of the processing capability of the personal computer and the realization of multimedia. .

Currently, 10BASE-using 4 pairs of unshielded paired binding wires (UTP cables) as main LAN devices.
There is a LAN called T standard Ethernet. In this method, the speed is 10 Mbps, and the communication method is a carrier sense multiple access method with collision detection (CSMA).
/ CD: carrier sense multiple access with collisi
on detection) is used.

[0004]

However, the current demand for higher speed requires a communication speed of 100 Mbps or more, and a method that can use the already laid 10BASE-T standard 4-pair UTP cable as it is. Has been.

By the way, the communication speed of the 10BASE-T standard Ethernet LAN is 100 Mbp as it is.
Although it is technically considered possible to raise to s,
If only the communication speed is increased by the same method, there is a fact that it is extremely difficult to prevent and prevent the problem of unnecessary radiant noise, which is a radio interference. Also, the communication method CSMA
/ CD has a poor communication efficiency and has a practical problem in a LAN having a communication speed of 100 Mbps.

In order to speed up the LAN device, it is necessary to provide both a method for speeding up the communication speed and a method for speeding up the communication procedure (protocol). If only one of them is dealt with, the effect on the speedup of the entire system becomes extremely small.

A method has been proposed in which four pairs of UTP cables are collectively used and switched by using all lines for transmission or reception. According to this method, UTP
25 Mbps, which is 1/4 of 100 Mbps per cable pair
Communication is possible at a speed as low as ps. However, when all four pairs are used, only half-duplex communication can be performed (one-way communication from one to the other in one period is called half-duplex communication). The efficiency deteriorates extremely in the communication procedure. There was a problem.

The present invention can deal with such a problem, can suppress the frequency of the communication path to a low frequency, and can also use CSMA / CD.
It is an object of the present invention to provide a high-speed LAN device using a method of multiplexing a token passing method, which has better communication efficiency than the method.

[0009]

In order to achieve the above object, a high speed LAN device of the present invention is a local area network (LAN) for performing communication between a plurality of communication devices, and is used as a communication line of the communication device. A pair of UTP cables are used, one pair is a reception dedicated line (RxD), one pair is a transmission dedicated line (TxD), and the remaining two pairs are transmission / reception communication lines (SCH ₀ , SCH ₁ ). It is characterized by being done.

Further, a receiving circuit (1) to which the reception exclusive line (RxD) and the transmission / reception communication lines (SCH ₀ , SCH ₁ ) are connected, the transmission exclusive line (TxD) and the transmission / reception communication. And a transmission circuit (13) to which the lines (SCH ₀ , SCH ₁ ) are connected, and a reception dedicated line (RxD)
The transmission line (TxD) and the transmission line (TxD) are always full-duplex communication systems, and the reception circuit (1) and the transmission circuit (13) transmit communication data in parallel by three pairs of connected communication lines. It may be configured to be able to send and receive at high speed.

Further, the communication frame composed of a predetermined bit string constituting the communication content between the communication devices is provided with a frame type section (FB) indicating that the communication content is either data or a command. A plurality of buffers corresponding to the data and commands indicated by the frame type section (FB) are independently provided, and the receiving circuit (1)
In the received frame identification circuit (3) for identifying the content of the data or command indicated by the frame classification section (FB).
6) may be provided.

Further, two FIFO memories (40, 42) respectively connected to the receiving circuit (1) and the transmitting circuit (13) and the memory spaces of the two FIFO memories are connected or separated from each other. Selectors (44a-4
4c) and a FIFO coupling circuit (46), and at the time of transmitting communication data from the transmission circuit (13), by switching between the selector and the FIFO coupling circuit, the respective FIFOs are switched.
O memory is separated for sending and receiving respectively, while
When the communication data is received by the receiving circuit (1), the two FIFO memories may be connected by switching the selector so that the double capacity can be freely received.

Further, the reception exclusive line (RxD) and the transmission / reception communication line (SC) in the reception circuit (1)
H ₀ and SCH ₁ ) include a peak hold circuit (25) that detects and holds the peak value of the received signal (RxD) and an inverting circuit (2) that inverts the output of the peak hold circuit.
6), and attenuation circuits (27a, 27b) for attenuating the output values of the peak hold circuit and the inverting circuit by a predetermined amount, respectively.
And a comparator (22, 23) for outputting the reception data (RD) corresponding to the output value of the reception signal (RxD) by using the output of the attenuation circuit (27a, 27b) as a threshold. You can also do it.

Further, while using the NRZ code as a communication signal, the transmission data (SD) is sent to the transmission circuit (13).
Phase delay circuits (55a to 55c) for phase delaying
The transmission data (SD) and the signal of the phase delay circuit are input, and the current booster circuits (57a, 57b, 58a ...
By outputting to the transmission dedicated line (TxD) and the transmission / reception communication lines (SCH ₀ , SCH ₁ ) via 58d), the pulse transformers (21a to 21d) for insulating between devices can be driven. .

[0015]

According to the above configuration, the communication line of the communication device is 4
A pair of UTP cables are used, of which the receiving circuit (1)
Received signals are received in parallel on the three pairs of communication lines by the reception-only line (RxD) and the transmission / reception communication lines (SCH ₀ , SCH ₁ ) connected to each other. Also, the transmission circuit (13)
The transmission signal is received in parallel by the three pairs of communication lines by the transmission-only line (TxD) and the transmission / reception communication lines (SCH ₀ , SCH ₁ ) connected to. As a result, the communication speed of each signal line can be reduced, and as a result, the communication signal can be communicated at high speed as a whole, and the reception dedicated line (Rx
D) and transmission-only line (TxD) are always available for communication 2
A double communication system can be adopted, and communication efficiency can be improved.
Furthermore, since the communication signal uses the NRZ code, the communication frequency can be set to 1/2 of the communication speed of each communication signal, and unnecessary radiation noise can be reduced.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION In the LAN device of the present invention, in order to speed up the LAN device, the communication speed and the speeding up of the communication procedure are simultaneously provided. First, the speeding up of communication speed will be described. In the present invention, the maximum communication speed is 16.7.
10 BAS currently used at the frequency of MHz
An E-T standard 4-pair UTP cable is used. The present invention uses these to achieve 100 Mbps. Therefore,
In the present invention, the communication speed can be increased without replacing the four pairs of UTP cables that have been conventionally laid.

FIG. 1 is a block diagram showing the overall construction of a high-speed LAN device according to the present invention. An outline of the diagram will be explained with reference to RxD, SCH ₀ , SCH ₁ , and TxD in the figure.
Is equivalent to one pair of 10BASE-T standard UTP cables. In the present invention, of the four pairs of UTP cables, the reception line RxD is exclusively used for reception and is connected to the reception circuit 1. In addition, SCH ₀ , S for bidirectional reception and transmission
It is connected to the receiving circuit 1 and the transmitting circuit 13 by using CH ₁ . Then, it is connected to the transmission circuit 13 by using the transmission line TxD exclusively for transmission.

Since this apparatus sends data at a high speed, TxD and SCH ₀ , S are sent from the sending circuit 13 at the time of sending.
Transmit 3 pairs of CH ₁ in parallel. Further, in the case of reception, the reception circuit 1 is made to receive three pairs of RxD and SCH ₀ , SCH ₁ in parallel at the same time. With this configuration, each U
The TP cable can perform 100 Mbps transmission at a rate of 33.4 Mbps, which is 1/3 of 100 Mbps per pair. Further, according to the present invention, the transmission line and the reception line, which are TxD and RxD, are always fixed and arranged to enable full-duplex communication, that is, to perform reception while transmitting. Is good.

Next, in the present invention, the NRZ code is used for coding the communication data. The NRZ code is a method of allocating a high level (or High) when data 1 and a low level (or Low) when data 0, and is 10 (or 0).
Since 1 cycle is formed by 2 bits of 1), the frequency can be halved of the baud rate. Therefore, the communication frequency is 1/2 of the communication speed of 33.4 Mbps.
Can be set to 16.7 MHz.

By the way, in the connection using the UTP cable, it is general to intervene with a pulse transformer in order to insulate the devices from each other and prevent the devices from being destroyed. However, the NRZ code used in this device cannot perform insulation in the pulse transformer. (The pulse transformer can only pass AC waves. When 1 or 0 continues in the NRZ code, it is regarded as DC and cannot pass through the pulse transformer.)

Therefore, in the present invention, as shown in the transmission circuit 13 of FIG. 6, one of the transmission data SD is connected to one of the pulse transformers through the current booster circuit, and the other one of the transmission data sd is connected to the phase transmission circuit 55a. Similarly, after delaying the phase through 55c, the current booster circuit 57a
The pulse transformers 21b to 21d are connected to one side of the pulse transformers 21b to 21d. As a result, as shown in the transmission / reception waveform of FIG. 7, only the data change point can be sent, and the pulse transformer can be driven.

Next, speeding up of the communication procedure will be described.
FIG. 2 is a diagram showing the structure of a communication frame. As shown in the figure, a uniquely determined bit code string (for example, 5
0 Bit) is a frame. The chunk of bits in this frame is called a token in the present invention. Start bit S indicating the start as a frame structure
It has a configuration in which there is a bit string with a meaning sandwiched between B and a stop bit EB indicating the end (similar to RS232C). Of course, start bit SB and stop bit E
B does not need to be defined to be limited to 1 bit, for example,
The start bit SB may define a 5-bit continuous code like 11111.

According to the frame structure of the present invention, the bits (frame type portion F) in which the frame type is distinguished are included in the frame.
B) is provided to define the types of tokens for multiplexing. The frame type part FB is roughly divided into data and commands. For example, the bit is "1" for data and the bit "0" for a command.
In the device, the type of the frame type portion is judged, and the data portion DB in the frame similarly sent is stored at the time of reception or becomes an instruction of some kind.

The overall structure of this apparatus will be described in detail below with reference to FIG. The received frame is input to the receiving circuit 1 and identified. Therefore, the received frame (token) is stored in the recognized buffer or memory prepared according to its type. In the receiving circuit 1, a number on the LAN is set by the address setting circuit 2.

In one embodiment of the present invention, the token is
In order to improve communication efficiency, it has a total of five types of tokens defined as data and commands. A buffer corresponding to each of these tokens is provided. First, the token defined as data is stored in the transmission / reception FIFO memory 3.

Further, the token defined as a command is further classified and recognized in the present embodiment into four types of a reception command, a reception port, an internal status transmission trigger and a transmission port transmission trigger.

The received command is stored in the received command buffer 5 and generates an interrupt request signal S1 for the CPU. The reception port is stored in the reception port buffer 7 and is used to generate an output port signal S2 and to display, for example, a lamp.

The internal status transmission trigger is output to the internal status buffer 9. By the input of the internal status transmission trigger, the contents stored in the internal status buffer 9 are output as the signal S3. The internal status buffer 9 has a reception error display signal S7 from the reception circuit 1 and a transmission / reception FIFO memory 3 to FIFO.
The O state display signal S8 is stored. The transmission port transmission trigger is input to the transmission port buffer 11. The input port signal S5 which is the state of the input port is stored in the transmission port buffer 11, and the stored contents are output as the signal S6 by the transmission port transmission trigger.

According to the investigation by the inventor, in the operations belonging to these commands, the information amount of data to be communicated is smaller than that of a token as data. This allows
The command token ~ is operated using only two pairs of RxD and TxD.

On the other hand, since the token as data has a large amount of information, the speed is increased by using 3 pairs. Figure 3
FIG. 3 is a block diagram showing an internal configuration of the receiving circuit 1. Receiving circuit 1 uses RxD, SC among UTP cables.
Reception input sections 20a, 20b, 20c having the same configuration are provided at the three ends of H ₀ and SCH ₁ , respectively. Explaining the reception input unit 20a, two comparators 22 and 23 that sense a level in the + direction and a level that senses in the-direction are transmitted through a pulse transformer 21a that receives RxD.
Connected to.

Further, the peak hold circuit 25, the inverting circuit 26 and the attenuation circuits 27a and 27b automatically adjust the threshold value of the detection level of each of the comparators 22 and 23. The attenuation amounts of the attenuation circuits 27a and 27b are the same as those of the CMO that constitutes the circuit
Background noise varies depending on each element such as S and TTL and the line state. Therefore, if the attenuation amount is set too high, the probability of detecting data decreases.

Therefore, the attenuation amount of each of the attenuation circuits 27a and 27b is a value that stabilizes for each device, and the attenuation value is normally 1/2.
It has been confirmed by experiments by the inventor that 1/3 is suitable. The circuits from the peak hold circuit 25 to the attenuation circuits 27a and 27b are composed of three reception input units 20a.
20c to 20c may be commonly connected in a single configuration.
Further, the attenuation circuits 27a and 27b may be commonly provided.

The flip-flop 29 connected through the comparators 22 and 23 performs RS for performing set and reset operations.
It consists of flip-flops. This flip-flop 29 is set by the detection of the comparator 22 in the + direction, that is, the RD signal becomes 1 (or High), and reset by the detection of the comparator 23 in the-direction, that is, the RD signal becomes 0 (or Low). Become. The manner of operation from the reception data RxD to RD is shown in the transmission / reception waveform of FIG.

The reception clock reproduction circuit 30 reproduces the reception clock RCLK from the RD signal. For this reason,
A pulse generation circuit and a phase synchronization circuit are provided in the reception clock recovery circuit 30. The reception frame detection circuit 32 recognizes the RD signal, recognizes the start bit and the stop bit in synchronization with the reception clock RCLK, and detects the reception frame detection signal S1 of the valid period of the reception frame.
0 is output.

A part of the outputs of the reception clock reproduction circuit 30 and the reception frame detection circuit 32 is input to the shift registers 34a to 34c via the AND circuit 31 as a trigger. This trigger is the receive clock RCLK. As a result, while the reception frame detection signal S10 is valid, the shift register 34a receives the reception data RD having a predetermined bit length.
Are taken in and the result is output to the reception data bus RDB.

The output of the reception frame detection circuit 32 is input to the reception frame identification circuit 36 as a trigger, and the reception frame identification circuit 36 determines the types of tokens on the reception data bus RDB. This reception frame identification circuit 3
Reference numeral 6 denotes a reception FIFO write signal S12, a reception command write signal S13, a reception port write signal S14, an internal status transmission trigger S15, which correspond to each of the tokens, in synchronization with the end of the reception frame detection signal S10. Any one of the transmission port transmission triggers S16 is output.

The reception input units 20b and 20c of the SCH ₀ and SCH ₁ and the shift registers 34b and 3 of the rear stage are provided.
4c is provided, and the received data RD having a predetermined bit length to be received are sequentially output to the received data bus RDB. The state of each signal of the receiving circuit 1 described above is shown in the reception timing chart of FIG.

Next, FIG. 5 is a diagram showing the structure of the transmission / reception FIFO memory 3, which stores tokens as data. The FIFO memory 3 has two FIFOs 1 (40) and 2 (42). These FIFO1 and FIFO2 can form a memory area connected or combined by selectors 44a, 44b, 44c, and
The FIFO coupling circuit 46 causes the FIFO1 and the FIFO2 to
The FIFO operation of is controlled.

The reception data bus RDB is the selector 44a.
Of the FIFO2 and the output D of the FIFO2 is connected to the output Y. The output Q of the FIFO2 is output to the CPU data bus CPUDB. The CPU data bus C
A part of PUDB is connected to the input A of the selector 44b, and the input D of the FIFO1 is connected to the output Y. FI
The output Q of FO1 is connected to the input A of the selector 44c and is also input to the FIFO coupling circuit 46.

The output of the FIFO coupling circuit 46 is connected to the input B of the selector 44a. Also, the reception data bus R
A part of DB is connected to the input B of the selector 44b.
Further, a part of the CPU data bus CPUDB is connected to the input B of the selector 44c.

The output Y of the selector 44c is provided with a transmission 1-frame buffer 47, which outputs the transmission data SD on the transmission data bus SDB for each frame.

The connection / separation operation of the FIFOs 1 and 2 is performed by C
It is controlled by the memory configuration selection signal S11 input from PU. The memory configuration selection signal S11 is a binary signal
When it is 0 "(or Low), each selector 44a-4
4c is connected to the output Y by switching the input A. As a result, the FIFO 2 is used as a reception FIFO memory that stores the reception data RD from the reception data bus RDB. FIFO1 is a CPU data bus CPU
It is used as a transmission FIFO memory for storing transmission data SD from the DB.

Further, the memory configuration selection signal S11 is set to "1".
(Or High), the selectors 44a to 44c
Is connected to the output Y by switching the input B. This allows
FIFO1 and FIFO2 are connected and receive data bus RD
The reception data RD of B is stored in the FIFOs 1 and 2. Both of the FIFOs 1 and 2 at this time are used as a reception FIFO memory and can receive data having a capacity double that of the FIFO reception memory as compared with the case of separation.

Thus, when receiving the reception data RD, the FI is received.
When FO1 and FO2 are connected, the transmitting side is FIFO
The data for the capacity of 2 is transmitted, and the CPU on the receiving side
While reading the data of O2, FIFO1
Since it is possible to continuously send data for the capacity of, it is possible to continuously send data on the communication path without interruption.

Further, the receiving side can perform full-duplex communication by transmission using TxD even during reception, so that the FIFO2
By sending a token as a command at the end of reading of the data of No. 2 to the sending side, the sending side has finished sending the data of the capacity of FIFO 1, and by checking the reading end of this FIFO 2, FIF
Data of O2 capacity can be sent.

The FIFO memories 40 and 42 are the selector 4
4a to 44c and the FIFO coupling circuit 46 have a larger circuit scale, so that the FIFO configuration of the present device can be compared to the conventional method using a FIFO memory for transmission and a FIFO memory having a double capacity for reception. According to this, there is an advantage that the circuit scale for the FIFO memory can be reduced to 2/3.

Next, FIG. 6 is a block diagram showing the structure of the transmission circuit 13. The transmission circuit 13 is provided with a transmission request arbitration circuit 51. In this transmission request arbitration circuit 51,
The transmission request signal S17 from the transmission FIFO memory 3, which is a factor of the transmission request, the transmission request signal S18 of the internal status from the internal status buffer 9, and the transmission port transmission request signal S19 from the transmission port buffer 11 are input. The transmission request arbitration circuit 51 adjusts the requests when there is a request for each signal at the same time, returns an ACK signal as an answer to the one that received the request, and sends a command signal for clock generation to the transmission clock generation circuit 52. Output.

A transmission clock generation circuit 52 which receives a command
Transmits the transmission clock SCLK to the shift registers 53a-5
3c and the phase delay circuits 55a to 55c. As a result, the transmission data SD stored in the shift registers 53a to 53c passes through the current booster circuits 57a to 58d and the pulse transformers 21b to 21d and then the communication line Tx.
D, SCH ₀ , and SCH ₁ are output in predetermined bit lengths.

The current booster circuits 58a to 58d corresponding to the bidirectional lines SCH ₀ and SCH ₁ in the figure are provided with a function for switching the output to a high impedance. Then, the transmission request arbitration circuit 51 outputs the signal CBUFEN1 to the current booster circuits 58a to 58d to control the output request of the FIFO memory 3 so that the transmission is possible only when the transmission request is transmitted.

That is, the bidirectional lines of SCH ₀ and SCH ₁ and the pulse transformers 21b and 21c are the same as those of the receiving circuit 1 and are commonly used. Since this signal is used for bidirectional communication, the transmission period Other than that, it is based on the fact that if the high impedance is not maintained, it becomes an obstacle during the receiving operation. The operation timing of the transmission circuit 13 is shown in the time chart of FIG. Further, in the figure, SCH ₀ and SCH ₁ are described as being held at a high impedance level (not “1” or “0”) except during data transmission.

An example of a concrete communication procedure of the apparatus described above is shown in the data communication procedure diagram of FIG. LA
As a main form of N, a client-server type in which a personal computer called a client and a personal computer terminal on the user side are connected to a personal computer that manages the whole called a server is generally used, and therefore this type will be used for description. .

In the initialization of both the server and the client, the transmission / reception FIFO memory is set separately. Further, both the server and the client perform address setting by the address setting circuit 2 shown in FIG.
The address on the AN) is set to be unique. After initialization, the server will
An operation called polling for checking whether a communication request is issued is performed.

In the present invention, a token for a transmission port transmission trigger is issued to a target client. The client of the transmission request sets a certain input port to a level indicating that there is a request, and the server judges the token of the reception port returned by the transmission port transmission request signal S19 issued by the server, Determine if there is a client request. If there is no request, check the next client in the same way. If a request is found during inspection, the token of the received command indicating that transmission is possible is sent to the client.

Since some communication requests request transmission from the server and some request transmission from the client, this difference is made by defining the bit of the input port. The figure shows the case of a transmission request from a client. The server changes the reception FIFO into a configuration in which the FIFOs 1 and 2 are connected in the same manner (or before) as the notification of the transmission permission to the client.

When the client receives the notification that transmission is possible, the client transmits the data for the capacity of the FIFO2 and subsequently issues the token of the internal status transmission trigger for transmitting the internal status of the server. The contents of the internal status of the returned server are inspected, and if there is no reception error, the notification of sending the data of FIFO2 is sent using the token of the receiving command, and then the data of the capacity of FIFO1 is sent continuously. If there is an error in the result of the internal status, it is notified that there is an error in the data of the FIFO2 capacity transmitted earlier, the token of the reception command is used, and the same data is retransmitted. The same procedure is repeated, and when the data to be transmitted is completed, the communication request bit of the input port is returned to no request, and the data transmission completion notification is sent to the server using the token of the received command.

[0056]

According to the first aspect of the present invention, four pairs of general-purpose UTP cables are used, two cables are used for both transmission and reception, and one transmission and reception are carried out one by one. It is possible to reduce the communication speed per one transmission signal and reception signal using three communication lines, respectively, and as a result, it is possible to increase the total communication speed. Further, the speedup can be achieved without replacing the UTP cable which has been conventionally laid.

According to the second aspect, the transmission signal and the reception signal are input and output via the transmission circuit and the reception circuit, respectively.
And the receiving circuit has a dedicated receiving line, and the transmitting circuit has
Since the transmission dedicated line is connected, full-duplex communication capable of always communicating between LAN devices can be performed. Thereby, the reception during the transmission while achieving the speedup of the communication speed,
Further, it is possible to perform transmission while receiving and improve communication efficiency.

According to the third aspect of the present invention, the frame type portion indicating the data or the command is provided in the communication frame forming the communication signal, and the content can be identified by the received frame identifying circuit. Further, since a plurality of buffers are provided independently corresponding to data and commands, the communication frame reception efficiency and the response to various commands can be simplified and made more efficient. Further, since many kinds of communication frames (tokens) can be provided, so-called multiplexing can be performed in which a plurality of tokens can be simultaneously output on the line.

According to the fourth aspect of the present invention, the receiving circuit and the transmitting circuit can be connected or separated from each other in a memory space.
The FIFO memory is provided and the selector is used for switching. Especially, when the reception signal is received, two FIFOs are used.
Since the IFO memory is connected and the double capacity can be received freely, there is no need to wait for communication of communication signals due to lack of memory capacity on the receiving side, and communication can be made efficient while achieving the speedup.

According to the present invention, since the receiving circuit is provided with the peak hold circuit for judging the receiving level of the received signal, the attenuating circuit, and the comparator, the noise level and the LAN device are connected to each other. The optimum receiving level according to the input / output level of can be automatically set, the occurrence of communication errors can be prevented, and stable communication can be performed.

According to the sixth aspect, the NRZ is used as the communication signal.
Although a code is used, a signal obtained by delaying the original signal and a half phase of the transmission clock by the phase delay circuit can be output via the pulse transformer.

According to claim 7, the communication line for both transmission and reception is
Although connected to both the receiving circuit and the transmitting circuit, the current booster circuit provided in the communication line for both transmission and reception is in a high impedance state during a period other than the period during which the transmission data is output. Can prevent the obstacles.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a high-speed LAN device according to the present invention.

FIG. 2 is a diagram showing a configuration of a communication frame.

FIG. 3 is a block diagram showing an internal configuration of a receiving circuit.

FIG. 4 is a diagram showing an operation timing of a receiving circuit.

FIG. 5 is a diagram showing a configuration of a transmission / reception FIFO memory.

FIG. 6 is a block diagram showing a configuration of a transmission circuit 13.

FIG. 7 is a diagram showing a transmission / reception waveform.

FIG. 8 is a diagram showing an operation timing of a transmission circuit.

FIG. 9 is a diagram showing a data communication procedure of the present apparatus.

[Explanation of symbols]

1 ... Reception circuit, 3 ... Transmission / reception FIFO memory, 5 ... Reception command buffer, 7 ... Reception port buffer, 9 ... Internal status buffer, 11 ... Transmission port buffer, 13 ...
Transmission circuit, 21a to 21d ... Pulse transformer, 22, 2
3 ... Comparator, 25 ... Peak hold circuit, 26 ... Inversion circuit, 27a, 27b ... Attenuation circuit, 36 ... Received frame identification circuit, 40 ... FIFO1, 42 ... FIFO2, 44a
-44c ... Selector, 51 ... Transmission request arbitration circuit, 55a
-55c ... Phase delay circuits 57a, 57b, 58a-5
8d ... Current booster circuit, SD ... Transmission data, RD ...
Received data, RxD ... Received signal (receive exclusive line), TxD
... transmission signal (transmission-only line), SCH ₀ , SCH ₁ ... transmission / reception communication line, FB ... frame classification section.

Claims (7)

[Claims] 1. In a local area network (LAN) for performing communication between a plurality of communication devices, four pairs of UTP cables are used as communication lines of the communication devices, and one pair is a dedicated reception line (RxD). High-speed LA in which one pair is a transmission-only line (TxD) and the remaining two pairs are transmission / reception communication lines (SCH ₀ , SCH ₁ ).
N device. 2. A receiving circuit (1) to which the reception exclusive line (RxD) and the communication lines for both transmission and reception (SCH ₀ , SCH ₁ ) are connected, and the transmission dedicated line (TxD) and communication for both transmission and reception. Transmission circuit (13) to which lines (SCH ₀ , SCH ₁ ) are connected
And a dedicated dedicated line (RxD) and a dedicated transmission line (TxD) are always communicable, and the receiving circuit (1) and the transmitting circuit (13) are connected to each other.
2. A high-speed LAN device according to claim 1, wherein communication data can be transmitted and received in parallel at a high speed by a pair of communication lines. 3. A frame type section (FB) indicating that the communication content is either data or a command is provided in the communication frame composed of a predetermined bit string that constitutes the communication content between the communication devices, A plurality of buffers corresponding to the data and commands indicated by the frame classification unit (FB) are independently provided, and the reception circuit (1) includes the frame classification unit (FB).
The high-speed LAN device according to claim 2, further comprising a reception frame identification circuit (36) for identifying the content of the data or command indicated by. 4. The receiving circuit (1) and the transmitting circuit (1)
2) two FIFO memories (4
0, 42) and selectors (44a to 44c) and FIFOs for connecting or separating the memory spaces of the two FIFO memories.
And a coupling circuit (46). When transmitting communication data from the transmission circuit (13), the respective FIFO memories are separated for transmission and reception by switching between the selector and the FIFO coupling circuit. When receiving the communication data by the receiving circuit (1),
3. The high-speed LAN device according to claim 2, wherein the two FIFO memories are connected by switching the selector, and a double capacity can be received. 5. The reception dedicated line (RxD) and the transmission / reception communication line (SC) in the reception circuit (1).
H ₀ and SCH ₁ ) include a peak hold circuit (25) that detects and holds the peak value of the received signal (RxD) and an inverting circuit (2) that inverts the output of the peak hold circuit.
6), an attenuator circuit (27a, 27b) for attenuating the output values of the peak hold circuit and the inverting circuit by a predetermined amount respectively, and an output of the received signal (RxD) with the output of the attenuator circuit (27a, 27b) as a threshold value. Received data (R
The high-speed LAN device according to claim 2, further comprising a comparator (22, 23) for outputting D). 6. An NRZ code is used as a communication signal, and the transmission circuit (13) includes phase delay circuits (55a to 55c) for delaying the phase of the transmission data (SD), the transmission data (SD) and the phase delay. The signal of the circuit is input, and the pulse transformers (21a to 21d) for outputting to the transmission dedicated line (TxD) and the communication lines for both transmission and reception (SCH ₀ , SCH ₁ ) and for performing insulation between the devices are provided. The high-speed LAN device according to claim 2, which is provided. 7. A communication line for both transmission and reception (SCH ₀ , SC
H ₁ ) is connected to both the receiving circuit (1) and the transmitting circuit (13), and is output to the communication lines (SCH ₀ , SCH ₁ ) for both transmission and reception except during the output period of the transmission data (SD). 7. The high-speed LAN device according to claim 2 or 6, further comprising current booster circuits (58a to 58d) which can be made to have a high impedance by inputting a signal (CBUFEN1) to be supplied.