JPH0746215A - Communication method for pwm data - Google Patents

Abstract

PURPOSE:To realize the excellent communication performance from the standpoint of the utilizing efficiency of a signal line and a CPU input output port, a data transmission efficiency and a communication speed by applying pulse width modulation to plural data, sending the modulated data serially and allowing a receiver side to send two pulses as a pair periodically. CONSTITUTION:A sender side CPU 1 decides a pulse width of a transmission pulse and sets a leading (ON) time A and a trailing (OFF) time B of a 1st pulse in the decided transmission pulse to a timer match output port P10 and sets a leading (ON) time C and a trailing (OFF) time D of a 2nd pulse to the timer coincidence output port P10. Two 1st and 2nd data are subjected to pulse width modulation and the modulated data are sent serially via a signal line 3. A receiver side CPU 2 executes the reception processing of the signal received from an edge interrupt port P20. In the transmission of the 1st and 2nd data, the 1st data are allocated to a time from the ON timing to the ON timing of the two pulses and the 2nd data are allocated to a time from the OFF timing to the OFF timing of the two pulses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a plurality of CPUs.
In a multi-CPU system in which a (central processing unit) operates in parallel, a method of communicating PWM (pulse width modulation) data transmitted and received between the CPUs, and in particular, a plurality of P
The present invention relates to the implementation of a data communication method that realizes efficient transmission and reception of PWM data when serially transmitting WM data and separating and demodulating the data on the receiving side.

[0002]

2. Description of the Related Art An example of the multi-CPU system is an electronic control system for automobiles. That is, in this electronic control system, a plurality of control devices such as an engine control device and a transmission control device are used to control different CPs.
The U is mounted, and data is transmitted and received between a plurality of CPUs mounted on the U, while electronically controlling each control target such as an engine and a transmission in a complex manner. Incidentally, the data transmitted and received between these CPUs is data indicating the throttle opening at each time transmitted from the engine control device to the transmission control device, or conversely transmitted from the transmission control device to the engine control device. There is data indicating the amount of retardation to be performed.

By the way, in order to exchange data between these CPUs, PWM communication is generally used in which the content of the data is pulse-width modulated for communication. However, since this PWM communication basically requires as many signal lines and input / output ports as the number of types of data to be exchanged, from the viewpoint of the usage efficiency of these signal lines and input / output ports. It's hard to say that this is the preferred communication method. Therefore, in recent years, for example, Japanese Patent Laid-Open No. 3-151
As seen in Japanese Patent Publication No. 735, a communication system has been adopted in which a plurality of types of data can be serially transmitted through a single signal line by using a header pulse for identifying the type of data. .

That is, in this communication system, as shown in FIG. 15, in the case of serially transmitting three types of data such as A, B, and C, the first half of the period (T) is used for each type A of the data. , B, and C, which are header data HA, HB, and HC, are sent first, and the actual data D is transmitted through one cycle (T) of the latter half.
A, DB, and DC are sent respectively. At this time, as the pulse widths of the header pulses HA, HB, and HC, unique values are preliminarily agreed between the transmitting side and the receiving side, and the receiving side receives the respective header pulses. By identifying the pulse widths of HA, HB, and HC, it is possible to determine the type of each data that is sent accompanying it.

[0005]

As described above, according to the above communication method using the header pulse, since a plurality of types of data can be serially transmitted through only one signal line, the use efficiency of the signal line and the input / output port is called. In terms of points, although it is certainly a meaningful data communication method,
On the other hand, two cycles (T +
This is also a communication method that requires time T), which still leaves a big problem in terms of data transmission efficiency or communication speed.

The present invention has been made in view of such circumstances, and realizes excellent communication performance in terms of not only the use efficiency of signal lines and CPU input / output ports but also data transmission efficiency or communication speed. It is an object to provide a PWM data communication method.

[0007]

In order to achieve these objects, the present invention provides a PWM data communication method in which a plurality of data are pulse-width modulated and serially transmitted, and the receiving side separates and demodulates the data. The first data is assigned to the time from the on timing of one pulse to the on timing, the second data is assigned to the time from the off timing of the two pulses to the off timing, and these two pulses are periodically transmitted as a set. To do so.

[0008]

For example, assuming that the two pulses in the above set are respectively regarded as a header pulse and a data pulse in the conventional communication method using the header pulse, this method allows only one data in the conventional communication method. At the time when the data could not be sent, the first and second data are sent. Therefore, it is possible to transmit at least two times the communication speed of the first and second at least two data, which are assumed to be ordered with respect to each other, as compared with the above-described conventional communication method.

If the cycle time T (transmission cycle time of each of the header pulse and the data pulse) defined in the above-mentioned conventional communication system is taken as the transmission cycle time of the above-mentioned two pulse sets, they are mutually ordered as in the above case. It is assumed that the first and second at least two data are assumed to be four times faster than the conventional one, and even when either one of the first and second data is used as a header, the communication speed is twice as fast as the conventional one. It becomes possible to transmit this.

As described above, in addition to the case where each first or second data transmitted cyclically is used as a header for identifying the type of the corresponding second or first data, three or more types are added. This is also true for the data of 1
Serial transmission is possible through one signal line.

If the pulse width of the pulse that is turned on first of the two pulses of the above set is T1 and the pulse width of the pulse that is turned on later is T3, the first pulse of the two pulses to be set And the data transmission time of the second data is: modulation time (data time) of the first data + pulse width T
3 or-Pulse width T1 + modulation time (data time) of the second data. Therefore, based on the magnitude relation between the first and second data to be modulated, if the first data> the second data, the pulse width T3 is set to the minimum pulse width, and the first data ≦ the second data In the case of the data of the above, by setting the pulse width T1 to the minimum pulse width, the data transmission time is also approximately: the modulation time of the first data (data time) or the modulation time of the second data. (Data time), and it becomes possible to transmit two types of data in approximately the same time as the transmission time of one of the larger types of data.

Further, for example, the most significant bit (MSB) of the first data is modulated as "1", and the other most significant data of the most significant bit (MSB) is modulated as "0". During modulation of the first and second data, the length relationship between the on-timing and on-timing of the two pulses and the off-timing and off-timing of the two pulses is always maintained. Those offset times as the first
And at least one of the second data, and when the data is separated and demodulated on the receiving side, the two pulses can be identified based on the relationship between the lengths of the two pulses.
It is not necessary to add any signal or information for identifying one pulse.

Further, the data to be transmitted is the above first and second data.
In the case of two types of data, a logic circuit whose output logic level is inverted at each on-timing of the serially transmitted pulse, and a logic circuit whose output logic level is inverted at each off-timing of the same pulse Can also be used for data separation and demodulation on the receiving side. As a result, the receiving side can perform the receiving process for these two types of data by using the normal PWM data demodulation method.

In the above communication method, a header pulse for identifying the first and second data sets to be assigned to the two pulses is additionally added to the two pulses forming the set. If these header pulses and the above two pulses are cyclically transmitted as a set, data of an integer multiple of 2, that is, twice the number of header pulses to be used, is serially transmitted through only one signal line. It is also possible.

[0015]

1 shows an embodiment of a PWM data communication method according to the present invention.

That is, in the communication method of this embodiment, as shown in FIG. 1, a first pulse that rises (turns on) at time A and falls (turns off) at time B and rises at time C ( Two pulses, a second pulse that falls (turns on) and falls (turns off) at time D,
Different 2 such as data 1 and data 2 to be transmitted
It incorporates two data and serially transmits it. Here, the data 1 is assigned to the time from each rising time (on timing) A to the rising time (on timing) C of these two pulses, and the data 2 is each falling time (off timing) of the same pulse. Falling time from B (off timing)
Allotted to time to D. By allocating data 1 and data 2 in this manner, these 2
The time required to transmit one data is the time TA from the rising time (ON timing) A of the first pulse to the falling time (OFF timing) D of the second pulse. Become. Then, in the communication method of this embodiment, the above-mentioned first and second pulses constituting the time TA are paired and transmitted as one cycle. Also, in order to demodulate this on the receiving side, these 2
The timing at which the logic level of one pulse changes, that is, the times A, B, C, and D, may be sequentially captured,
The demodulation can be performed as (CA) time for the data 1 and as (DB) time for the data 2.

As described above, according to the communication method of this embodiment, two data are incorporated into two pulses in a time-efficient manner, and therefore, in terms of data transmission efficiency or communication speed. Communication performance will be greatly improved.

Incidentally, assuming that the two pulses in the above set are respectively regarded as a header pulse and a data pulse in a conventional communication system using a header pulse, the communication method of this embodiment allows At the time when only one piece of data could be sent, the two pieces of data, data 1 and data 2, are sent. Therefore, it is possible to transmit these at least two pieces of data, which are supposed to be ordered with each other, at a communication speed at least twice as high as that of the conventional communication method.

If the cycle time T (transmission cycle time of each of the header pulse and the data pulse) defined in the above-mentioned conventional communication system is taken as the transmission cycle time of the above-mentioned two pulse sets, they are mutually ordered as in the above case. It is possible to transmit at least two data that are supposed to be transmitted at a communication speed four times that of the conventional one.

By the way, the time TA required to transmit the above two data means the pulse width T1 (time AB) of the first pulse and the pulse width T3 (time T2 of the second pulse, as also shown in FIG. Time C-D) and the off-time T2 between these first and second pulses (time B-C), which is the sum of the data transmission efficiency and the communication speed. It is effective to shorten this time TA.

In FIG. 2, the time TA is shortened in this way,
A transmission pulse construction method capable of further increasing data transmission efficiency or communication speed is shown. As shown in FIG. 1 above, the pulse width of the first pulse is T1 and the pulse width of the second pulse is T3 among the two pulses in the above set.
Then, the time TA required for data transmission of the two data of the data 1 and the data 2 is as follows: TA = modulation time of data 1 (time T1 + T2) + pulse width T3 or TA = modulation time of pulse width T1 + data 2 ( Time T2 +
Represented as T3).

However, the modulation time of the data 1 or the data 2 is a value obtained by time-converting the data 1 or 2 in accordance with the content (size) of the data, and its length cannot be freely adjusted.

Therefore, here, the data 1 to be modulated is
And data 2> data 2 based on the magnitude relation of data 2
If so, as shown in FIG. 2A, the pulse width T3 is set to a minimum pulse width (for example, 16 μs) that can be recognized as a pulse, and conversely, if data 1 ≦ data 2, As shown in FIG. 2 (b), the pulse width T1 is set to the minimum pulse width that can also be recognized as a pulse. That is, as a result, the data transmission time TA also becomes
When data 1> data 2, TA≈data 1 modulation time (time T1 + T2), and when data 1 ≦ data 2 TA≈data 2 modulation time (time T2 + T3), whichever is larger It is possible to transmit two types of data, that is, the data 1 and the data 2, in almost the same time as the data transmission time.

FIG. 3 shows an example of the structure of a multi-CPU system for realizing the communication method of the embodiment shown in FIG. 1 or FIG. That is, this system is provided with two CPUs, that is, the sending side CPU 1 and the receiving side CPU 2, and the timer matching output port P1 of the sending side CPU 1 is provided.
The signal line 3 is laid from 0 to the edge interrupt port P20 of the receiving CPU 2, and the signal line 4 is laid from the general output port P11 of the transmitting CPU 1 to the general input port P22 of the receiving CPU 2. As shown in FIG. 3, the signal line 3 is a signal line through which data 1 and data 2 are transmitted based on the communication method illustrated in FIG. 1 or 2, and the signal line 4 is a signal line. This is a signal line through which an auxiliary signal (hereinafter referred to as a first pulse determination signal) indicating the first pulse position in one cycle is transmitted in synchronization with the data output to the line 3.

FIGS. 4 to 6 show a data transmission procedure executed by the transmission side CPU 1, and FIGS. 7 to 8 show a data reception procedure executed by the reception side CPU 2, respectively. Hereinafter, the communication method of the above-described embodiment executed through the system will be described in more detail with reference to FIGS.

FIG. 4 shows a procedure for determining the pulse width of a transmission pulse based on the pulse construction method shown in FIG. 2. The transmission side CPU 1 is based on the procedure shown in FIG. The pulse width of the transmission pulse is determined in this manner.

That is, the transmitting CPU 1 first compares the sizes of data 1 and data 2 to be transmitted in step 400, and if data 1> data 2, the pulse width of the second pulse is passed through step 410. Set T3 to the minimum recognizable pulse width. Here, for example, T3 = 16 μs is set.

The transmitting side C having the pulse width T3 thus set
PU1 then determines the off time T2 between the first and second pulses through step 411, and further executes step 412 based on the determined time T2 to perform the first
The pulse width T1 of the pulse is calculated. As is apparent from FIGS. 1 and 2, the off time T2 can be obtained by T2 = time of data 2−pulse width T3, and the pulse width T1 can be calculated by T1 = time of data 1−off time T2. You can ask. Here, it is assumed that the data 1 and the data 2 are converted into time information in the following manners.

That is, now, the value “32” is set as the data 1.
Is given and the value “10” is given as the data 2, and the data communication in the system is based on, for example, 1 LSB (least significant bit length) = 32 μs and OFFSET (0 pulse length) = 32 μs. Assuming that this is done, the time for data 1 is 32 (value) × 32 μs (1 LSB) +32 μs (OFF
SET) = 1056 μs, and the time for data 2 is 10 (value) × 32 μs (1 LSB) +32 μs (OFF
SET) = 352 μs. Therefore, the time T2 is calculated as T2 = 352 μs−16 μs (T3) = 336 μs, and similarly, the pulse width T1 is also calculated as T1 = 1056 μs-336 (T2) = 720 μs.

On the other hand, when it is judged in the above step 400 that the magnitude relationship between the data 1 and the data 2 to be transmitted is data 1 ≦ data 2, the transmitting side C
PU1 sets the pulse width T1 of the first pulse to the minimum recognizable pulse width through step 420.
That is, in this example, T1 = 16 μs is set. Then, after that, through steps 421 and 422, the off time T2 and the pulse width T3 are changed in a manner similar to the above.
Are sequentially requested.

The transmitting-side CPU 1 having determined the pulse width T1, the off-time T2, and the pulse width T3, respectively, next, according to the procedure shown in FIG. 5, outputs the logical level of the first pulse discrimination signal to the signal line 4. (Step 500), the rising (ON) time A and the falling (OFF) time B of the first pulse in the determined transmission pulse are set in the timer coincidence output port P10 (step 501). After that, as the interrupt processing at the time B, the rising (on) time C and the falling (off) time D of the second pulse in the determined transmission pulse are set as described above according to the procedure shown in FIG. The timer coincidence output port P10 is set (step 600).

Incidentally, the transmitting side CPU 1 is a CPU having a large data storage capacity and is capable of setting all of the above four times A, B, C and D in the timer coincidence output port P10 within one cycle time. If it is, the time B interrupt processing shown in FIG. 6 is omitted.

On the other hand, the receiving side CPU 2 to which the data thus transmitted is inputted executes the receiving process of the inputted data in the following manner based on the procedure shown in FIGS. 7 and 8.

In the receiving side CPU 2, first, as the falling edge interrupt processing through the edge interrupt port P20, the falling edge of the input pulse, that is, the time (timing) of the transmission pulse added to FIG.
At B or time (timing) D, the interrupt process shown in FIG. 7 is executed.

That is, the CPU 2 on the receiving side receives the time B,
Alternatively, each time the interrupt process is started corresponding to time D, the input pulse is the first pulse ( First, it is determined whether it is the first pulse) (step 700). As a result, if it is determined that the pulse is the first pulse, the history of time A and time B, which are the rising (on) time and the falling (off) time of the pulse, is fetched (step 710), 1
If it is determined that the pulse is not the pulse, the history of time C and time D that is the rising (on) time and the falling (off) time of the pulse is taken in (step 7).
20).

In this way, the receiving-side CPU 2 that has fetched all the time information about the two pulses forming a set then follows the procedure shown in FIG. 8 as a data receiving process, and sets data 1 = time A-time C as data 1 The time is settled (step 800), and similarly, the time of data 2 is set as data 2 = time B−time D (step 801).

Incidentally, the demodulation from the thus determined time information to each value of the data 1 and the data 2 can be performed by the value of data = (time value-OFFSET) / LSB. That is, assuming that the time of the determined data 1 is “1056 μs” and the time of the data 2 is “352 μs”, the communication condition 1LSB (least significant bit length) = 32 μs OFFSET ( 0 pulse length) = 32 μs, so the value of data 1 = (1056 μs−32 μs) / 32 μs
= 32 Data 2 value = (352 μs−32 μs) / 32 μs =
It will be demodulated as 10.

The system shown in FIG. 9 is also a multi-CPU system which realizes the communication method of the embodiment shown in FIG. 1 or 2 like the system shown in FIG. In the system shown in FIG. 9, in addition to the two CPUs of the transmitting side CPU 1 and the receiving side CPU 2, two flip-flops 5 and 6 are provided.
And a signal (pulse) derived from the signal line 7 and having the logical level of the signal (pulse) inverted,
It is configured by including hardware (logic circuit) including an inverter 8 applied to the clock terminal CL. Signal line 7
Is a signal line laid from the timer coincidence output port P10 of the transmission side CPU 1 to the clock terminal CL of the flip-flop 5, and the signal lines 9 and 10 are respectively received from the output terminals Q of the two flip-flops 5 and 6. It is a signal line laid across the edge interrupt ports P20 and P21 of the side CPU2. The signal line 11 is laid from the general-purpose output port P12 of the transmission side CPU 1 to the reset terminals R of the two flip-flops 5 and 6. Incidentally, the above two flip-flops 5
6 and 6 are configured to invert the logical level of the signal output from the Q terminal at the rising edge of the signal (pulse) applied to the clock terminal CL. Also, if the signal applied to the reset terminal R is in the on (logical high level) state, those Q terminal outputs are also reset to the off (logical low level) state.

FIG. 10 shows an example of operation of the system shown in FIG. 9, and FIG. 11 shows a data transmission procedure executed by the transmission side CPU 1.
Hereinafter, the communication method of the above-described embodiment executed through the system will be described in detail with reference to FIGS. 10 and 11. It should be noted that most of the data transmission procedure executed in the transmission side CPU 1 is common to the procedures shown in FIGS. 4 to 6 above, and here, one cycle of data transmission timing setting is involved. Only the processing is shown in FIG.
11 as an alternative to the above, and redundant description of the common processing will be omitted.

In the system shown in FIG. 9, the transmitting CPU 1 first determines the pulse width of the transmitting pulse by the procedure shown in FIG. 4, and then the procedure shown in FIG. Accordingly, the rising (on) time A and the falling (off) time B of the first pulse in the determined transmission pulse are set in the timer coincidence output port P10 (step 1103). However, in the system shown in FIG. 9, the reset signals of the flip-flops 5 and 6 output to the signal line 11 are turned on (logic high level) prior to the time setting to the timer coincidence output port P10. (Step 1100), after a lapse of a predetermined time in which the flip-flops 5 and 6 can be reliably reset (step 1101), a process of releasing the reset signal is executed (step 110).
2). It should be noted that, after the timer coincidence output port P10 is set at the times A and B, the interrupt processing at the time B as shown in FIG.
If the CPU 1 has a large data storage capacity and is capable of setting all of the four times A, B, C, and D in the timer coincidence output port P10 within the time of one cycle, such times are set. The fact that the interrupt processing at B can be omitted is the same as in the case of the system shown in FIG.

FIG. 10D shows an ON / OFF mode of the reset signal, and FIG. 10A shows the CPU 1 on the transmitting side.
The output mode of the transmission data which is set to the timer coincidence output port P10 and output to the signal line 7 will be described.
Through the output data from the flip-flops 5 and 6 whose logic level is inverted based on the rising edge of the transmission data and the data whose logic level is inverted by the inverter 8, that is, the receiving side CPU 2 through the signal lines 9 and 10. The signals input to the
As shown in 0 (b) and (c), after being once reset to the off (logical low) level by the reset signal, the logic high level time is the same as the data 1 time or the data 2 time. The received signal is taken in by the receiving CPU 2. Therefore, the receiving side CPU 2 does not need the data receiving process as shown in FIG. 7 and FIG. 8, and simply sets the logical high level time of the signal taken in the ports P20 and P21 to the value of the data 1 or the value of the data 2. It suffices to perform only the process of demodulating.

As described above, according to the system shown in FIG. 9, the load on the receiving CPU itself is significantly reduced. Further, in the case of the same system, the signal lines 9 and 10 are connected to the input ports (edge interrupt ports) of the two separate receiving CPUs, and the data 1 and the data 2 are connected to these two separate receiving CPUs. It is also possible to transmit to.

In the system shown in FIG. 9, assuming that the signal potentials of the signal lines 9 and 10 are always set to the off (logic low) level in the initial state, The reset signal and the processing related to its transmission are unnecessary.

FIG. 12 shows another embodiment of the PWM data communication method according to the present invention. Also in the embodiment shown in FIG. 12, the data 1 is assigned to the time from the on timing of the first and second pulses to the on timing, and the data 1 is assigned to the time from the off timing of the two pulses to the off timing. The communication method itself of allocating data 2 and periodically transmitting these two pulses as a set is the same as in FIG.
Alternatively, it is similar to the case of the embodiment shown in FIG. Here, by changing the modulation method of the data 1 and the data 2, that is, the method of converting those data values into the length of time, it is possible to determine each of these data (pulses).

That is, in the embodiment shown in FIG. 12, the most significant bit (MSB) of data 1 is modulated as "1", and the other most significant bit (MSB) of data 2 is set to "1". When these two data are modulated such as "0", the time from the on-timing A of the first and second pulses to the on-timing C (time of data 1) and the off-timing of the two pulses are the same. The time from B to the off-timing D (time of data 2) is always given to those data such that the length relation is maintained in the relationship of time of data 1> time of data 2. . For the sake of simplicity, taking a 4-bit value as an example, for data 1, the most significant bit (MSB) is set to “1”, “1, X, X, X”.
The data value “X, X, X” is expressed in the form such as, and the other data 2 has the most significant bit (MS
The data value "X, X, X" is expressed in the form of "0, X, X, X" where B) is "0". As a result, even when the data 1 takes the minimum value, the modulation time becomes the time corresponding to the 4-bit value “1, 0, 0, 0”, and the same as when the data 2 takes the maximum value. The time is definitely longer than the time corresponding to the bit values “0, 1, 1, 1”.

FIG. 12 is an image of such a relationship between data 1 and data 2. In the state where the receiving side normally recognizes this as one cycle, the relationship of time of data 1> time of data 2 is maintained, and thus the front-back relationship of the first and second pulses, or the relationship between those data. Others will be recognized normally. Further, even if the receiving side erroneously recognizes the above one cycle and fetches the data so that the one cycle is started from the second pulse (a pulse that turns on at time C and turns off at time D), In that case, the time of data 1 (NG) becomes less than the time of data 2 (NG), so that the receiving side can easily judge that the recognition of one cycle is incorrect. .

As described above, according to the communication method of the embodiment shown in FIG. 12, when separating and demodulating data on the receiving side,
Since it becomes possible to discriminate the first pulse and further discriminate the data 1 and the data 2 based only on the length relation of the data time, a signal or information for discriminating the data or the first pulse. No need to add.

Therefore, even in the system illustrated in FIG. 3, the communication method of the embodiment shown in FIG.
The signal line 4 itself can be eliminated.

In the embodiment shown in FIG. 12, which MSB of data 1 or data 2 is set to "1" is arbitrary. Change of the data between the sender and the receiver
The same algorithm for demodulation need only be used.

Further, the communication method of the same embodiment which enables the discrimination of data is not always realized only by setting those MSBs. The point is that when modulating data 1 and data 2, the time from the on timing of the first and second pulses to the on timing and the time from the off timing of the two pulses to the off timing are always Any communication method may be used as long as it provides the offset time for at least one of the data 1 and the data 2 such that the long-short relationship is maintained.

In each of the above embodiments, the data to be transmitted is the data 1 and the data 2, but the data 1 of each cycle is, for example, as shown in FIG. Is used as a header for identifying the type of data 2 corresponding to it,
It is possible to serially transmit data of three or more types through only one signal line.

That is, FIG. 13 exemplifies such a communication method (FIG. 13B) of the present invention in comparison with a conventional communication method using a header pulse (FIG. 13A = FIG. 15). As shown in FIG. 13B, the header A is used as the header data for indicating the type of the data A, the header B is used as the header data for indicating the type of the data B, and the header C is used as the data C. If it is used as header data to indicate the type of, the time required for the conventional method is (1/2).
It becomes possible to serially transmit various types of data, and in a manner in which the data can be distinguished from each other.

Further, FIG. 14 shows still another embodiment of the communication method according to the present invention in comparison with the conventional communication method (FIG. 14 (a) = FIG. 15) which also uses a header pulse. It is a thing.

That is, according to the communication method of the embodiment, FIG.
As shown in (b), a header pulse for identifying a set of data 1 and data 2 to be assigned to these pulses is further added to the two pulses forming the set, and these header pulse and the above 2 are added. Periodically transmitted as a set of two pulses. In FIG. 14B, DA1 and DA2 respectively indicate data 1 and data 2 of the A group, and DB1 and DB2 respectively indicate
Data 1 and data 2 of group B are shown, where DC1 and DC2 are data 1 and data 2 of group C, respectively.
Indicates. The header pulses HA, HB, and HC may be the same as the conventional communication method.

As described above, according to the communication method of the embodiment shown in FIG. 14B, at the same time as the conventional communication method,
It becomes possible to serially transmit twice as many kinds of data as the conventional one. More generally, it becomes possible to serially transmit the data of an integer multiple of 2, that is, twice the number of header pulses to be used, which is the conventional data, through only one signal line.

The system to which the communication method of each of the above-described embodiments is applied is not necessarily limited to the multi-CPU system as illustrated in FIG. 3 or FIG. INDUSTRIAL APPLICABILITY The communication method of the present invention can be applied to all serial communication systems using PWM data, and for the communication systems to which they are applied, the maximum data transmission efficiency via the minimum data transmission medium, Alternatively, the communication speed can be guaranteed.

[0057]

As described above, according to the PWM data communication method of the present invention, not only the use efficiency of the signal line and the CPU input / output port but also the data transmission efficiency or the communication speed is excellent. Communication performance can be obtained.

[Brief description of drawings]

FIG. 1 is a time chart showing an embodiment of a PWM data communication method according to the present invention.

FIG. 2 is a time chart showing a transmission pulse constructing method for further shortening the data transmission time in the communication method of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a system configuration example for realizing the communication method of the embodiment shown in FIG.

4 is a flowchart showing a pulse width determination procedure of a transmission pulse executed by a transmission side CPU of the system shown in FIG.

5 is a flowchart showing a procedure for constructing a first half of a transmission pulse, which is executed by a transmission side CPU of the system shown in FIG.

6 is a flowchart showing a procedure for constructing a latter half of a transmission pulse executed by a transmission side CPU of the system shown in FIG.

FIG. 7 is a flowchart showing an interrupt processing procedure by a reception pulse, which is executed in the reception side CPU of the system shown in FIG.

8 is a flowchart showing a data receiving procedure executed by a receiving side CPU of the system shown in FIG.

FIG. 9 is a block diagram showing another system configuration example for realizing the communication method of the embodiment shown in FIG.

FIG. 10 is a time chart showing an operation example of the system shown in FIG.

11 is a flowchart showing a procedure for constructing a first half of a transmission pulse, which is executed by a transmission side CPU of the system shown in FIG.

FIG. 12 is a time chart showing another embodiment of the PWM data communication method according to the present invention.

FIG. 13 is a time chart showing a PWM data communication method according to the present invention and a conventional communication method using a header pulse for comparison.

FIG. 14 is a time chart showing still another embodiment of the PWM data communication method according to the present invention.

FIG. 15 is a time chart showing an example of a conventional communication method using a header pulse.

[Explanation of symbols]

1 ... Transmission side CPU, 2 ... Reception side CPU, 3, 4 ... Signal line, 5, 6 ... Flip-flop, 7 ... Signal line, 8 ... Inverter, 9, 10, 11 ... Signal line.

Claims (6)

[Claims] 1. A PWM data communication method in which a plurality of pieces of data are pulse-width modulated and serially transmitted, and the pieces of data are separated and demodulated on the receiving side, the method being the first from the ON timing of two pulses to the ON timing. 1. A PWM data communication method comprising: allocating 1 data, allocating 2nd data in the time from the off timing of the same two pulses to the off timing, and periodically transmitting these 2 pulses as a set. 2. When the pulse width of a pulse that is turned on first of the two pulses of the set is T1 and the pulse width of a pulse that is turned on later is T3, the first and second modulation targets are set. 1st data> 2nd based on the magnitude relationship of the data
2. The PWM data according to claim 1, wherein the pulse width T3 is set to the minimum pulse width when the data is the above data, and the pulse width T1 is set to the minimum pulse width when the first data ≦ the second data. Communication method. 3. When modulating the first and second data, the time from the on-timing to the on-timing of the two pulses and the time from the off-timing to the off-timing of the two pulses are always the same. At least one of the first and second data is provided with an offset time such that the length relationship is maintained, and when the data is separated and demodulated on the receiving side, two sets are formed based on the time relationship. The PWM data communication method according to claim 1, wherein the pulse is identified. 4. A logic circuit in which an output logic level is inverted at each on-timing of the serially transmitted pulse and a output logic level at each off-timing of the same pulse for separating and demodulating data on the receiving side. The PWM data communication method according to claim 1, wherein a logic circuit for inverting is used. 5. The PWM data communication method according to claim 1, wherein each of the first or second data transmitted cyclically is used as a header for identifying a type of the corresponding second or first data. . 6. The PWM data communication method according to claim 1, further comprising a header pulse for identifying the first and second data sets to be assigned to the two pulses, which are included in the set. P is characterized in that the header pulse and the two pulses are periodically transmitted as a set.
Communication method of WM data.