JPH0746097A - Signal level identification circuit - Google Patents

Abstract

PURPOSE:To well discriminate the level of digital signals for which a maximum run length is limited. CONSTITUTION:Reproduction signals from a medium receive the delay of an identification timing clock period by the respective delay elements DL of a delay circuit 50 and the signals of the maximum run length N+1 are inputted to a maximum value detection circuit 52 and a minimum value detection circuit 54. Since a signal value corresponding to the H of a logical value and the signal value corresponding to the L of the logical value are surely present in the reference signal values of the maximum value detection circuit 52 and the minimum value detection circuit 54 a maximum value and a minimum value are detected well. The average of the maximum value and the minimum value is obtained in resistors R3 and R4 and is subjected to sample-and-hold in a sample-and-hold circuit 56 at the timing of sample pulses supplied from a sample pulse generation circuit 58. In a comparator 30, the average value is defined as a comparison level and the binarization processing of the reproduction signals is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital video tape recorder (D-VTR), a digital audio recorder.
The present invention relates to a digital signal reproducing device such as a tape recorder (DAT), and more particularly to an improvement of a signal level identification circuit for identifying the logical value level of a signal.

[0002]

2. Description of the Related Art As a digital signal reproducing apparatus, there is a digital signal magnetic recording / reproducing apparatus as shown in FIG. Referring to the recording side in the figure, a digital signal such as a digital video signal is encoded by an error correction encoder (not shown) and the processed signal is supplied to the recording encoder 10. In the recording encoder 10, the digital signal is modulated so as to match the characteristics of the magnetic tape / magnetic head system that is the transmission system. Several methods are known as modulation methods.

For example, the recording signal is "0" (or "L").
And “1” (or “H”), and a maximum value in which “0” or “1” is continuous, that is, the maximum run length is limited. The 8-10 modulation code used in DAT is an example (The DAT Co
nference Standard for the Digital Audio Tape Recor
d-ing Systems, Electric Industries Associations of
Japan (June, 1987)). By limiting the maximum run length, there is an advantage that the reproduction clock can be easily extracted from the recording / reproduction signal.

A signal encoded by the recording encoder 10 is amplified by a recording amplifier 12 and supplied to a recording magnetic head 16 via a rotary transformer 14. Then, a signal is recorded on the magnetic tape 18 as a magnetization pattern. The recorded magnetization pattern is read by the reproducing magnetic head 20, and the rotary transformer 2
The signal is amplified to the required level by the regenerative amplifier 24 via 2.

The low frequency component of the frequency of the amplified signal is raised by the integrator 26. This compensates for the differential characteristics of the ring-type reproducing magnetic head 20. The waveform equalizer 28 raises the high frequency component of the integrated signal. This is for compensating the attenuation of the high frequency component due to the waveform interference of the recording magnetization pattern on the magnetic tape 18 and improving the so-called eye pattern.

Next, the output of the waveform equalizer 28 is supplied to the comparator 3
0 and the clock recovery circuit 32, respectively. The comparator 30 compares the input signal with the zero potential (ground level) and outputs a binary signal of "1" or "0". On the other hand, the clock reproduction circuit 32 extracts a reproduction clock indicating the identification timing of the reproduction signal from the input signal. The binary signal output of the comparator 30 is supplied to the D input of the D-type flip-flop in the next stage, and the recovered clock obtained by the clock recovery circuit 32 is supplied to the clock input of the flip-flop 34.

In the flip-flop 34, the input data is latched at the rising timing of the reproduction clock and Q
It is output from the output. The output of the flip-flop 34 is a digital signal, and this digital signal is supplied to the decoder 36. The decoder 36 performs a decoding process that is the reverse of the encoding performed by the recording encoder 10, and the processed signal is supplied to an error correction code decoding circuit (not shown). .

By the way, in the recording / reproducing of the digital signal as described above, when the recorded digital signal contains a relatively large amount of low frequency components, the comparator 30 of FIG. It is known that the error rate of level detection during reproduction detection can be reduced by using the level discriminating circuit as shown in (Nakagawa et al., "Study on integral detection method in NRZ recording", IEICE technical research. Report, MR 77-46).

In the figure, the output signal of the waveform equalizer 28 in FIG. 2 is supplied to the terminal TA. A low-pass component of the input signal is removed by a high-pass filter composed of a capacitor CA and a resistor RA, and a volume VR, a diode DA, and a diode DA are passed through a buffer amplifier GA.
It is supplied to DB respectively. A capacitor CB and a resistor RB are connected to the cathode side of the diode DA, and these circuits output a signal following the peak of the positive potential of the input signal. A capacitor CC and a resistor RC are connected to the output side of the diode DB, and these circuits output a signal following the peak of the negative potential of the input signal.

Each of these peak tracking signals has a resistance RD,
The signals are combined through RE and supplied to the inverting input side of the comparator GB. The signal output from the above-mentioned volume VR is supplied to the non-inverting input side of the comparator GB. In the comparator GB, the signal supplied from the volume side from which the low frequency component with relatively large noise is removed,
Level detection is performed with reference to the peak tracking signal supplied from the circuit side of the diodes DA, DB and the like. The terminal TB to which the output side of the comparator GB is connected is connected to the D input side of the flip-flop 34 in FIG. 2, and the comparison result becomes the D input.

[0011]

FIG. 4A shows an example of a digital signal to be recorded, and FIG. 4B shows the output of the waveform equalizer of the reproduced signal. . Figure 5
Other similar signal examples are shown in (A) and (B). In these figures, the time indicated by the alternate long and short dash line represents the identification timing. In the prior art of FIG. 2, the comparison level of the comparator 30 is 0 potential, and in each figure (B), a signal larger than the comparison level is set to “1” and a small signal is set to “0” at the identification timing. Then, level identification is performed.

In this case, the waveforms shown by broken lines in each figure (B) are almost ideal reproduced waveforms, and in this case, no level identification error occurs. However, in the waveform of the solid line actually obtained, an error occurs at point f in FIG. 4 (B) and point q in FIG. 5 (B). Such a reproduced waveform is generated due to lack of high frequency compensation by the waveform equalizer 28, bit shift due to non-linearity of the recording / reproducing system, and the like.

In the prior art shown in FIG. 3, since relatively low frequency noise is suppressed as described above, a level discrimination error caused by such low frequency noise is eliminated. Can be reduced. The upper limit of the frequency band having the suppression effect is determined by the discharge time constants of the resistor RB, the capacitor CB, the resistor RC, and the capacitor CC.

However, it has been pointed out in the above literature that if the discharge time constant is reduced in order to obtain a suppression effect in the high frequency range, the noise margin for the high frequency noise component is adversely affected. Therefore, this technique is effective only when the identification error occurs due to the noise of the relatively low frequency, and is not effective for the identification error caused by the noise of the high frequency. Further, in the case where a large-amplitude noise is suddenly superimposed on the reproduced signal, the identification error is likely to occur for the time corresponding to the discharge time constant due to the influence of this noise.

The present invention focuses on these points,
It is an object of the present invention to provide a level identification circuit capable of favorably performing level identification when the maximum run length of a digital signal is limited.

[0016]

In order to achieve the above object, the present invention provides a signal level identification for performing level identification on a reproduced signal obtained by reading an encoded signal having a maximum run length limited to N from a recording medium. In the circuit, delay means for delaying the reproduction signal to extract at least N + 1 signals, and at least N extracted by the delay means.
A maximum / minimum detecting means for detecting the maximum value and the minimum value by referring to the +1 signal, and an average value calculating / holding means for obtaining and holding an average value of the maximum value and the minimum value of the reproduced signal detected by the maximum and minimum value. The comparison means compares the average value held thereby as a comparison level with the reproduction signal to perform level identification. In another invention, in the above invention, the maximum / minimum detecting means is provided with a limiting means for limiting the maximum value and the minimum value to a predetermined range.

[0017]

According to the present invention, the signal to be processed is limited in maximum run length N. Then, at least N + 1 signals are referenced with respect to this maximum run length, and their maximum value and minimum value are detected. Therefore, N + 1
Since the logical values “H” and “L” are always included in the number, the average value of the signals can be satisfactorily obtained. Then, the signal level is discriminated by using this average value as a comparison level.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal level identification circuit according to the present invention will be described in detail below with reference to the accompanying drawings. <First Embodiment> FIG. 1 shows the configuration of the first embodiment of the present invention. The same reference numerals are used for the same components as those of the above-described conventional technique or components corresponding to the conventional technique. Further, it is assumed that the maximum run length of the target signal of this embodiment is limited to "4".

In the figure, the input terminal T1 is connected to the delay circuit 50. The delay circuit 50 is composed of four delay elements DL connected in series. The output terminals of the input terminal T1 and the delay elements DL are connected to the anode side of the diode D1 in the maximum value detection circuit 52 and to the cathode side of the diode D2 in the minimum value detection circuit 54, respectively. The output side of the delay circuit 50 is the non-inverting input side of the comparator 30 (+
Side).

The cathode side of the diode D1 of the maximum value detection circuit 52 is connected to the ground via the resistor R1 on the one hand and to the resistor R3 on the other hand. Similarly, the anode side of the diode D2 of the minimum value detection circuit 54 is connected to the ground via the resistor R2 on the one hand and to the resistor R4 on the other hand. Further, the resistors R3 and R4 are connected to a buffer amplifier G1 on the input side of the sample hold circuit 56, and the output side of the buffer amplifier G1 is connected to the buffer amplifier G2 and the capacitor C1 via the switch S1. . The output side of the buffer amplifier G2 is connected to the inverting input side (-side) of the comparator 30.

The output side of the comparator 30 is connected to the D input of a D type flip-flop 34. The input terminal T1 is connected to the clock recovery circuit 32,
The output side of the clock reproduction circuit 32 is connected to the sample pulse generation circuit 58 and the clock input of the flip-flop 34, respectively. And flip-flop 3
The Q output of 4 is connected to the output terminal T2.

The input terminal T1 is the waveform equalizer 2 of FIG.
8 and the output terminal T2 is connected to the decoder 36. Further, the maximum value limiting circuit 60 and the minimum value limiting circuit 62 in the figure are used in the second embodiment described later and need not be considered in the first embodiment.

Of the above-mentioned respective units, the delay element DL inputs the input signal to one clock period td of the identification timing clock.
It is for delaying each and outputting. In the maximum value detection circuit 52, five signals respectively input from the input terminal T1 and the delay element DL are supplied to the diode D1, and the maximum value among the input signals is determined by the action of the diode D1 and the resistor R1. It is supposed to be output. On the contrary, in the minimum value detection circuit 54, the minimum value of the input signals is output by the action of the diode D2 and the resistor R2.

The resistors R3 and R4 are for taking and outputting the average value of the detected maximum and minimum values. In the sample hold circuit 56, the sample pulse generating circuit 5
The switch S1 is turned on at the timing of the sample pulse supplied from 8, and the capacitor C1 is charged by the input signal, so that the input signal is sampled and held. The resistors R3 and R4 and the sample hold circuit 56 constitute a threshold value calculation holding circuit.

The sample pulse generating circuit 58 for supplying the sample pulse to the sample hold circuit 56 has a ratio of once every five rising edges of the reproduced clock signal (identical to the identification timing clock) obtained by the clock reproducing circuit 32. A sample pulse having a time width sufficiently shorter than one clock period td is generated at the timing immediately before the rise. The comparator 30 binarizes the output of the delay circuit 50 using the signal level held by the sample hold circuit 56 as a comparison level. Flip flop 3
4 has a function of latching and outputting the input signal at the rising timing of the reproduction clock supplied from the clock reproduction circuit 32.

Next, the basic operation of the embodiment constructed as described above will be explained.
The reproduced signal output of the waveform equalizer 28 (see FIG. 2) shown by the solid line in (B) is supplied to the delay circuit 50, and the delay element DL causes the identification timing clock period td.
Delays (intervals of alternate long and short dash lines in FIGS. 4B and 5B) are successively received. The output of each delay element DL and the input of the first delay element DL are input to the maximum value detection circuit 52 and the minimum value detection circuit 54, respectively.

The maximum value detection circuit 52 detects the maximum value in the input signal. For example, in FIG. 4B, if five signals of points a to e are input to the maximum value detection circuit 52, the signal level at point d, which is the maximum value of them, is detected as the maximum value. . On the other hand, the minimum value detection circuit 5
At 4, the minimum value in the input signal is detected. For example, in FIG. 4 (B), if five signals from point a to point e are input to the minimum value detection circuit 54, the signal level at point b, which is the minimum value, is detected as the minimum value. .

The maximum and minimum values of these are the resistances R3 and R4.
Then, the average value is obtained and is supplied to the sample hold circuit 56. The sample hold circuit 56 samples and holds the input signal at the timing of the sample pulse given from the sample pulse generation circuit 58. For example, in FIG. 4B, th1 and th2, and in FIG. 5B, th3 and t.
Those operations are performed at the timing of h4. Then, the comparator 30 compares the reproduced signal with the reproduced signal based on the held signal level. That is, in the present embodiment, the binarization processing of the reproduced signal is performed using the average value of the maximum value and the minimum value of the input signal level as the comparison level.

By the way, in the present embodiment, the maximum run length of the signal to be processed is limited to 4 as described above, and the maximum value and the minimum value both refer to this maximum run length + 1 signal value. is doing. Therefore, there is always a signal value corresponding to the logical value "1" and a signal value corresponding to the logical value "0" in the reference signal values. Therefore, the maximum value and the minimum value are detected well, and the average value of them is also obtained well. Since the signal level is binarized using this average value, it is possible to perform good level discrimination without causing the inconvenience of the above-described conventional technique.

The waveform examples of FIGS. 4 and 5 will be described in detail. The values sampled and held at time th1 are as shown in FIG.
It is the average value LA1 of the maximum value d and the minimum value b among the signal values a, b, c, d and e in (B). Similarly, the value sampled and held at time th2 is the signal value f,
The average value L of the maximum value i and the minimum value h of g, h, i, j
It is A2. The signal values f, g, h, i, j will be compared with this average value LA2. As a result, in the conventional technique, the level of the signal at the point f, which has become an identification error, is correctly identified.

Similarly, the signal values m, n, and
Since o, p, and q are compared with the average value LB1, the level of the signal at point q, which is an identification error in the prior art, is correctly identified.

As described above, according to the first embodiment, the reproduced signal value sampled at the identification timing is used as the comparison level, and the maximum run length + 1 signal value is obtained by utilizing the knowledge of the maximum run length. Since the comparison level is obtained by reference, it is possible to prevent an identification error caused by factors other than relatively low frequency noise, and perform good level identification. Even if error correction processing is performed using an error correction code or the like, it is not always possible to correct all identification errors. Therefore, the level identification errors are reduced and uncorrectable errors are also reduced.
Therefore, it is possible to improve the reproduction quality in a digital signal reproducing device such as a VTR.

<Second Embodiment> Next, a second embodiment of the present invention will be described. In the second embodiment, a maximum value limiting circuit 60 and a minimum value limiting circuit 62 are provided in the circuit of FIG. Maximum value limiting circuit 60
Is composed of power sources V1 and V2, diodes D3 and D4, and a resistor R5.
D4 is connected in anti-parallel. Also, V1> V2 is set. Therefore, the diode D3 conducts when the detection voltage of the maximum value detection circuit 52 becomes V1 or more and limits the output, and conversely, the diode D4 when the detection voltage of the maximum value detection circuit 52 becomes V2 or less. To limit the output. That is, the maximum value limiting circuit 60 has the function of limiting V1> maximum value> V2.

The minimum value limiting circuit 62 is composed of power sources V3, V4, diodes D5, D6, and a resistor R6.
Diodes D5 and D6 are connected in antiparallel to the power supplies V3 and V4. Also, V3 <V4 is set. Therefore, the diode D5 conducts when the detection voltage of the minimum value detection circuit 54 becomes V3 or less and limits the output, and conversely, the diode D6 when the detection voltage of the minimum value detection circuit 54 becomes V4 or more. To limit the output. That is, the minimum value limiting circuit 62 has the function of limiting V3 <minimum value <V4.

Next, the operation of this embodiment will be described.
Since the maximum value limiting circuit 60 and the minimum value limiting circuit 62 operate symmetrically with each other, the maximum value limiting circuit 60 will be described as a representative. The power supplies V1 and V2 of the maximum value limiting circuit 60 are set to potential levels as shown in FIGS. 4 (B) and 5 (B), for example.

For example, it is assumed that a sudden large-amplitude positive noise is superimposed on the signal at the point d and has a value larger than V1. In this case, according to this embodiment, the maximum value is limited to V1, and this V1 becomes the output of the maximum value detection circuit 52. As described above, according to the present embodiment, it is considered that the signal value of V1 or more has a large potential due to noise, and it is possible to favorably prevent the comparison level from becoming unnecessarily large due to noise.

On the contrary, for example, it is assumed that a sudden large-amplitude negative noise is superposed on the signal at the point s and has a value smaller than V2. In this case, according to this embodiment, the maximum value is limited to V2, and this V2 becomes the output of the maximum value detection circuit 52.
As described above, according to the present embodiment, it is considered that the signal value of V2 or less becomes a small potential due to noise,
Noise prevents the comparison level from becoming unnecessarily large. Also in the minimum value limiting circuit 62, the minimum value is similarly limited to V3 to V4.

<Other Embodiments> The present invention is not limited to the above embodiments, and includes, for example, the following. (1) In the above embodiment, the delay circuit 50, the maximum value detection circuit 52, the minimum value detection circuit 54, and the comparator 30 are configured as analog circuits, but they may be configured as digital circuits. In this case, an A / D converter using the reproduction clock as a sampling clock is provided on the input terminal T1 side of FIG. Then, the delay element DL may be configured by a flip-flop of a predetermined bit unit, and the maximum value detection circuit 52, the minimum value detection circuit 54, the comparator 30 and the like may be replaced with logic circuits. In addition, various design changes can be made so as to achieve the same operation.

(2) In the above-mentioned embodiment, the maximum value and the minimum value are individually limited, but the average value synthesized from the maximum value and the minimum value is also limited, which is almost the same. The effect is obtained. (3) Although the maximum run length is 4 in the above-mentioned embodiment, the value is not limited to that value. If the average value is obtained with reference to at least the signal of maximum run length + 1, the above effect can be obtained regardless of the maximum run length value.

[0040]

As described above, the signal level identification circuit according to the present invention has the following effects. (1) When the maximum run length of the signal to be processed is limited to N, the maximum value and the minimum value are obtained by referring to N + 1 signals, and the average value is set as the comparison level for level identification. The level identification can be performed satisfactorily without error. (2) Since the maximum value and the minimum value are limited,
The influence of noise can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal level identification circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a configuration example of a digital signal recording / reproducing apparatus.

FIG. 3 is a circuit diagram showing an improved conventional example of a signal level identification circuit.

FIG. 4 is a graph showing a waveform example of a recording signal and a reproduction signal thereof.

FIG. 5 is a graph showing another waveform example of a recorded signal and its reproduced signal.

[Explanation of symbols]

30 ... Comparator, 32 ... Clock regenerator, 34 ... Flip-flop, 50 ... Delay circuit, 52 ... Maximum value detection circuit, 5
4 ... Minimum value detection circuit, 56 ... Sample hold circuit, 5
8 ... Sample pulse generating circuit, 60 ... Maximum value limiting circuit,
62 ... Minimum value limiting circuit, C1 ... Capacitor, DL ... Delay element, D1 to D6 ... Diode, G1, G2 ... Buffer amplifier, LA, LB ... Average value as comparison level, R1 to R6 ...
Resistance, S1 ... Switch, V1-V4 ... Power supply, a-v ... Signal point, td ... Delay time, th1-th4 ... Sampling timing.

Claims (2)

[Claims] 1. A signal level discriminating circuit for discriminating a level of a reproduced signal obtained by reading a coded signal having a maximum run length limited to N from a recording medium, delaying the reproduced signal to obtain at least N + 1. Delay means for extracting the signal of at least N, and at least N extracted by the delay means
A maximum / minimum detecting means for detecting the maximum value and the minimum value by referring to the +1 signal, and an average value calculating / holding means for obtaining and holding an average value of the maximum value and the minimum value of the reproduced signal detected by the maximum and minimum value. A signal level discriminating circuit comprising: a comparison means for discriminating a level by comparing the average value held thereby as a comparison level with the reproduction signal. 2. The signal level identification circuit according to claim 1, wherein the maximum / minimum detecting means includes limiting means for limiting the maximum value and the minimum value to a predetermined range. .