JPH0745706A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a pillar and the wiring of the lower part of the pillar in an excellent reproducible manner and to simply conduct inter-wiring connection by a method wherein an aluminum film is deposited in the groove pattern of an insulating film, a wiring operation is conducted thereon, a pillar part and a wiring part are formed simultaneously, and the insulating film is exposed at the point of time when the pillar part and the wiring part are formed. CONSTITUTION:A BPSG film 2 and a resist groove pattern 3 are formed on a semiconductor substrate 1. A groove 4 is formed by etching the BPSG film 2, and resist is removed. An aluminum film 5 is deposited on the whole surface, a resist pattern 6, which becomes a pillar, is formed and the aluminum film 5 is etched. After the resist pattern 6 has been removed, a pillar 7 and the first wiring 8 are formed. After a silicon oxide film 9 has been formed on the whole surface, the silicon oxide film 9 is flattened until the upper part of the pillar 7 is exposed, an aluminum film 5 is deposited, and the second wiring 10 is formed by lithographic method and dry etching. As a result, the end point of aluminum etching can be detected easily using a luminescent/ spectral diffraction method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming electrodes for multi-layer wiring.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high integration of LSIs, devices having a multilayer wiring structure are being developed. One of the major problems in the multilayer wiring structure is that the method of connecting the wirings is a method of opening a connection hole in the wiring insulating layer and embedding a conductive material, so that it is a complicated process and causes a decrease in yield and throughput. Is mentioned. As a method for easily connecting the wirings, a metal pillar (hereinafter referred to as a pillar) is formed on the wirings, a second insulating layer is further formed on the metal pillars, and flattening is performed until the upper part of the metal is exposed. After that, a method of forming the second wiring has been proposed. In this method (hereinafter referred to as a pillar formation method), since the pillars are formed, there is an advantage that fine interconnections with a high aspect ratio can be easily connected.
An example of the conventional pillar forming method described above will be described below with reference to the drawings.

FIG. 8 and FIG. 9 are process explanatory views of a conventional pillar forming method. FIG. 8 is disclosed in JP-A-61-208849, and FIG. 9 is disclosed in JP-A-61-208850.

In FIG. 8, a silicon oxide film on the semiconductor substrate 1 or containing boron and phosphorus (hereinafter referred to as a BPSG film).
An aluminum film 5 is deposited on the surface 2 and a wiring-shaped resist pattern 17 is formed by photolithography (FIG. 8).
(A)). Next, after the aluminum film 5 is etched by dry etching, the resist pattern 17 is removed to form the first wiring 8 (FIG. 8B). A resist pattern 6 to be a pillar is formed on the wiring 8 by photolithography, and aluminum is etched to half the wiring film thickness by dry etching (FIG. 8C). Resist pattern 6
Then, a silicon oxide film 9 is deposited, and the silicon oxide film 9 is flattened until the upper portion of the pillar 7 is exposed (FIG. 8D). The second wiring 10 is formed thereon (FIG. 8).
(E)).

In FIG. 9, instead of depositing the aluminum film 5 in the step of FIG. 8A, a laminated film 18 of, for example, aluminum 5 / tungsten 11 / aluminum 5 is deposited, and a wiring-shaped resist is formed thereon by photolithography. The pattern 17 is formed (FIG. 9A). Next, after the laminated film 18 is etched by dry etching, the resist pattern 17 is removed to form a laminated wiring 19 (FIG. 9).
(B)). A resist pattern 6 to be a pillar is formed on the laminated wiring 19 by photolithography, and after etching with a gas system containing chlorine, the resist pattern 6 is removed to form an aluminum pillar 7 on the tungsten (see FIG. 9 (c)). Next, a silicon oxide film 9 is deposited, and the silicon oxide film 9 is flattened until the upper portion of the pillar 7 is exposed (FIG. 9D). The second wiring 10 is formed on it (FIG. 9E).

Further, flattening the wiring and the interlayer insulating film is one of the problems in the multilayer wiring structure. Recently, a flattening method by polishing has been proposed. Among them, a method of forming a groove in an insulating film, depositing a metal film to be a wiring, and flattening by polishing has attracted attention (Nikkei Microdevices). August 1992 page 49-50). In this method, the insulating film can be used as a stopper when polishing the metal film,
It has the advantages that it is not necessary to detect the end point of polishing and the degree of freedom in selecting a metal film is increased. An example of the conventional planarization method by polishing will be described below with reference to the drawings.

FIG. 10 is a process explanatory view of a conventional wiring flattening method by polishing.

A BPSG film 2 is deposited on the semiconductor substrate 1 and heat-treated, and a resist groove pattern 3 to be a wiring is formed on the BPSG film 2 by photolithography (FIG. 10).
(A)). Next, the BPSG film 2 is etched to a desired depth by dry etching to remove the resist (see FIG. 10).
(B)). After depositing the aluminum film 5 on the entire surface, the aluminum film 5 is polished by a chemical mechanical polishing method (hereinafter referred to as CMP) until the upper surface of the BPSG film 2 is exposed to form a first wiring 8 (see FIG. 10 ( c)). Next, a silicon oxide film 9 is deposited on the entire surface by chemical vapor deposition, and a contact hole (hereinafter referred to as a via hole) 20 is opened by photolithography and dry etching (FIG. 10D). Tungsten 11 is deposited on the entire surface by chemical vapor deposition, and tungsten 11 is deposited by CMP until the upper surface of silicon oxide film 9 is exposed.
Is polished and flattened (FIG. 10E). The second wiring 10 is formed thereon (FIG. 10 (f)).

[0009]

However, in the method of connecting wirings as described above, it is necessary to stop the etching of the metal film on the way or to form an etching stopper layer for forming pillars. In such a process, if etching is stopped midway, it is difficult to obtain processing reproducibility, and if an etching stopper is formed, a metal deposition process of a plurality of layers is required,
There is a problem that a new etching technique is required to etch the metal of a plurality of layers.

Further, the wiring flattening method has problems that a step of opening a via hole is required and that a metal polishing step has a low throughput.

Therefore, in view of the above problems, the present invention provides a method of manufacturing a semiconductor device, in which the pillars and the wirings under the pillars are formed with good reproducibility, and the interconnection between the wirings is easily performed. is there.

[0012]

In order to solve the above problems, a first method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first insulating film on a semiconductor substrate and a step of forming the first insulating film. Forming a groove in the film, depositing a metal film on the first insulating film including the groove, forming a resist pattern on the metal film, and forming a metal film on the first insulating film. To form a metal pillar and a metal wiring, and a second insulating film is formed on the metal pillar, the metal wiring, and the first insulating film until the upper surface of the metal pillar is exposed. And a step of etching the second insulating film.

A second method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a groove in the first insulating film, and the groove. Depositing a first metal film on the first insulating film, and
Forming a resist pattern on the metal film and etching the first metal film on the first insulating film to form a metal column and a metal wiring; and electroless plating or selective chemical vapor deposition. A step of selectively forming a second metal film on the metal wiring and the metal pillar by a method, and forming a second insulating film on the second metal film and the first insulating film, The second
And etching the second insulating film until the upper surface of the metal film is exposed.

A third method for manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a groove in the first insulating film, and the groove. The first
A step of depositing a metal film on the insulating film, a step of removing the metal film until the first insulating film is exposed, forming a metal wiring, and forming a resist pattern on the metal wiring,
Etching the metal wiring to form a metal pillar, and forming a second insulating film on the metal pillar, the metal wiring, and the first insulating film until the upper surface of the metal pillar is exposed. And a step of planarizing the second insulating film.

[0015]

With the first or second structure of the present invention, the etching end point of the metal film can be detected on the first insulating film.
Pillars can be formed with good reproducibility.

Further, according to the second structure of the present invention, by depositing the metal film on the pillars and the wirings below the pillars, it is possible to prevent the pillars from being thinned and the wirings below the pillars from being broken during etching.

Further, according to the third structure of the present invention, the pillars are formed on the wiring formed in the groove, so that the metal deposition step and the polishing step can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pillar forming method according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a process explanatory view of a pillar forming method in a first embodiment of the present invention.

A BPSG film 2 is deposited on the semiconductor substrate 1 and heat-treated, and a resist groove pattern 3 to be a wiring is formed on the BPSG film 2 by photolithography (FIG. 1).
(A)).

Next, the BPSG film 2 is etched to a desired depth by dry etching to form a groove 4 and the resist is removed (FIG. 1 (b)). An aluminum film 5 is deposited on the entire surface, and a resist pattern 6 serving as a pillar is formed thereon (FIG. 1 (c)). The aluminum film is etched with a gas system containing chlorine (Fig. 1 (d)). The aluminum etching apparatus has a configuration capable of detecting the etching end point when the aluminum film is etched until it reaches the insulating film. After removing the resist pattern 6, the pillar 7 and the first wiring 8 are formed.

Next, after the silicon oxide film 9 is formed on the entire surface by chemical vapor deposition (FIG. 1E), the silicon oxide film 9 is flattened by etching back or polishing until the upper portion of the pillar 7 is exposed. (Fig. 1 (f)). Further, the aluminum film 5 is deposited, and the second wiring 10 is formed by lithography and dry etching (FIG. 1 (g)).

As described above, according to this embodiment, as shown in FIG.
In the step (d), the aluminum film is deposited in the groove pattern of the insulating film and the portion is used as a wiring, so that the pillar portion and the wiring portion can be formed at the same time. A perspective view at that time is shown in FIG.

Since the insulating film is exposed when the pillar portion and the wiring portion are etched and formed, it is possible to easily detect the end point of aluminum etching by the emission spectroscopic analysis method. This state is shown in FIG. This figure shows the emission wavelength of chlorine emitted in plasma used for etching aluminum film,
It shows an emission spectral analysis method for investigating the intensity change, and at the same time, shows that the shape of the sample changes with the etching time in a sectional view.

When a pillar is formed by stopping the etching of the aluminum film in the middle as in the conventional case, the emission intensity of chlorine is changed between (a) and (b) of FIG. Since it does not change during etching, it is necessary to decide the time and finish the etching (Fig. B (d), (e)). further,
If it is excessively etched (Fig. B (c) of the same figure), the wiring portion will be etched as shown in Fig. B (f) of the same figure. The pillar height and wiring height are likely to vary from process to process, resulting in poor process reproducibility.

On the other hand, in this embodiment, when the aluminum film is etched with a chlorine-based gas, chlorine is consumed to form a chloride of aluminum, so that it is hardly observed as a luminescent species in plasma. (Fig. A (a)). Usually LS
In the multilayer wiring structure of I, since the area ratio of the wiring in the same plane is 50% or less, as shown in FIG.
When the aluminum film is etched up to the insulating film, the amount of chlorine consumed for etching the aluminum film sharply decreases, and the emission intensity of chlorine increases in proportion to that (see
Figure A (b)). Even if etching is continued, the same figure A (f)
As shown in Fig. 3, the light emission intensity of chlorine is also constant because it is merely an overetch of aluminum (Fig. A (c) of the same figure). It can be easily detected as the end point of etching in the transition region of chlorine emission intensity in Fig. A (b). At this time, the wiring has the same thickness as the groove depth, the pillar height and width can be made constant, and the processing reproducibility is improved.

(Embodiment 2) FIG. 4 is a process explanatory diagram of a pillar forming method in a second embodiment of the present invention. In this embodiment, two wirings formed in the groove are connected to each other, and the connected portion serves as a pillar.

A BPSG film 2 is deposited on the semiconductor substrate 1, heat-treated, and photolithography is performed on the BPSG film 2 to form a groove pattern 3 of a resist for wiring (FIG. 4).
(A)). Next, the BPSG film 2 is etched to a desired depth by dry etching to form a groove 4 and the resist is removed (FIG. 4B). An aluminum film 5 is deposited on the entire surface, and a resist pattern 6'which serves as a pillar is formed on the aluminum film 5 so as to intersect adjacent grooves (FIG. 4C). The aluminum film is etched with a gas system containing chlorine (Fig. 4 (d)). The aluminum etching apparatus has a configuration capable of detecting the etching end point when the aluminum film is etched until it reaches the insulating film. After removing the resist pattern 6 ′, the pillar 7 ′ and the first wiring 8 are formed. The pillars 7'are shaped so as to intersect on the adjacent first wirings (FIG. 4 (d)).

Next, after the silicon oxide film 9 is formed on the entire surface by chemical vapor deposition (FIG. 4E), the silicon oxide film 9 is flattened by etching back or polishing until the upper portion of the pillar 7'is exposed. (Fig. 4 (f)). Further, the aluminum film 5 is deposited, and the second wiring 10 is formed by lithography and dry etching (FIG. 4G).
A perspective view of the state of FIG. 4 (d) is shown in FIG.

As described above, according to this embodiment, similarly to the first embodiment, the pillar portion and the wiring portion can be formed simultaneously,
In addition, since the insulating film is exposed when the pillar portion and the wiring portion are etched and formed, the end point of aluminum etching can be easily detected by the emission spectroscopic analysis method, so that the reproducibility of processing is improved. Further, as shown in FIG. 3 (g), since the pillar portions are formed so as to intersect with the adjacent wirings, the connection between the wirings in the same plane and the connection between the wirings in different planes are performed at the same time. It is possible to achieve high density wiring.

(Embodiment 3) FIG. 6 is a process explanatory view of a pillar forming method in a second embodiment of the present invention.

On the semiconductor substrate 1, an element isolation insulating layer 14,
Gate insulating film 13, gate electrode 12, silicide wiring 1
After forming 5, the BPSG film 2 is deposited and heat-treated, a contact hole is formed by photolithography and dry etching, and tungsten 11 is buried. Next, a silicon oxide film 9 is deposited by the chemical vapor deposition method and a resist groove pattern 3 to be a wiring is formed by photolithography (FIG. 6A). The silicon oxide film 9 is etched by dry etching until the tungsten 11 is exposed, and the resist 3 is removed (FIG. 6B).

Next, after depositing an aluminum film 5, a resist pattern 6 to be pillars is formed on it by photolithography.
Are formed (FIG. 6 (c)). The aluminum film is etched with a gas system containing chlorine (Fig. 6 (d)). The aluminum etching apparatus has a configuration capable of detecting the etching end point when the aluminum film is etched until it reaches the insulating film. At this time, the aluminum film 5 is etched in the direction perpendicular to the substrate, and as shown in FIG. 6C, the thickness h ₂ of the aluminum film in the direction perpendicular to the substrate in the step portion is flat by the step d. It becomes thicker than the thickness h ₁ of the aluminum film. For this reason,
At the time when the etching of the aluminum film on the silicon oxide film in the flat portion is completed, the aluminum etching residue 16 is generated in the step portion. In order to remove this aluminum etching residue 16,
The wiring 8 is dug down by overetching (FIG. 6E). After removing the resist pattern 6, tungsten 11 'is formed only on the pillar 7 and the wiring 8 by selective chemical vapor deposition so that the upper surface of the wiring 8 and the upper surface of the silicon oxide film 9 are aligned with each other (FIG. 6). (F)).

Next, a silicon oxide film 9 is formed on the entire surface by chemical vapor deposition, and the silicon oxide film 9 is flattened by etching back or polishing until the upper portion of the pillar 7 is exposed (FIG. 6 (g)). . Further, the aluminum film 5 is deposited, and the second wiring 10 is formed by lithography and dry etching (FIG. 6 (h)).

As described above, according to the present embodiment, even if the wiring under the pillar is dug down due to over-etching to remove the aluminum film residue on the step portion, FIG.
As shown in the step (f), by selectively depositing tungsten on the wiring and the pillar, the dug portion can be buried, and the wiring resistance under the pillar and the wiring disconnection can be prevented. Further, since tungsten can be deposited so that the upper surface of the wiring and the upper surface of the silicon oxide film are aligned with each other, the flatness of the insulating film formed on the pillar is not impaired, and the reliability of the wiring formed on the insulating film is improved. Let Also, it is possible to prevent oxidation of the aluminum pillar.

(Embodiment 4) FIG. 7 is a process explanatory view of a method for forming a multilayer wiring in a fourth embodiment of the present invention.

A BPSG film 2 is deposited on the semiconductor substrate 1 and heat-treated, and a resist groove pattern 3 to be a wiring is formed on the BPSG film 2 by photolithography (FIG. 3A). Next, the BPSG film 2 is etched to a desired depth by dry etching to form a groove 4 and the resist is removed (FIG. 2 (b)). The aluminum film 5 is deposited on the entire surface (Fig. (C)), and the aluminum film 5 is C until the upper surface of the BPSG film 2 is exposed.
The first wiring 8 is formed by polishing and flattening with MP. (Figure (d)). A resist pattern 6 serving as a pillar is formed on the first wiring 8 by photolithography, and then the first wiring 8 is formed by a gas system containing chlorine.
Is etched until the film thickness becomes about half. The resist pattern 6 is removed to form pillars 7 (FIG. 7E). Next, after the silicon oxide film 9 is formed on the entire surface by the chemical vapor deposition method ((f) in the same figure), the silicon oxide film 9 is polished and planarized by CMP until the upper portion of the pillar 7 is exposed (the same figure). (G)). Further deposit the aluminum film 5,
The second wiring 10 is formed by lithography and dry etching ((h) in the figure).

As described above, according to this embodiment, it is necessary to stop the etching during the pillar formation, but since the wiring and the interlayer insulating film are polished and flattened, it is possible to completely flatten the multilayer wiring structure. It is possible, and compared with the conventional example, the step of opening the via hole as shown in the step of FIG. 10D, the step of depositing tungsten in the via hole shown in FIG. Since the polishing step can be eliminated, throughput and yield can be improved.

In the first to fourth embodiments, the insulating film for forming the groove pattern is the BPSG film which has been subjected to the heat treatment, but the silicon oxide film, the silicon oxide film to which phosphorus is added, the silicon nitride film, the polyimide. , And other insulating films may be used. The film forming method may also be a chemical vapor deposition method, a coating method, a sputtering method, or any other method. Regarding the insulating film between the first and second wirings, the film type and the film forming method are arbitrary as in the above case. Further, as the planarization method, polishing, etchback, or other method may be used.

In the present embodiment, the first and second wirings and the pillars are made of aluminum film, but tungsten, copper,
It may be a silver, gold, or other metal film, an alloy film, a laminated metal film, a polysilicon film doped with phosphorus, arsenic, or boron, or a silicide film. The film forming method may be a sputtering method, a chemical vapor deposition method, plating, or any other method.

Although the aluminum wiring has two layers, the number of layers is not limited. Further, the second wiring was formed by depositing an aluminum film on the insulating film and performing photolithography and dry etching. However, like the first wiring, a groove pattern is formed in the insulating film, and then the wiring metal film is etched. Alternatively, it may be formed by polishing.

Although the tungsten film is formed by the selective chemical vapor deposition method in the third embodiment, other metals may be used. Metal may be deposited on the pillars and wiring by plating or other methods.

[0043]

As described above, according to the first or second structure of the present invention, the pillar can be formed with good reproducibility, the lower wiring of the pillar is prevented from being broken, the flatness of the multilayer wiring structure is improved, and the pillar is formed. Can be prevented. Further, it is possible to completely flatten the multilayer wiring structure and to reliably connect the wirings, and to improve the throughput and the yield.

[Brief description of drawings]

FIG. 1 is a process explanatory diagram of a pillar forming method according to a first embodiment of the present invention.

FIG. 2 is a perspective view of a wiring structure after pillar formation by the pillar formation method in the embodiment.

FIG. 3 (A) is a diagram showing the relationship between the etching time and the emission intensity of chlorine in the aluminum etching process in the same embodiment, and a transition diagram of changes in the wiring cross-sectional shape (B) is the etching in the aluminum etching process in the conventional example. Relationship diagram between time and chlorine emission intensity and transition diagram of change in wiring cross-sectional shape

FIG. 4 is a process explanatory diagram of a pillar forming method according to a second embodiment of the present invention.

FIG. 5 is a perspective view of a wiring structure after pillar formation by the pillar formation method in the embodiment.

FIG. 6 is a process explanatory diagram of a pillar forming method according to a third embodiment of the present invention.

FIG. 7 is a process explanatory view of a wiring forming method using CMP according to a fourth embodiment of the present invention.

FIG. 8 is a process explanatory diagram of a conventional pillar forming method.

FIG. 9 is a process explanatory diagram of a conventional pillar forming method.

FIG. 10 is a process explanatory view of a conventional wiring forming method using CMP.

[Explanation of symbols]

1 semiconductor substrate 2 heat-treated silicon oxide film containing boron and phosphorus 3 resist pattern for forming a groove 4 groove formed in an insulating film 5 aluminum film 6 resist pattern for forming a pillar 6'on adjacent grooves Resist pattern for forming crossed pillars 7 Pillars 7 ′ Pillars crossing adjacent grooves 8 First wiring 9 Silicon oxide film 10 Second wiring 11 Tungsten 11 ′ Tungsten film deposited by selective vapor deposition 12 Gate electrode 13 Gate insulating film 14 Element isolation insulating layer 15 Silicide wiring 16 Aluminum etching residue 17 Wiring-shaped resist pattern 18 Laminated film 19 Laminated wiring 20 Connection hole (via hole)

Claims (3)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of forming a groove in the first insulating film, and a metal film deposited on the first insulating film including the groove. And a step of forming a resist pattern on the metal film and etching the metal film on the first insulating film to form a metal pillar and a metal wiring, the metal pillar, the metal wiring, and the metal wiring. Forming a second insulating film on the first insulating film, and etching the second insulating film until the upper surface of the metal pillar is exposed. 2. A step of forming a first insulating film on a semiconductor substrate, a step of forming a groove in the first insulating film, and a first metal on the first insulating film including the groove. A step of depositing a film, and a step of forming a resist pattern on the first metal film and etching the first metal film on the first insulating film to form a metal pillar and a metal wiring. A step of selectively forming a second metal film on the metal wiring and the metal pillar by electroless plating or selective chemical vapor deposition, and on the second metal film and the first insulating film. And a step of forming a second insulating film and etching the second insulating film until the upper surface of the second metal film is exposed. 3. A step of forming a first insulating film on a semiconductor substrate, a step of forming a groove in the first insulating film, and a metal film deposited on the first insulating film including the groove. And a step of removing the metal film until the first insulating film is exposed to form a metal wiring, a resist pattern is formed on the metal wiring, and the metal wiring is etched to form a metal pillar. Forming a second insulating film on the metal pillar, the metal wiring and the first insulating film, and planarizing the second insulating film until the upper surface of the metal pillar is exposed. A method of manufacturing a semiconductor device, comprising: