JPH0744505B2 - Digital demultiplexer - Google Patents

Description

The present invention relates to a configuration of a digital terminal device in a PCM transmission system, and more particularly to a timing extraction circuit in a digital demultiplexing device for transmitting Gb / s information. It is about improving the feasibility of.

[Prior Art] With the progress of optical transmission technology, studies on ultra-high-speed optical transmission technology using long-wavelength optical devices / single-mode fibers have been promoted as the possibility of large-capacity / long-distance transmission systems.
In particular, in order to realize a wideband information communication network that provides a wide variety of services for images, data, and voice, it is expected that the optical transmission device will be speeded up and put into practical use in a stable manner.

The transmission capacity of the backbone transmission system in such a broadband information communication network reaches, for example, several gigabits per second in a time division multiplex transmission system, and the optical transmitter / receiver is required to have a wide band / high speed.

Usually, a digital terminal device is equipped with a transmitting / receiving transmitting device having the same function as a regenerating repeater device (see "Design and characteristics of F-400M type terminal repeater device"). Volume 32 Issue 3 (1983) P-23).

FIG. 2 shows a typical configuration of a conventional digital terminal receiving device. As an example of serial / parallel conversion function, 1: 2 conversion is used.
The reception signal received from the transmission system via the input terminal 20 is subjected to the extraction of the clock signal and the identification reproduction of the reception signal by using the clock signal in the reception device 22 as in the case of the normal intermediate reproduction relay device. The receiving device 22 is an amplifier (amplifier) 23 that amplifies a received signal, and a timing extraction circuit that plays a role of giving a time point at the center of the eye in order to perform correct discrimination with respect to an equalized waveform, generally a PCM transmission system. In this case, it is composed of a timing extraction circuit 24 that extracts a timing component from the transmitted code sequence itself, and an identification circuit 25 that identifies and reproduces the received signal based on the extracted clock signal.

The data discriminated and reproduced by the receiving device 22 and the extracted clock signal are transferred to the serial / parallel converter 26 (“demultiplex converter”).
Also called). In the serial / parallel conversion unit 26, the clock signal input from the receiving device 22 is divided by a 1/2 divider circuit 27.
At 1 :, the clock signal is converted into a two-phase clock signal with a half cycle required to perform 1: 2 serial / parallel conversion and a phase shift of 180 °. Further, the two-phase clock signals are supplied to the latch circuits 28-1 and 28-2 which perform serial / parallel conversion.

On the other hand, the received signal discriminated and reproduced by the discriminating circuit 25 of the receiver 22 is transferred to the latch circuits 28-1 and 28-2 of the serial / parallel converter 26.
Serial 2CH time-division-multiplexed on the transmission side by the branched and input clock signal supplied from the 1/2 divider circuit 27
Of the (channel) signals, 1CH is latched and output to each output terminal 21-1, 21-2.

FIG. 3 is a block diagram of a conventional timing extraction circuit. NRZ (Non Return to Zero) code is assumed as the code format of the input signal. Since the NRZ code, the bipolar code, etc. do not have the timing component themselves, generally, the timing signal is extracted by the non-linear timing extraction method to generate the clock signal.

In FIG. 3, the NRZ signal input to the input terminal 30 is subjected to the sign change point detection in the differentiating circuit 32, and the both-wave rectifying circuit 33 performs the both-wave rectification to extract the f ₀ component. The output signal of the both-wave rectification circuit 33 is further applied to the resonance circuit (timing tank) to extract the f ₀ sine wave component (clock signal). As the resonance circuit, since the timing deviation is regarded as an important characteristic, a surface acoustic wave filter (SAW) 34 having a relative band Q of about 800 is used in consideration of temperature characteristics, aging, detuning, etc. (Reference: "Surface wave device and its application", Nikkan Kogyo Shimbun). On the other hand, when the code format of the input signal is RZ, since the signal itself has a clock component, the input RZ signal is directly applied to the surface acoustic wave filter 34 to extract a sine wave clock signal.

[Problems to be Solved by the Invention]

However, in such a conventional digital demultiplexer, a clock signal extracted at a frequency f ₀ synchronized with a data transmission rate by using a SAW filter having a high Q in a receiver is 1 / N in a serial / parallel converter. Since the signal processing for frequency division is performed, there is a defect that characteristics of the clock signal are deteriorated.

In addition, a surface acoustic wave filter is used as a timing extraction circuit in the receiving device, that is, a timing tank, and
In the form of directly generating the clock signal of the f ₀ component in the z region, there are problems that the usable frequency region is limited due to the problem of fine processing of the surface acoustic wave filter, and the process yield decreases. PCM using
There is a drawback that it also leads to a decrease in the productivity of the signal receiver.

That is, the fundamental frequency f of the surface wave excited in the surface acoustic wave filter is determined by the surface wave propagation velocity V of the material and the electrode pitch L, and f = V / L. Therefore, when the excitation frequency is in the GHz range, the surface wave propagation velocity is generally 3 × 1
Since it is 0 ³ (m / s), the electrode width must be 1 μm or less. As a specific example, the electrode width of the surface acoustic wave filter used in the 4 Gbps optical regenerator is 0.2 μm using a quartz substrate as the material and 400 μm as the electrode length.
m (Ref: “Prototype of 4 Gbps Optical Regenerator” Proceedings of IEICE, 1987 General Conference). In order to accurately process such an electrode width, it is difficult to realize a surface acoustic wave filter because processing technologies such as photo etching and laser processing have limitations, and it is difficult to realize a PCM signal receiver in the Gbps region. There was a big problem that the timing extraction circuit could not be realized.

An object of the present invention is to provide a digital demultiplexer that solves such a problem.

[Means for Solving the Problems]

The present invention discriminates and reproduces a received signal and further reproduces the signal
In a digital demultiplexer for parallel conversion, a first timing extraction filter that extracts a basic timing component from the received signal that is input, and a frequency division that divides the output signal of the first timing extraction filter into 1 / N. A circuit, an OR circuit that performs an OR operation with the output signal of the frequency divider circuit as one input signal and the other input signal, and a stable timing signal of 1 / N frequency from the output signal of the OR circuit. A second timing extraction filter for extracting, and an (N + 1) -phase and 1 / N frequency clock optimal for performing serial / parallel conversion from the 1 / N frequency timing signal extracted by the second timing extraction filter. A clock distribution circuit that distributes a signal, and a predetermined delay time for the (N + 1) th signal output from the clock distribution circuit to input the other input to the OR circuit. Is characterized a delay circuit for input that is composed of said regenerating and S / P conversion circuit for performing the serial / parallel conversion at the same time of the 1 / N frequency of the received signal at the clock signal as No..

[Action]

After extracting the coarse timing component from the input signal and dividing the coarse timing component into the frequency range of 1 / N, the clock signal is generated at highly stable timing and the clock signal is supplied to the serial / parallel converter. Further, by omitting the identification circuit in the receiving device and adopting a configuration in which the latch circuit of the serial / parallel conversion unit is also used, the feasibility of the timing extraction circuit in the GHz region is improved and the characteristic deterioration of the clock signal is avoided. It is possible to reduce the device scale.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital demultiplexer which is an embodiment of the present invention. In the description below, the RZ (return to zero) code is assumed as the code format of the received signal.

This digital demultiplexer includes an amplifier 12 for amplifying a received signal and a first timing extraction filter for extracting a basic timing component f ₀ from an input received signal.
13 and the output signal of the first timing extraction filter 13
Stable from the frequency divider circuit 14 that divides to N, the OR circuit 15 that uses the output signal of the frequency divider circuit 14 as one input signal to perform the OR operation with the other input signal, and the output signal of the OR circuit 15. Na 1 /
A second timing extraction filter 16 for extracting a timing signal of N frequency, and an (N + 1) phase optimum for performing serial / parallel conversion from the timing signal of 1 / N frequency extracted by the second timing extraction filter, and A clock distribution circuit 17 that distributes a clock signal of 1 / N frequency, and a (N + 1) th signal output from the clock distribution circuit 17 is given a fixed delay time and input to the OR circuit 15 as the other input signal. It comprises a delay circuit 18 and N latch circuits 19-1 to 19- _n for simultaneously performing identification / reproduction and serial / parallel conversion of a received signal with a clock signal of 1 / N frequency.

A resonance circuit (timing tank) is used as the first timing extraction filter 13 and the second timing extraction filter 13 is used.
A surface acoustic wave filter (SAW filter) is used as the resonance circuit (timing tank) for 16.

In the digital demultiplexer having the above-described structure, the RZ reception signal input to the input terminal 10 is sufficiently amplified by the amplifier 12 and then supplied to the latch circuits 19-1 to 19- _n and the first timing extraction filter 13. Is applied.

In this first timing extraction filter 13, the input
A clock signal synchronized with the basic timing frequency f ₀ is extracted from the RZ reception signal with coarse accuracy. Therefore, as the timing tank to be used, the relative bandwidth Q that can extract a clock signal that does not affect the timing jitter amount is used.
A filter having (about 500 or less) may be used.

The clock signal of the coarse f ₀ component extracted by the first timing extraction filter 13 is counted down by the 1 / N frequency dividing circuit 14 at an arbitrary frequency division ratio. As the frequency division ratio of the frequency dividing circuit 14, a ratio matching the time division multiplicity N is used.

The clock signal f ₀ / N divided into 1 / N by the 1 / N divider 14 is
It is input to the OR circuit 15. The logical sum circuit 15 performs logical sum processing of the signal input from the delay circuit 18 and the signal input from the 1 / N frequency dividing circuit 14 to generate an output signal. Now, assuming the initial as a time process, the delay circuit
Since the signal from 18 is no signal, as the output signal of the OR circuit 15, the signal of the f ₀ / N component in which the signal component input from the 1 / N frequency dividing circuit 14 is dominant is output. It The output signal of the OR circuit 15 is the second timing extraction filter.
Entered in 16.

The center frequency of the second timing extraction filter 16 is
It is necessary to set f ₀ / N, and set a high specific bandwidth Q in consideration of timing deviation, detuning, and the like. In particular, considering the secular change and temperature characteristics, it is desirable to use the surface acoustic wave filter (SAW filter) as the timing tank as described above.

Now referring to FIG. 1, the basic timing frequency f ₀ is 4 GHz,
If the division ratio is 8, f ₀ / N is 500 MHz. When the second timing extraction filter 16 is a surface acoustic wave filter made of quartz, the surface acoustic wave wavelength is about 6.3 μm. If the strip width and the gap of the interdigital electrodes are selected to be equal, the strip width is about 1.6 μm, and such an electrode pattern can be formed by a usual photoetching technique.

The clock signal of f ₀ / N having a stable characteristic extracted by the second timing extraction filter 16 is supplied to the clock distribution circuit 17. In this clock distribution circuit 17, from the input signal, (serial / parallel conversion number + 1), that is, (N + 1)
Clock signals whose phases are shifted by T / N (T: 1 cycle time) are generated, and the Nth clock signals are supplied to the latch circuits 19-1 to 19- _n , respectively. The (N + 1) th signal is input to the delay circuit 18 and given a certain delay, and then supplied to the OR circuit 15. Therefore, the output signal of the OR circuit 15 is the stable f ₀ / N clock signal input from the delay circuit 18 and the first timing extraction filter.
The f ₀ / N clock signal as a result of performing the logical sum processing with the signal obtained by dividing the coarse f ₀ component clock signal from 13 by 1 / N is output.

In the latch circuits 19-1 to 19- _n , the received signals respectively input are latched by this clock signal and output terminals 11-1 to 11-n.
Output from 11- _n . Therefore, at this stage, the received signal identification processing and the serial / parallel conversion processing are simultaneously satisfied.

In this way, the high Q surface acoustic wave filter necessary for timing extraction is used in the region of the 1 / N frequency division ratio, whereby the feasibility of the timing extraction circuit of the high-speed PCM signal transmission system is improved. An improved and stable clock signal can be supplied to the serial / parallel conversion circuit.

In the above description, the case where the code format of the received signal is RZ has been described, but the present invention is also effective in the case of NRZ, and the differentiating circuit 32, as in the conventional example shown in FIG.
The same function can be obtained by connecting to the input terminal 10 of FIG. 1 after passing through the non-linear means of the double-wave rectification circuit 33.

〔The invention's effect〕

As described above, the use of the digital demultiplexer according to the present invention improves the feasibility of the timing extraction circuit in the high-speed PCM signal transmission system, the stabilization of the serial / parallel conversion function, and the simplification of the device configuration. .

[Brief description of drawings]

 FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are views for explaining a conventional example. 10 …… Input terminal 11 …… Output terminal 12 …… Amplifier circuit 13 …… First timing extraction filter 14 …… 1 / N frequency divider circuit 15 …… OR circuit 16 …… Second timing extraction filter 17 …… … Clock distribution circuit 18 …… Delay circuit

Claims (1)

[Claims] 1. A digital demultiplexing device for identifying and reproducing a received signal and further serial / parallel converting the received signal, a first timing extraction filter for extracting a basic timing component from the input received signal, and the first timing extraction filter. A divider circuit that divides the output signal of the timing extraction filter into 1 / N, and an OR circuit that performs an OR operation with the output signal of the divider circuit as one input signal and the other input signal, A second timing extraction filter for extracting a stable timing signal of 1 / N frequency from the output signal of the OR circuit, and serial / parallel conversion from the timing signal of 1 / N frequency extracted by the second timing extraction filter A clock distribution circuit that distributes a clock signal of (N + 1) -phase and 1 / N frequency, which is optimum for performing the clock, and an (N + 1) th signal output from the clock distribution circuit. A delay circuit for giving a constant delay time and inputting to the OR circuit as the other input signal, and a serial / parallel converter for simultaneously performing the identification reproduction and the serial / parallel conversion of the received signal with the clock signal of the 1 / N frequency. A digital demultiplexer comprising a parallel conversion circuit.