JPH0744412A - Computer system - Google Patents

Abstract

PURPOSE:To realize a computer system in which the deterioration in the performance due to addition of a checker CPU is prevented in the highly reliable computer system adopting multi-CPUs. CONSTITUTION:A master CPU 110, a system controller (SCU) 130 and a comparator 100 are connected to a master processor bus 140. A checker CPU 120 implementing the same processing as that of the master CPU 110 to check the operation of the master CPU 110 is connected to the comparator 100 by a checker processor bus 150. The SCU 130 controls the access from the master CPU 110 to a main storage device 170 and an input output device 190. The comparator 100 compares the processing results outputted from the master and checker CPUs and provides the output of different processing result to the SCU 130 when the processing results differ. Since the data transfer between the master CPU 110 and the SCU 130 does not slow down because the data do not pass through the comparator 100.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a master central processing unit (C
PU) and a checker central processing unit, and a highly reliable computer system by multiplexing the central processing units, and particularly small and high performance in which the central processing unit and the system control unit (SCU) are composed of one-chip VLSI. Computer system. Furthermore, the present invention relates to a highly reliable computer system of a master checker type in a multiprocessor.

[0002]

2. Description of the Related Art There have been many techniques for improving the reliability of computer systems, for example, the Institute of Electronics, Information and Communication Engineers Vol. 7
3, No. 11 (November 1990) pp. 1135-
1245 “Special Issue on Fault Tolerant Systems”. Among them, the method of detecting inconsistency by multiplexing CPUs compares the processing results output from a plurality of central processing units, and when the processing results differ, the SCU
It is classified into the following three types depending on the place where the comparison device for outputting that the processing result is different is placed in the (control device).

The first method is to place the comparison device between the CPU and SCU. A conventional example of this method is a majority circuit of a fault tolerant computer (FTC). In the case of the majority circuit, there is no distinction between the master and the checker, and the outputs of three CPUs performing the same operation are compared, and if two of them are the same, it is output to the SCU. In this method, all the CPUs are connected to the comparison device, and all the CPUs operate at the same timing (FIG. 3).

In the second method (FIG. 4), in order to connect the checker directly to the processor bus, the normal mode and the checker mode are built in the microprocessor in advance, and the mode is designated by an external signal. In the checker mode, data is received from the processor bus but not output, so that when the master and the checker are operated at the same timing, output data from both are prevented from colliding. Since the output of the checker cannot be output to the outside in this way, the comparison device is placed inside the checker. This method is used in some microprocessors (reference above). Even in this method, all CPUs operate at the same timing.

The third method is to use two processor buses 51,
52 into one SCU 55, and the processor bus 5 to the comparator 57 and other parts of the SCU inside the SCU.
1, 52 are branched. Then, the comparison device 57 is set to S
This is a system built into the CU55. As a conventional example that adopts this method, a dual system is available (FIG. 5). Even in this method, all CPUs operate at the same timing. Although the SCU is also duplicated in the example of FIG. 5, the SCU is not duplicated in the present invention.

On the other hand, in Japanese Patent Application Laid-Open No. 58-18756, even if input data is given to the master and checker CPUs at the same time, the output timings of these two CPUs vary greatly, and the output is performed at a constant timing from the time of input. A technique for a CPU, which is difficult to compare even by comparing In the reference, for the input data to the master and the checker, the signal for reading (read signal) output by the master is used, and for the master, the signal is fetched according to the signal, and for the checker, the data is read from the master. The signal is latched in the data register RDR by the above signal, and then the same data is surely input to the master and the checker by fetching it from the data register RDR to the checker by the signal for fetching from the checker. Therefore, the checker is operated later than the master. Regarding the comparison of the outputs of the master and the checker, when the output of the master is surely output, the write data register WDR (in the case of write data) is latched by the signal from the master, and the output of the latch is sent to the comparison circuit.
The checker output that is output with a delay is sent directly to the comparison circuit, and the comparison circuit output is reliably compared by latching it in the register with the signal from the checker when the output from the checker is surely output. Get results. In this way, the difference in the operation timing between the two is absorbed. The present invention was conceived so that a duplication check can be performed even by a microprocessor whose operation timing is originally unclear.

[0007]

In the above-mentioned first to third conventional master checker systems, when the master CPU fails, the checker CPU performs the proxy operation,
At that time, the emphasis was placed on continuing the processing without degrading the system performance.
It was supposed to operate the PU at exactly the same timing. Therefore, the conventional technique has the following performance deterioration factors as compared with the system without the checker.

In the first method of the conventional example, the data on the master side also passes through the comparison device, so that the SC can be compared to the case without the comparison device.
Access to U is slow and performance is degraded.

In the second method of the conventional example, since a plurality of CPUs are directly connected to the processor bus, the fan-out of the bus is proportional to the number of CPUs (two in FIG. 4). The fanout gets bigger,
The operating frequency of the bus cannot be increased and the performance deteriorates. Further, as described above, it is necessary to incorporate the checker function in the processor in advance.

In the third method of the conventional example, two processor buses 51 and 53 are pulled to one SCU 55, so that the number of signal lines is doubled as compared with the case of one processor bus. The cost is too high except for a large-scale computer that is configured by dividing the CPU or SCU into many LSIs. In the case of a multiprocessor, if the master and checker cannot be mounted on one board, for example, SCU
If the board 55 and the CPU 58 are different boards, the processor bus 52 becomes long and the wiring delay becomes large. Therefore, since the signal from the CPU 58 is delayed compared with the signal from the CPU 57, it is necessary to match the operation with the signal from the CPU 58. As a result, it is difficult to increase the operating frequency.

By the way, it is important to detect a failure of master / checker mismatch, and when a failure occurs, the performance of the system may be reduced, or even if one system is brought down, recovery may be performed by hot standby or the like. In that case, since the processing performance is reduced by adopting the master checker system, the performance is lower than that of the system without the checker, or a higher performance, large-scale CPU is installed to obtain the same performance. I had to do it.
Therefore, the performance of the master checker system was low relative to the scale, resulting in poor cost performance.

On the other hand, in the configuration of Japanese Patent Laid-Open No. 58-18756, the output of the master is latched and then compared, so that it is considered that there is a delay similar to the first method. Further, in this example, the configuration in which the CPU and the SCU are connected by the processor bus is not described, and the following is not considered.

In the case where the CPU and the SCU are connected by a processor bus, data transmission / reception uses a common data line, and the bus (data line) usage right is switched between them. That is, the data output by both parties are mixed on the bus. For this reason, if only the data from the master CPU is sent to the comparison circuit and only the data from the SCU is sent to the checker CPU separately for the data on the bus, the comparison will be executed with erroneous data. It is considered that the data from the master CPU and the data from the checker CPU cause data collision.

An object of the present invention is to provide a computer system having a checker function and having a performance equivalent to that of a system without a checker.

[0015]

According to the present invention, in order to solve the above problems, a master central processing unit and the same processing as the master central processing unit are performed in parallel, and the operation of the master central processing unit is checked. Check central processing unit,
A main memory accessed by the master central processing unit;
An input / output device accessed by the master central processing unit;
At least the main storage device, the input / output device, and the master central processing unit, which are interposed between the master central processing unit and the control unit for controlling the access, and the processing results output from the master and checker central processing units are compared and processed. When the results are different, a comparison device that outputs a different processing result to the control device, a master side processor bus that connects the master central processing device, the control device and the comparison device, and the checker center A checker-side processor bus that connects the processing device and the comparison device is provided, and the checker central processing device is connected to the control device, the main storage device, and the input / output device via the comparison device. It was decided to be done.

Further, when some of the checker central processing units are not operating, a holding unit for holding information for identifying the operating checker central processing unit, and an operating unit based on the information. It has a selector for sending the data output from the master central processing unit corresponding to the non-checker central processing unit to the checker side processor bus.

[0017]

According to the present invention, in order to realize a high-performance master checker system, the master CPU and the SCU are directly connected, and the checker CPU is connected through the comparison device.

Since the data on the master CPU side does not pass through the comparison device, the access to the SCU does not slow down. Also, S
The number of CU signal lines does not increase.

The fan-out of the processor bus is increased by the number of comparison devices as compared with the system having no checker, but even when this configuration is applied to a multiprocessor,
Since the processor bus is separated on the master side and the checker side, the fanout does not become twice the number of CPUs,
The operating frequency of the bus can be increased. Therefore, the above problems can be solved.

Further, since it is not necessary to incorporate the comparison device in the processor, the master checker system can be realized by a commercially available multiprocessor.

When data is sent from the SCU to the checker CPU side, it passes through the comparison device, so if it cannot be sent at the same timing as the master CPU side data, the checker CPU
It is possible to maintain the synchronization with the master CPU side by delaying the operation timing of 1) from the master CPU by a certain time.

When this configuration is made into a multiprocessor, the present invention also enables the following.

In a multiprocessor, particularly a shared memory type multiprocessor sharing a main memory, since the same data is accessed by a plurality of CPUs, it is necessary to control the coherency of the cache memories. Coherency control refers to the contents of a cache having the same address as the address rewritten between the caches of each processor when any processor writes to the main memory via the cache. Refers to the matching control. For this purpose, each CPU constantly monitors (snoops) the processor bus and performs processing while checking the address. Therefore, when a failure occurs in a checker CPU and the cause of the failure is investigated as a part of the failure processing, it is necessary to write back the cache contents of the corresponding master CPU to the main memory. At this time, snooping is correctly performed between the master CPUs and the cache is rewritten correctly, but between the checker CPUs, correct data may not be output from the checker CPU in which the failure has occurred. Snooping may be performed and rewriting of the incorrect cache may be performed. Therefore, as it is, the consistency of the contents of the cache memory cannot be guaranteed between the other normal master CPU and the other normal checker CPU, and the process cannot be restarted unless all the normal CPUs are reset.

In order to solve this problem, in the selection device that sends data to the checker side bus of the comparison device, the SC
The checker CPU in which the failure occurred in addition to the data from U
The data from the master CPU corresponding to is selectively sent to the checker side bus, and the checker side may perform snooping based on this data.

As described above, by selectively sending the data of the master CPU in which the corresponding checker has failed to the checker side bus, the cache memories of the master side and the checker side are made coincident, and only one checker has failed. The system does not stop at.

In the case of the present invention, the processing performance in the proxy operation of the checker alone is lower than that in the master side, but the performance in the normal operation, which occupies the overwhelming part of the system operation time, is the same as that of the system without the checker. Can be realized,
Cost performance is greatly improved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIGS.

FIG. 1 is a diagram showing the basic configuration of a master checker type computer system according to the present invention. This system includes a master CPU 110 and a comparison device (CMP) 100.
A master side processor bus 140, a system control unit (SCU) 130, a checker CPU 120,
Checker-side processor bus 150 and memory bus 180
And a main memory (MS) 170 and an I / O bus 200
And an input / output device (I / O) 190. Master C
The PU 110 and the comparison device (CMP) 100 are connected to the system control unit (S) via the master side processor bus 140.
CU) 130. Checker CPU120
Is the CMP 10 via the processor bus 150 on the checker side.
It is connected to 0. An error signal 160 is connected from the CMP 100 to the SCU 130. A main memory unit (MS) 170 is connected to the SCU 130 via a memory bus 180.
Through the I / O bus 200, but an input / output device (I / O) 1
90 is connected.

The SCU 130 responds to the read / write request from the master CPU 110 by the MS 170 and I / O.
Read / write to 190.

FIG. 2 is a diagram showing the internal structure of the comparison apparatus (CMP) 100. Master bus buffer register (MB
BR) 101 latches the data on the processor bus 140 on the master side. Selector (SEL) 105 is MBBR
Of the data once latched at 101, the data output by the SCU 130 is selected by the signal line 1051 to the checker side processor bus 150, and the data output by the master CPU 110 is selected by the signal line 1052 to the master bus compare register (MBCR) 102. Output. The MBCR 102 latches the data once latched by the MBBR 101. The checker bus compare register (CBCR) 103 is a processor bus 150 on the checker side.
Latch the above data. Comparator 104 is MBCR10
2 and the contents of the CBCR 103 are compared, and if they are not equal, the SCU 130 is notified by the error signal 160.
Report to. The MBBR 101 is a delay circuit that delays the operation timing at which the checker central processing unit performs processing from the operation timing at which the master central processing unit performs processing by a predetermined time.

The data on the processor bus has CP
Data valid (Valid) signals from U and SCU are attached and each device connected to the bus (comparator C
MP), including 100), knows which device is outputting data on the bus.

In this embodiment, the operation cycle of the master and checker processor buses is twice the machine cycle of the master and checker CPU, and the operation delay of the checker CPU from the master CPU is one processor bus cycle.

The comparison timing of the comparison device (CMP) 100 will be described with reference to FIG. In the processor bus cycle 1, the master CPU 110 executes the i-th step and the checker CPU 120 executes the i-2th step. In this cycle, write data (“0000111” in the figure) to the MS 170 is written on the master side processor bus 140.
1 ") is output.

CMP100 in processor bus cycle 2
The MBBR 101 therein latches the data on the bus 140. The SCU 130 uses the bus 1 as a buffer in the SCU 130.
Latch the data on 40 and issue a write request to MS 170. The checker CPU 120 operating one processor bus cycle behind the master CPU outputs write data on the checker side processor bus 150 in this cycle.

In processor bus cycle 3, since the master side data is from the master CPU 110, MB
It is sent from the BR 101 to the MBCR 102 through the SEL 105. The checker side data is latched by the CBCR 103.

MBCR 10 in processor bus cycle 4
2 and the contents of CBCR 103 are compared by comparator 104, and if they do not match, they are reported to SCU 130 by error signal 160. When an error is reported, the SCU 130 inhibits writing to the MS 170, which is executed in processor bus cycle 6. If no error is reported, writing to MS 170 is performed.

Next, the data read from the MS 170 is converted into C
The operation of sending to the PU will be described with reference to FIG. MS17
Data read from 0 (“888889999” in the figure)
Is latched in the buffer in the SCU 130 in the processor bus cycle 1. At this time, the master CPU 110 and the checker CPU 120 are waiting at the i-th step due to waiting for data.

SCU 130 uses processor bus cycle 2
Output to the master side processor bus 140.

Master CPU in processor bus cycle 3
110 latches the data on the master-side processor bus 140 and restarts the processing. MBBR1 in CMP100
01 latches the data on the bus 140, and the SCU 130
Since it is from the above, the data is directly output to the checker side processor bus 150 through the SEL 105.

In processor bus cycle 4, checker CP
The U120 latches the data on the checker side processor bus 150 and restarts the processing.

Next, the operation of the control signal of the CPU will be described with reference to FIG. In this embodiment, the control signal is also included in the processor bus and is synchronized with the processor bus cycle. When the control signal is sent to the comparison circuit in the CMP 100 like the data, the control signal is compared and the timing is delayed by being latched. . Here, the reset of the CPU will be described. The reset signal is output from the SCU 130. In the processor bus cycle 1, the reset signal is issued, and the master CPU 110 and the checker CP are
U120 is in the initial state.

In the processor bus cycle 2, the reset signal in the processor bus 140 on the master side is released, and the master CPU 110 starts processing.

In the processor bus cycle 3, the reset signal in the checker side processor bus 150 is released, and the checker CPU 120 starts processing. Master CPU 11
0 issues a read request from address 0 to the master side processor bus 140.

Check CP in processor bus cycle 4
U120 issues a read request from address 0 to the checker side processor bus 150.

Next, the second embodiment will be described. This is an embodiment in which the checker can perform the substitute operation. Figure 6
FIG. 6 is a diagram showing a configuration of a master checker type computer system in a second embodiment. A master side control signal 1301 and a checker side control signal 1061 which are not synchronized with the processor bus are added to FIG. Other configurations are the same as those in FIG.

FIG. 7 shows a comparison device (C in the second embodiment).
FIG. 3 is a diagram showing an internal configuration of MP) 1001. 2, the timing delay circuit (DLY, synchronous circuit) 106, the master side control signal 1301, the checker side control signal 106
1, CBCR 103 to master side processor bus 140
A route 1031 for sending data to the checker CPU, and a selector 1032 for sending data from the CBCR 103 to the master side processor bus 140 only when the checker CPU performs a surrogate operation.
(A connection circuit for connecting the checker side processor bus and the master side processor bus) is added. Other configurations are the same as those in FIG.

In the MBBR 101, when a failure occurs in the master central processing unit and the checker central processing unit operates as a substitute for the master central processing unit, the operation timing of the checker central processing unit is set to the master central processing unit. Is a delay circuit that delays the operation timing by a certain time from the operation timing when was operating.

First, a fixed failure occurs in the master CPU,
The operation when the checker CPU performs the substitute operation will be described. The processing when a comparison error occurs between the master and checker, the recovery processing from the failure, and the like are the same as those in a normal master checker system, and therefore description thereof is omitted.

FIG. 11 shows the operation timing of data writing from the checker CPU. It is assumed that the checker CPU 120 outputs write data to the checker side processor bus 150 in the processor bus cycle 1.

In processor bus cycle 2, write data is latched by CBCR 103 and route 103
1 to the master side processor bus 140.

SCU 130 in processor bus cycle 3
Latches the data on the bus 140 in the buffer in the SCU 130 and issues a write request to the MS 170.

As described above, the 1-bus cycle timing is delayed as compared with the case where the master CPU outputs data.

The timing of reading and resetting data is the same as when the master CPU is operating (the checker CPU is delayed by 1 bus cycle from the original timing of the master CPU).

Next, a control signal not synchronized with the processor bus, such as an interrupt signal, will be described.

As the master side control signal 1301 in the CMP 1001, the control signal given to the master CPU 110 is given at the same timing. 1 for DLY105
The timing of the control signal 1301 is delayed by the processor bus cycle, that is, the delay of the checker CPU with respect to the master CPU, and is output to the checker side control signal 1061. As a result, the input timing of the control signal with respect to the operation step of the CPU becomes equal, and the master and the checker CPU are not out of synchronization.

A third embodiment of the present invention will be described with reference to FIGS.

FIG. 12 is a diagram showing the basic configuration of a master checker type computer system when the present invention is applied to a multiprocessor. The master CPUs No. 0111, No. 1 112, No. 2 113, and No. 3 114 are connected to the master side processor bus 140, and the checker CPU No. 121, No. 1
The number 122, the second number 123, and the third number 124 are connected to the checker side processor bus 150, respectively. Checker CPU No. 1 to master CPU No. 111
21 performs the same operation with a delay of one bus cycle (master C
The PU CPU No. 112 is the checker CPU CPU No. 122, and so on). Although the number of processors is four in this embodiment, the number of processors is not essential in the present invention.

FIG. 13 is a diagram showing board mounting of this embodiment. Master CPU No. 0 to No. 3 111 to 114 and SC
The U 130 is mounted on the master side processor board 240, and the checker CPU Nos. 0 to 3 121 to 124 are mounted on the checker side processor board 250.

FIG. 14 shows a comparison device (CM
(P) is a diagram showing a configuration of 1002. 2, the processor ID (identification number) holding register (PID) 107
Has been added. The PID 107 holds the processor ID of the currently operable checker CPU, and the SEL 105 selects the data to be sent to the checker side bus 150 based on this value. In this embodiment, the checker CPUs 0th to 3rd
All the numbers 121 to 124 are operable, and "0",
The values “1”, “2”, and “3” are held in the PID 107. The SEL 105 sends the data output from the master CPU Nos. 0 to 3 111 to 114 on the master side bus to the comparator 104 and the data output from the SCU 130 to the checker side bus 150, respectively.

Among the components of the comparison device (CMP) 1002, the MBBR 101 is the master side processor board 240.
The other MBCR 102, CBCR 103, comparator 104, SEL 105, PID 107, etc. are mounted on the checker side processor board 250. That is, CMP1
00 is divided and mounted on two boards. The two boards are connected by the output signal 109 of the MBBR 101. Error signal 160 is SCU1 across two boards
Report error to 30.

The operation timing in this embodiment is basically the same as that in the first embodiment. FIG. 1 shows the comparison timing of the comparison device (CMP) 1002 in the multiprocessor configuration.
5 will be described. In the processor bus cycle 1, the master CPU No. 0111 is the master side processor bus 14
It is assumed that the request is read out to 0 and issued. In the processor bus cycle 2, the checker CPU No. 121 outputs a read request to the checker side processor bus 150,
The CMP 1002 compares the request issuer CPU number and the request content.

Master bus in processor bus cycle 3
It is assumed that the first number 112 issues a read request to the master side processor bus 140. In the processor bus cycle 4, the checker CPU No. 1 122 issues a read request to the checker side processor bus 150, and the CMP 10
02 compares both.

In this way, the comparison device (CMP) 1002 compares the request issue source CPU number and the request contents, and thus the master checker operation in the multiprocessor configuration is possible.

Next, the operation when a failure occurs in the checker CPU will be described. As described above, in the multiprocessor, since the same data is accessed by a plurality of CPUs, it is necessary to control the coherency of the cache memory, and each CPU always performs processing while snooping the processor bus. Therefore, when a failure occurs in a certain checker CPU and the cache content of the corresponding master CPU is written back to the main memory as part of the failure processing, correct data may not be output from the failed checker. As it is, there is a problem that the consistency of the contents of the cache memory cannot be guaranteed between the other normal master CPU and the other normal checker CPU, and the processing cannot be restarted unless all the normal CPUs are reset.

It is assumed that the checker CPU No. 0121 has a failure. In this case, of the values “0”, “1”, “2”, and “3” held in the PID 107, “0”
To reset. With this, the data from the checker CPU 121 becomes invalid, and the SEL 105 sends the data from the master CPU No. 0111 to the checker side bus 150 in addition to the data from the SCU 130. As a result, the checkers No. 1 122 to No. 3 124 can perform coherency control by using the data of the master CPU No. 0111 which has not failed, and the master CPU No. 1 112 to
The contents of the cache memory can be kept the same between the third and 114th.

By utilizing the above-mentioned function, it can be realized even when the number of checker CPUs is smaller than the number of master CPUs in the multiprocessor configuration. This is obvious if the checker CPU is disconnected from the beginning in the above example. This makes it possible to realize a cost-effective master checker system by selectively using dual CPUs and non-duplicated CPUs in a multiprocessor system.

A fourth embodiment of the present invention will be described with reference to FIG. FIG. 16 shows the processor ID of the checker CPU as S.
It is the figure which made it possible to designate dynamically from CU. In a normal operation state, the processor ID designation signal 210 gives the checker CPU 121 a processor ID “0”, and similarly, the designation signal 211 gives a checker CPU 122 a “1”, the designation signal 212 gives a checker CPU 123 a “2”, a designation signal. Checker CPU124 by 213
"3" is designated for each.

In this state, the master CPU No. 0-11
1 and the checker CPU No. 1222 has a fixed failure. In this case, after the fault processing is completed, the processor ID designation signal 210 is used to re-designate the processor ID “1” to the checker CPU 121, and the processing is restarted to reduce the number of failed CPUs from two to one. Therefore, it is possible to minimize the deterioration of the processing performance.

If a fixed fault occurs in the master CPU No. 0111 and the checker CPU No. 122 in a system with two CPUs, the processing cannot be continued as it is. By redesignating the processor ID “1” to the checker CPU 121 by 210, the processing can be restarted and the system down can be prevented.

The fifth embodiment of the present invention is shown in FIGS.
Will be explained. FIG. 17 is a diagram in which the present invention is applied to a triple multiprocessor. The second set of checker CPUs 125 to 128 is added to the second embodiment and is connected to the comparison device (CMP) 1003 by the second set of checker-side processor buses 1502.

Comparative apparatus (CMP) 10 in this embodiment
The basic internal structure of No. 03 is shown in FIG. In contrast to FIG. 2, there are two sets of checker bus compare registers and comparators.

(CBCR1031, CBCR1032 and comparator 1041, comparator 1042). OR circuit 104
3 is SC by the error signal 160 when a mismatch is detected by either the comparator 1041 or the comparator 1042.
Report to U130.

The operation timing in this embodiment is exactly the same as that in the second embodiment. The two sets of checker CPUs perform the same operation with a delay of one bus cycle with respect to the master CPU.

The sixth embodiment of the present invention will be described with reference to FIG. In this embodiment, a comparison device (CM
P) 1004 built-in, checker side processor bus 15
0 is directly connected to the SCU. Also in this embodiment, the checker CPU performs the same operation with a delay of one bus cycle with respect to the master CPU.

In the sixth embodiment of the present invention, the number of signal lines connected to the SCU is increased by the processor bus on the checker side as compared with the other embodiments, but the conventional master C
Compared to a system in which the PU and the checker CPU operate at the same timing, the checker CPU can operate even at a delayed timing, so that board mounting conditions such as wiring delay from the checker CPU and clock skew are alleviated.

[0076]

According to the present invention, the master CPU and the SCU
Since the comparison device does not enter during the period, there is no delay in processing for passing through the comparison device. Further, in the system in which the comparison device is built in and the checker CPU is connected to the processor bus, the fanout of the bus increases in proportion to the number of processors (double in the case of one set of checkers). The fan-out of 1 increases by one comparator, but the fan-out does not increase even if the number of processors increases, and the bus speed can be increased. As described above, according to the present invention, a compact and high performance master checker type computer system can be realized.

When the present invention is applied to a multiprocessor, a high performance master-checker type computer system can be realized and a flexible configuration can be adopted when a failure occurs by switching the processor ID of the checker CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a master checker type computer system according to the present invention.

FIG. 2 is a block diagram of a first embodiment of a comparison device according to the present invention.

FIG. 3 is a block diagram showing a conventional example in which a comparison device is placed in the middle of a processor bus.

FIG. 4 is a block diagram showing a conventional example in which a comparison device is incorporated in a checker CPU.

FIG. 5 is a block diagram showing a conventional example in which a two-pull comparison device with a processor bus is incorporated in an SCU.

FIG. 6 is a block diagram showing the configuration of a second embodiment of a master checker type computer system according to the present invention.

FIG. 7 is a block diagram showing the configuration of a second embodiment of the comparison device according to the present invention.

FIG. 8 is a timing chart showing a comparison timing of write data in the first embodiment of the present invention.

FIG. 9 is a timing chart showing the transfer timing of read data to the checker CPU in the first embodiment of the present invention.

FIG. 10 is a timing chart showing the timing at the time of reset in the first embodiment of the present invention.

FIG. 11 is a checker CP according to the second embodiment of the present invention.
The timing chart showing the write data transfer timing during U surrogate operation.

FIG. 12 is a block diagram showing the configuration of a third embodiment of the master checker type computer system according to the present invention.

FIG. 13 is an explanatory diagram showing a board mounting state of a third embodiment of the master checker type computer system according to the present invention.

FIG. 14 is a block diagram showing the configuration of a third embodiment of a master checker type computer system according to the present invention.

FIG. 15 is a timing chart showing the comparison timing of write data in the second embodiment of the present invention.

FIG. 16 is a block diagram showing the configuration of a fourth embodiment of a master checker type computer system according to the present invention.

FIG. 17 is an explanatory diagram showing a board mounting state of the fifth embodiment of the master checker type computer system according to the present invention.

FIG. 18 is a block diagram showing the configuration of a fifth embodiment of the comparison device according to the present invention.

FIG. 19 is a block diagram showing the configuration of a sixth embodiment of a master checker type computer system according to the present invention.

[Explanation of symbols]

 CPU Central processing unit CMP comparator SCU system control unit MBBR master bus buffer register MBCR master bus compare register CBCR checker bus compare register SEL selector (selection device)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Oguro 810 Shimoimaizumi, Ebina City, Kanagawa Pref., Hitachi Systems Office Systems Division (72) Inventor Sataka Ishikawa 810 Shimoimaizumi, Ebina City, Kanagawa Stock Company Hitachi Factory Office Systems Division

Claims (17)

[Claims] 1. A master central processing unit, a check central processing unit that performs the same processing as the master central processing unit in parallel to check the operation of the master central processing unit, and a main access unit to which the master central processing unit accesses. A storage device, an input / output device accessed by the master central processing unit, and a control device interposed between at least the main storage device and the input / output device, and the master central processing unit to control the access, A comparison device that compares the processing results output by the master and check central processing units, and outputs a difference in processing results to the control unit when the processing results differ, the master central processing unit and the control unit And a master side processor bus that connects the above-mentioned comparison device and the checker-side processor bus that connects the above-mentioned checker central processing unit and the above-mentioned comparison device. A computer system having a processor bus, wherein the checker central processing unit is connected to the control unit, the main storage unit, and the input / output unit via the comparison unit. 2. The computer system according to claim 1, further comprising a delay circuit that delays an operation timing at which the checker central processing unit performs processing from the operation timing at which the master central processing unit performs processing by a predetermined time. The computer system is characterized in that the comparison device compares the processing results output by the master and the checker central processing unit when the processing results output by the checker central processing unit are obtained. 3. The computer system according to claim 2, wherein the fixed time is one machine cycle time or more of the master central processing unit. 4. The computer system according to claim 1, 2 or 3, wherein when the comparison device detects that the comparison result is different in the write processing to the main storage device or the input / output device, A computer system characterized in that the comparison result is transmitted from the comparison device to the control device before the control device writes to the main memory device or the input / output device. 5. The computer system according to claim 1, 2, 3 or 4, wherein a failure occurs in the master central processing unit, and the checker central processing unit operates as a substitute for the master central processing unit. A computer system having a connection circuit for connecting the checker side processor bus and the master side processor bus. 6. The computer system according to claim 5, wherein when a failure occurs in the master central processing unit and the checker central processing unit operates as a substitute for the master central processing unit, the checker central processing unit A computer system having a delay circuit for delaying an operation timing by a predetermined time from an operation timing when the master central processing unit was operating. 7. The computer system according to claim 1, 2, 3, 4, 5 or 6, wherein the comparison device is built in the control device. 8. The computer system according to claim 2, wherein the timing of a control signal from the control device to the checker central processing unit, which is not synchronized with the operation timing of the master side processor bus, is set to the checker side processor bus. A computer system having a synchronization circuit for synchronizing with an operation timing. 9. The computer system according to claim 2, wherein the comparison device latches data inputted through the master side processor bus, and the inputted data and the checker side processor bus are inputted. And a selector for comparing the data with the data, and a selector for sending the data from the master central processing unit among the latched data to the comparison circuit and sending the data from the control unit to the processor bus on the checker side. A computer system characterized by. 10. Claims 1, 2, 3, 4, 5, 6, 7, 8
Alternatively, in the computer system described in the paragraph 9, there is a plurality of the master central processing units. 11. The computer system according to claim 10, wherein there are a plurality of the checker central processing units, and the number thereof is the same as the number of the master central processing units. 12. A method according to claim 1, 2, 3, 4, 5, 6, 7,
In the computer system according to 8, 9, or 10, there are a plurality of the checker central processing units, the checker central processing units are divided into a plurality of groups, and the plurality of checker side processor buses correspond to the groups. Characteristic computer system. 13. The computer system according to claim 10, 11 or 12, further comprising information for identifying an operating checker central processing unit when some of the checker central processing units are not operating. A computer system comprising: holding means for holding; and a selector for sending data output by a master central processing unit corresponding to a checker central processing unit that is not operating to the checker side processor bus based on the above information. 14. The computer system according to claim 10, 11, 12 or 13, wherein the correspondence relationship between the master central processing unit and the checker central processing unit is variable. 15. The computer system according to claim 14, wherein the checker central processing unit corresponding to the failed master central processing unit corresponds to the master central processing unit which has not failed. 16. The computer system according to claim 10, 11 or 12, wherein identification information for identifying each of said master and checker central processing unit is attached, and said central processing unit and said identification information. A computer system having means for switching the correspondence relationship between 17. The computer system according to claim 16, wherein the checker central processing unit corresponding to the failed master central processing unit is identified from the central processing unit so that the checker central processing unit corresponds to the non-failed master central processing unit. A computer system having means for switching the correspondence with information.