JPH0744224B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a semiconductor memory device excellent in designability and expandability.

[Background of the Invention]

Conventionally, for the built-in I ² L RAM in analog / digital coexistence LSI, the IEICE Transactions J66-C
No. 9, pp. 668 to 675, discussed in Kaneko et al., "High-breakdown-voltage analog circuit coexistence 256-bit I ² L RAM", and JP-A-58-159294.

Further, I ² L RAM is discussed in JP-A-55-21179, JP-A-55-67995 and JP-A-56-19658.

FIG. 1A is a circuit diagram of a memory cell using a conventional I ² L element.

The memory cell shown in FIG. 1 (a) uses an I ² L 2 element having two collectors, each I ² L base and one of the two collectors are cross-connected to each other, and the remaining one collector is used. Are connected to the bit lines B, respectively. Also,
The I ² L injector is used as the word line W ⁺ , and the I ² L emitter is used as the word line W ⁻ .

Q ₁₁ and Q ₁₂ are pnp transistors, and Q ₁₃ and Q ₁₄ are 2-collector npn transistors operating in the reverse direction.

FIG. 1 (b) is an equivalent circuit for explaining the operation of FIG. 1 (a). The two-collector reverse npn transistors Q ₁₃ and Q ₁₄ in FIG. 1 (a) are equivalent to each other in FIG. 1 (b).
Q ₂₃ and Q ₂₄ are shown separately as reverse npn transistors Q ₂₅ and Q ₂₆ , which serve as coupling elements between the outside when reading and writing, and Q ₂₃ and Q ₂₅ are shown as Q ₁₃ and Q _{25. 24} and Q ₂₆ are Q ₁₄
Equivalent to.

A constant current source I _inj is connected to the word line W ⁺ , and the pnp transistors Q ₂₁ and Q _{22 function} as loads on the reverse npn transistors Q ₂₃ and Q ₂₄ and Q ₂₅ and Q ₂₆ , respectively. Also, reverse npn transistor
The collectors of Q ₂₅ and Q ₂₆ are connected to the bit line B, respectively, and B, is connected to the power supply V _BB through the load resistance R _B.

The read operation and its conditions will be described below with reference to the equivalent circuit diagram of FIG.

Now, if the reverse npn transistors Q ₂₃ and Q ₂₅ are conductive,
Q ₂₄ and Q ₂₆ are non-conductive. Q ₂₅ is a pnp transistor Q ₂₂
A collector current corresponding to the base current supplied through the current flows. The collector current in this case is supplied from the power source V _BB through the load resistance R _B , and the potential V _B of the bit line B becomes lower than V _BB by the amount of the voltage drop of the load resistance R _B.

On the other hand, the potential of the bit line is V _BB because Q ₂₆ is non-conductive.
It is possible to read out the information in the memory by detecting the potential difference with the bit line B.

The read operation of only one bit has been described above, but in an actual RAM, there are a plurality of memory cells sharing the bit line B.

Therefore, since the selected and unselected memory cells cannot be electrically separated, the unselected memory cells also absorb the collector current from the bit line.

Therefore, as a method of selecting and deselecting a memory cell, a _means of increasing the injector current I _inj of the selected cell to make a difference from the current _drawn by the non-selected cell is taken. In this case, the worst condition in which the potential difference between the bit lines is the smallest is when all the non-selected memory cells hold the opposite information to the selected memory cell. When the injector current of the selected memory cell is I _S and the injector current of the non-selected memory cell is I _US ,
The sink current I _{B of} the selected cell and the total sink current I _UST of the non-selected cell are Becomes

Here, α _P and β _n are pnp transistors Q ₂₁ and Q ₂₂ respectively.
Is the base grounding current amplification factor of and the current amplification factors of the reverse npn transistors Q ₂₅ and Q ₂₆ . N is the number of memory cells connected to the bit line B. Since the condition that the information of the selected memory cell can be read is I _B > I _UST (3), the relationship between the injector currents, I _US and I _S is I _S > I _US (N-1) (1.4) ) Must be.

For example, if a 1K-bit RAM is made up of 1 word and 8 bits, the number of memory cells sharing a bit line is 128, and I _S must be 127 times or more of I _US . As a result, the number of memory cells sharing a bit line varies depending on the scale and configuration of the RAM, and the peripheral circuit must be designed each time. Further, for stable operation, I _S / I _US is preferably 10 ² or less. Therefore, the conventional I ² L RAM circuit is not suitable for 1K bit or more RAM.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device having excellent designability and expandability.

[Outline of Invention]

In the present invention, in order to achieve the above object, the first and second polarities of the first polarity, in which the base and the collector are cross-connected to each other and the respective emitters are both connected to the first word line, are provided.
And the first and second transistors as a load, one end of each of which is connected to the collectors of the first and second transistors, and the other one end of which is the third.
First and second load elements connected to the first word line, the bases connected to the collectors of the first and second transistors, respectively, the emitters connected to the second word line, and the collectors respectively connected to the second word line. A semiconductor memory device having a memory cell including first and second coupling transistors of the first polarity connected to the first and second bit lines is provided.

Example of Invention

The first embodiment of the present invention will be described below with reference to FIG. FIG. 2 is an equivalent circuit of one bit of the I ² L memory cell according to the present invention.

In FIG. 2, cross-connected npn transistors Q ₃ and Q ₄ and pnp transistors Q ₁ and Q ₂ acting as loads are
The first embodiment is constructed by interconnecting I ² L 2 gates. Q ₁ and Q ₄ and Q ₂ and Q _{3, respectively}
Corresponds to the I ² L 1 gate. Further, Q ₅ and Q ₆ are normal npn transistors, that is, forward-direction npn transistors. Also, Q ₃ and Q ₄ are reverse acting transistors in the I ² L gate. Therefore, Q ₅ and Q ₆ operate in the opposite direction to Q ₃ and Q ₄ . The word line W ⁺ is an I ² L injector line.

During operation, a constant current source is connected to the word line W ⁺ .

Next, the operation of the memory cell according to the present invention will be described.

FIG. 3 shows the word line W of the memory cell of FIG._C, W_SAnd
It represents the potential change of the test line B, and
In the timing chart that clarified the behavior of the molysel
is there. At point a in FIG. 3, word line W_CPotential V_WCIs almost 0
Low level about V, W_SLevel V_WSIs a high level of about 0.7V
And the potential V of bit line B,_B, V Are both high level
Switching transistor Q_Five, Q₆Turned off
is there. Therefore, the information inside the memory cell is retained and the
It is in a state. At point b, word line W_C, W_SPotential of
V_WC, V_WSAre both high level and the potential V of the bit line B_BIs low
Level, potential V Is at a high level. For this reason,
Ittsu transistor Q_FiveBias between base and collector of
Becomes Q and operates in the opposite direction, Q_FiveThe base potential of word line W_Cof
Potential V_WCIs almost the same as. Yotsute Q_FourBass Emitsu
Forward bias is no longer applied between the
In fact, writing is performed. At point c, word line W_C, W_S
Potential V_WC, V_WSAre both low level. This state
Then, by the writing done at point b
Dista Q₆Since the base potential of is at a high level, Q₆
Is a forward operating potential V To a low level. This and
Potential difference of the bit line B, (V_B-V ) Is detected
Makes it possible to read.

At the point d, the state of the word line is the same as that at the point b and it is in the written state, but the bit line is at the low level on the opposite side of the point b. This causes Q ₆ to operate in the forward direction and Q _{3 to} be non-conductive. If the writing performed at the point b is "1", "0" is written at the point d. Further, at the point e, as with the point c, the word line is read while the word line is in the read state. However, the information being read is the opposite of that at the point c, and the low level of B is the high level. ing. If the information read at point c is "1", the information read at point e corresponds to "0".

In this embodiment, each of Q ₁ , Q ₄ and Q ₂ , Q ₃ is formed by an I ² L gate, so that two transistors can be formed in a small area which is almost one element. Therefore, it has an effect of reducing the cell area. Further, since the coupled npn transistors Q ₅ and Q ₆ are forward transistors, the gain is large. Therefore, there is an effect that reading can be stably performed. Further, in the cell circuit configuration of the present invention, W _C and W _S are separated from each other and a potential is independently applied unlike the conventional case.
Therefore, there is an effect that the selection and non-selection of the cells can be surely performed electrically.

FIG. 4 (a) shows an embodiment of a plane pattern when the memory cell according to the present invention is formed on an integrated circuit. Fourth
FIG. 4B is a sectional structural view taken along the line XX ′ in FIG.

In FIG. 4 (a), one bit of the memory cell is shown within a broken line, and the transistor pair Q ₃ , Q ₄ and Q ₁ , in FIG.
Q ₂ is formed in the I ² L region, and Q ₅ and Q ₆ are formed in the npn region.
Further, the I ² L region and the individual npn transistors in the npn region are electrically isolated by the element isolation region 41 and then interconnected. The word line W _C can be wired by providing the extraction electrode 45 at the end of the n ⁺ buried layer 424 in the I ² L region and does not require wiring on the element region.

The npn transistor shares the n-type region 429 serving as a collector, the n ⁺ diffusion layer 433, and the n ⁺ buried layer 430 with the npn transistor of the memory cell in the lower stage, and is in one isolation region. In the present embodiment, the bit lines B ',', B, use the two-layer wiring, but it is also possible to wire them using the one-layer wiring.

FIG. 5 is a circuit diagram showing the second embodiment.

FIG. 5 shows one bit of the memory cell, in which the pnp transistors Q ₁ and Q ₂ which become the load of the memory cell of FIG. ₂ are replaced with load resistors R ₅₁ and R ₅₂ . Also, as in FIG. 2, the transistors Q ₅₁ and Q ₅₂ are npn transistors that operate in the reverse direction, and Q ₅₃ and Q ₅₄ are npn transistors that operate in the forward direction.

FIG. 6 is a circuit diagram showing a third embodiment.

FIG. 6 shows one bit of the memory cell, in which the pnp transistors Q ₁ and Q ₂ which are the loads of the memory cell of FIG. ₂ are replaced with diodes D ₆₁ and D ₆₂ . Also, as in FIG. 2, the transistors Q ₆₁ and Q ₆₂ are npn transistors which operate in the reverse direction and Q ₆₃ and Q ₆₄ operate in the forward direction.

Next, a fourth embodiment of the present invention will be described. The circuit has the same configuration as in FIG. In the fourth embodiment, Q ₁ , Q
₂ is a normal pnp transistor, and Q ₃ , Q ₄ , Q ₅ , and Q ₆ are all normal forward npn transistors. In this embodiment, since Q ₃ , Q ₄ , Q ₅ , and Q ₆ are all high gain, there is a margin even if the gain is reduced due to manufacturing variations or the like. Therefore, the manufacturing margin is wide. However, the cell area is larger than in the first embodiment.

A fifth embodiment will be described. The circuit has the same configuration as in FIG. In the fifth embodiment, Q ₁ , Q ₄ and Q ₂ , Q ₃ are formed by I ² L gates respectively, and Q ₅ , Q ₆ are formed by reverse npn transistors. In the present embodiment, Q ₃ , Q ₄ and Q ₅ , Q ₆ are reverse npn transistors having a common emitter, so that the word line wiring is not necessary and the cell area can be reduced.

Further, in this embodiment, it is also effective when only Q ₃ and Q ₄ are formed by forward npn transistors.

FIG. 7A shows an example of a plane pattern when the memory cell according to the fifth embodiment is formed on an integrated circuit. FIG. 7 (b) is a sectional structural view taken along the line XX 'in FIG. 7 (a).

In FIG. 7 (a), the inside of the broken line is one bit of the memory cell, and the transistor pair Q ₃ , Q ₄ and Q ₁ , in FIG.
Q ₂ is formed in the I ² L region, and Q ₅ and Q ₆ are formed in the npn region.
Further, the I ² L region and the npn region are electrically isolated by the element isolation region 41. The word line W _C can be wired by providing the extraction electrode 45 at the end of the n ⁺ buried layer 424 in the I ² L region and does not require wiring on the element region.

Similarly, the word line W _S can also be wired by providing the extraction electrode 412 on the n ⁺ buried layer 430 in the npn region, and does not require wiring on the element region. In this embodiment, the bit lines B ',
Although ', B, use two-layer wiring, it is also possible to wire these by using one-layer wiring.

FIG. 8 shows a 1K constructed using the memory cell according to the present invention.
It is an example of a block diagram of a bit RAM. Even if any of the memory cells of the first to fourth embodiments according to the present invention is used, the memory can be realized with the configuration of FIG.

In the block diagram of FIG. 8, cell blocks CB (1,1) to CB (1
6,8) have a common word line in one block 8
It contains a bit memory cell. In this circuit, eight cell blocks are laterally connected to each other, and a total of 64 memory cells share a word line. Also, 16 memory cells are connected to the pair of bit lines, and 16 memory cells are connected in the vertical direction.
It is constructed by stacking individual cell blocks.

Sixteen word drivers WD1 to WD16 are connected to the word line ends, and eight sense amplifiers and bit driver blocks SABD1 to SABD8 are connected to the bit line ends.

Reading and writing in this circuit are performed for each cell block. Therefore, eight input / output data lines 721 and 722 are provided, but by changing the circuits of the sense amplifier and bit driver and using the signals of the read / write lines, the input / output lines are shared and the data lines are provided. It is also possible to make a total of eight. The cell block selecting method is performed by the X address decoder 717 and the Y address decoder 723.
In addition, read or write is selected as read or write.
719.

〔The invention's effect〕

According to the present invention, the memory cells in the operating state and the memory cells in the holding state can be easily electrically separated, and the degree of freedom in the configuration of the standardized RAM of the peripheral circuit can be increased. Therefore, it is effective in improving designability and expandability.

[Brief description of drawings]

 Figure 1 shows the conventional I²Circuit diagram of L RAM cell and its equivalent circuit
FIG. 2 is a circuit diagram of an embodiment of the memory cell according to the present invention.
FIG. 3 is a control pulse diagram of a memory cell according to the present invention.
FIG. 4 is a diagram showing a gate of the memory cell of the first embodiment.
FIG. 5, FIG. 6 and FIG. 6 showing a plane pattern and a sectional structure
Are circuits of the second and third embodiments of the memory cell according to the present invention.
FIG. 7 and FIG. 7 are plane patterns of the memory cell of the fifth embodiment.
And FIG. 8 is a view showing a sectional structure, and FIG.
Block diagram showing the configuration of a 1K bit RAM using a controller
It Q₁₁, Q₁₂, Q_{twenty one}, Q_{twenty two}...... pnp transistor, Q₁₃, Q₁₄…… 2
Collector npn transistor, Q_{twenty three}, Q_{twenty four}, Q_{twenty five}, Q₂₆...... npn
Langista, Q₂₇, Q₂₈...... Diode, W⁺, W^-……word
Line, B, ... Bit line, R_B...... Load resistance, V_BB...... Bits
Power source, I_inj...... Current source, W_C, W_S...... Word line, Q₁, Q₂
...... pnp transistor, Q₃, Q_Four, Q_Five, Q₆...... npn Transis
T, V_WC...... Word line W_CPotential of V_WS...... Word line W_SElectric power
Rank, V_B...... The potential of bit line B, B ...... Bit line power
, 41,422,428,433 …… Element isolation region, 42,43,45,423,4
26,431 …… p-type impurity diffusion region, 44,47,411,413,424,42
7,430,432,433 ... n-type impurity diffusion region, 45,46,48,410,
412,416, ... Contact hole, 437 ... p-type substrate, 425,429
…… N-type epitaxial layer, 417,418,419,420,421 ……
Electrodes and wiring, 436,435 ... Insulating film, R₅₁, R₅₂...... Load resistance
Anti, Q₅₁, Q₅₂, Q₅₃, Q₅₄...... Npn transistor, W⁺, W_C, W_S…
… Word line, B, …… bit line, D₆₁, D₆₂...... Dio
Do, Q₆₁, Q₆₂, Q₆₃, Q₆₄...... Npn transistor, W⁺, W_C, W_S…
… Word line, B, …… bit line, CB (1,1) to CB (16,
8) …… Memory cell block, WD1 to WD16 …… Word drive
IBA, SABD1 to SABD8 ... Sense amplifier, bit driver
Block, 717 ... X address decoder, 723 ... Y add
Response decoder, 718 ... X address decoder input, 720 ...
... Y address decoder input, 719 ... Read / write signal
Line, 721 ... Data input line, 722 ... Data output
line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Hayashi 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ultra ESL Engineering Co., Ltd. In-house (72) Inventor Tomoyuki Watanabe 1-chome, Higashi Koikeku, Kokubunji, Tokyo 280 In the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Keizo Matsumoto 1479 Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Ultra ELS Engineering Co., Ltd. (72) Inventor Makoto Furihata Nishi, Takasaki, Gunma Prefecture 111 Yokotemachi, Takasaki Plant, Hitachi, Ltd. (72) Inventor Setsuo Ogura 111, Nishiyotecho, Takasaki City, Gunma Hitachi, Ltd., Takasaki Plant

Claims (4)

[Claims] 1. A first and a second transistor of a first polarity whose base and collector are cross-connected to each other and whose respective emitters are both connected to a first word line, and said first and second transistors. , Each of which is connected to the collectors of the first and second transistors, and the other one of which is connected to the third transistor.
First and second load elements connected to the first word line, the bases connected to the collectors of the first and second transistors, respectively, the emitters connected to the second word line, and the collectors respectively connected to the second word line. A semiconductor memory device comprising a memory cell including first and second coupling transistors of a first polarity connected to first and second bit lines. 2. The first and second load elements are third and fourth transistors of the second polarity, respectively, the bases of which are both connected to the first word line, and the collectors of the first and second load elements are respectively connected to the first word line. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the collectors of the first and second transistors, respectively, and the emitters thereof are both connected to the third word line. 3. The semiconductor memory device according to claim 1, wherein each of the first and second load elements is a resistor. 4. The first and second load elements are diodes, respectively.
The semiconductor memory device according to the item.