JPH0740596B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

[Conventional technology]

As a semiconductor device in which a semiconductor element is built in a package, a resin-molded semiconductor device, an IC card in which an IC chip is embedded in a plastic card, and the like are well known.

Most of the conventional LSI packages are plastic package packages for the purpose of cost reduction. Since the semiconductor device and the sealing plastic have different linear expansion coefficients by about one digit, thermal stress is generated in the package when the temperature of the package changes. However, until now, the size of the semiconductor device was smaller than the size of the entire package, so that the stress generated was small, and the semiconductor device and the package itself were not adversely affected. For this reason, until now, problems due to stress have hardly been considered in terms of improving the reliability of the package, and mainly soft error countermeasures have been the main focus. The problem of thermal stress is described in detail in Nikkei Electronics Separate Volume Micro Devices No.2, p82-p92.

In addition, an IC card with an IC (microprocessor and memory) embedded in a plastic card may cause unexpected stress on the card because the card is often carried by the user, and it may be exposed to extremely high temperatures or in opposite locations. Thermal stress may occur because the card is placed in a very cold place. Of course, stress may be applied to the card even while the card is in use.

[Problems to be solved by the invention]

In a semiconductor device in which a semiconductor element as described above is built in a package, various stresses applied to the semiconductor device cause the semiconductor element or the package to crack, or even if the crack does not occur, the semiconductor element functions normally. There is a problem that it will not do.

In recent LSIs, the size of semiconductor elements tends to increase rapidly, and the stress caused by the difference in expansion coefficient between the resin for molding and the semiconductor elements is also increasing. Further, semiconductor devices are rapidly being highly integrated and multifunctional, and the demand for reliability is extremely high. Therefore, it is important to deal with defects caused by the generation of stress. Needless to say, it is necessary to deal with various problems caused by stress even in an IC card or the like incorporating an LSI.

Examples of failure due to stress are breakage failure such as disconnection of Al wiring and bonding wire on semiconductor element, and moisture penetration due to cracking of passivation film on element surface causing corrosion disconnection of Al wiring, or failure Various defects such as variations in electrical characteristics due to variations in diffusion resistance value due to the piezoresistive effect of the silicon element are possible. In this way, the stress cannot be ignored when considering the reliability of the semiconductor element.

Therefore, an object of the present invention is to provide a semiconductor device and a failure prevention method for a semiconductor device, in which the state before a failure of a semiconductor element is grasped early and the reliability is improved by preventing the failure. It is to be.

[Means for solving problems]

The above-mentioned object is to incorporate a stress detecting means (hereinafter, referred to as a “stress detecting section”) for detecting a stress acting on the semiconductor element into a semiconductor device, and when the detected value of the stress detecting section exceeds a predetermined value, the semiconductor element This is achieved by providing preventive measures for implementing measures to prevent the failure of the.

[Action]

By incorporating the stress detector in the semiconductor device, the stress applied to the semiconductor element can be accurately recognized. If this stress exceeds a predetermined value, a negative effect due to the stress is expected, and therefore preventive measures are taken to reduce the stressed state. As a result, it is possible to prevent the failure of the semiconductor device.

〔Example〕

Hereinafter, the present invention will be described in detail based on specific examples.

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, the semiconductor element 6 is built in a package 8 such as a plastic. The semiconductor element 6 is, for example, an LSI such as a memory or a processor. In this example, the stress detector 10 for detecting the stress applied to the semiconductor element 6 is incorporated in the semiconductor element 6 as a part of an electronic circuit formed in the semiconductor element 6. Also, a processor 5 which inputs the detection output of the stress detection unit 10 and outputs a signal for preventing a failure when the detection value exceeds a predetermined value stored in advance is also formed in the semiconductor element 6. It is incorporated in the semiconductor element 6 as a part of the circuit. When the semiconductor element 6 itself is a processor, it is not necessary to separately provide the processor 5. Further, the processor 5 does not have to be incorporated in the semiconductor element 6, and may be separately provided in the package 8. The semiconductor element 6 itself does not have to be one, and may be composed of two or more elements as shown in FIG. The power supply 7 supplies electric power necessary for various operations of the semiconductor device included in the package 8, and is provided in the package 8 in this example. The alarm sound generator 20 is for generating an alarm sound by the alarm signal output of the processor 5. The display section 30 is composed of a display element such as liquid crystal and a drive section thereof, and is for visually displaying an alarm of the processor 5 or for visually displaying an abnormal state of the semiconductor element.

Now, the stress detector 10 shown in FIG. 1 will be described.
Conventionally, there is no known one that can accurately detect various stresses applied to the semiconductor element 6 in the package. Therefore, the present inventor has developed a semiconductor element built-in type stress sensor utilizing the piezoresistive effect. This principle is as follows. The piezoresistive effect is a phenomenon that when the crystal is strained, its specific resistance changes. The piezoresistive effect in semiconductors such as silicon and germanium is obtained by using the resistivity ρ represented by the second-order tensor, the strain force tensor X, and the fourth-order tensor π. Is expressed as Here, λ = 1 to 6 respectively correspond to direction components xx, yy, zz, yz, zx, xy when assuming a three-dimensional XYZ rectangular coordinate system. πμλ is a piezoresistance coefficient, and in a crystal having cubic symmetry such as silicon or germanium, the number of independent components is three. From the equation (1), it can be seen that six independent strain force components contribute to the change δρμ of the specific resistance component. In general, there are three resistivity components that can be measured independently in one plane (δ _ρxx , δ assuming the XY plane).
_{ρ yy} , δ _{ρ xy} ) only. Therefore, it is impossible to separately detect the three-dimensional strain force component acting on one plane from the change in the in-plane resistivity component.

However, the piezoresistance coefficient is characterized in that its value changes independently depending on the type of impurities diffused in the semiconductor crystal. Therefore, when two types of impurities are diffused in one semiconductor crystal plane to form respective diffusion resistance layers, three independent changes in resistivity can be measured in each diffusion resistance layer, and both diffusion layers can be measured. The specific resistance changes in are independent of each other. Therefore, a total of 6 independent resistivity changes can be measured in one crystal plane. Since there are six independent strain force components acting on the plane, it becomes possible to separately detect the strain force components by solving the equation (1). The piezo resistance coefficient corresponding to the sensor sensitivity is calibrated in advance.

The stress detecting section 10 shown in FIG. 1 is formed in the substrate of the silicon single crystal (100) crystal plane by utilizing this principle. In this example, two P-type diffusion resistance layers 1 and two n-type diffusion resistance layers 2 are arranged. The resistors in each layer are orthogonal to each other, and the P-type diffusion resistance layer 1 and the n-type diffusion resistance layer 2 are
It makes an angle of 45 °. An electrode terminal 33 is taken out from each resistance layer and connected to a processor 5 by an electric wiring 4.
The operation of each diffusion resistance is as follows when the n-type diffusion resistance layer is aligned with the <100> crystal axis direction and the P-type diffusion resistance layer is aligned with the <110> crystal axis direction. When the crystal plane is made coincident with the XY plane, the normal stress components are σ _x , σ _y and σ _z , and the shear stress component is τ _xy , the specific resistance change corresponding to each stress is as follows.

Here, A to F are piezoresistive coefficients, δ _ρn is a specific resistance change of the n-type diffusion resistance layer, and δ _ρp is a specific resistance change of the P-type diffusion resistance layer. Note that changes in the resistivity of silicon in the (100) crystal plane include τ _yz and τ _zx of other three-dimensional shear stress components.
Does not contribute. 4 in total for P-type diffusion resistance layer and n-type diffusion resistance layer
Since it is possible to detect individual independent changes in resistivity, solving equation (2) allows three-dimensional stress components σ _x , σ _y , σ
_z and τ _y can be detected separately. This operation is performed by processor 5
It is executed by. Each piezoresistive coefficient is calibrated in advance by generating a known stress.

When a diffusion resistance layer is formed in another crystal plane of silicon, for example, the (111) crystal plane, the three-dimensional total stress components (σ _x , σ _y , σ _z , τ _xy are included in the resistivity change. , Τ _yz ,
Since τ _zx ) contributes, at least three n-type and P-type diffusion resistance layers are required. Since the number of diffusion resistance layers varies depending on the crystal plane used, the stress component contributing to the change in specific resistance, the number of diffusion resistance layers may be set to a necessary minimum or more. Further, since the piezo resistance coefficient has temperature dependence, it is preferable to incorporate a temperature compensation circuit in the peripheral circuit. The shape of the diffusion resistance layer does not have to be rectangular.

Next, the processor 5 shown in FIG. 1 will be described.
As shown in FIG. 3, the processor 5 includes a measuring circuit 51,
It is composed of an arithmetic circuit 52, a memory circuit 53, and an input / output circuit 54. The measuring circuit 51 constitutes a bridge circuit and measures a change in resistance value of the stress detecting unit 10 as a change in bridge balance, converts this to a digital value and outputs the digital value to the arithmetic circuit 52. The arithmetic circuit 52 inputs the signal obtained by the measuring circuit to calculate the stress applied to the semiconductor element, and when the stress exceeds a predetermined value stored in the memory circuit 53, a signal for failure prevention. The data is output via the input / output circuit 54, and the semiconductor device is further diagnosed. If an abnormality is determined as a result of this diagnosis, the abnormal state is stored in the storage circuit 53. Also,
This abnormal state is output via the input / output control circuit 54. The memory circuit 54 stores programs and data necessary for the arithmetic processing of the arithmetic circuit 52. The calculation result is also stored.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to the flow chart shown in FIG. The stress generated in the semiconductor device, particularly the stress applied to the semiconductor element 6, appears as a change in the specific resistance in the stress detection unit 10. A signal corresponding to the change in the specific resistance is input to the arithmetic circuit 52 via the measuring circuit 51. The arithmetic circuit 52 calculates the generated stress using the input signal. This process is step F10 in FIG. Next, the maximum value σ _m of the generated stress is obtained (step F20). Then step F
At 30, the magnitude relationship between the maximum value σ _{n of} stress and the predetermined value (here, the allowable stress σ _c ) stored in the storage circuit 53 is determined. The allowable stress σ in this example
_c is determined as follows. The strength of a semiconductor element such as silicon changes significantly depending on the presence or absence of crystal defects inside the element. For this reason, the strength of the element is defined as the strength with a destruction probability of what%. Therefore, in this example, the strength at which the fracture probability is 1% is set as the allowable stress σ _c . Of course, this value may be changed to an appropriate value in consideration of the safety factor and the like. If σ _m ≧ σ _c in step F30, the process proceeds to step F40. Conversely, when σ _m <σ _c , step F60
Proceed to. At Step F40, the fact that the generated stress σ _m exceeds σ _c is transmitted to the outside. This outputs a warning signal to the alarm sound generation unit 20 via the input / output circuit 54, and
It can be realized by 20 making a warning sound. It can also be realized by displaying on the display unit 30 that the stress has exceeded the allowable value. Here, an alarm sound is emitted and the fact that a failure has occurred is displayed. When the above process is completed in step F40, the process proceeds to step F50 to record (store) the warning output existence in the memory circuit 53. The warning will continue until the stress is below the permissible value. For example, when the user of the IC card notices the warning sound and relaxes the stress, σ _m becomes σ _c
It gets smaller. Then proceed to step 60. Step
At 60, the data indicating the presence / absence of the warning output of the memory circuit is checked to determine whether or not the warning output is present. If there is no warning output, the process returns to step F10. If there is an alarm output, the process proceeds to step F70, where the semiconductor element is diagnosed and the presence or absence of abnormality is checked. If there is no abnormality, the process proceeds to step F80 to erase the data indicating the warning output of the memory circuit. If there is an abnormality, the process proceeds to step F90 to store the occurrence of the abnormality and its content in the memory circuit 53. Further, these pieces of information are output and displayed on the display unit 30. Further, when there is an output terminal to the outside of the device and this terminal and the external device are electrically connected, this abnormal state is transmitted to the external device.

According to this embodiment, the occurrence of stress can be detected extremely accurately and reliably, and based on the detection result, the semiconductor device warns the outside when the stress exceeds the allowable value. Therefore, it is possible to prevent the breakdown. Since the warning is given by a warning sound and the warning content is displayed, it is possible to effectively prevent a failure due to stress even in a semiconductor device that can be easily carried around like an IC card. Furthermore, when a warning is output, it is diagnosed whether the semiconductor element is functioning normally, and if there is an abnormality, the state is stored and displayed, so use of a semiconductor device in an abnormal state is recommended. Easy to prevent.

The stress sensing portion in the element does not necessarily have to be provided in the central portion of the semiconductor element surface as shown in FIG. As shown in FIG. 8, a plurality of elements may be arranged along the ends or diagonals on the element, or a plurality of elements may be arranged along the center line on the element as shown in FIG. In addition, the arrangement of the stress sensing section in the element plane is not particularly limited as necessary.

Next, another embodiment of the present invention will be described with reference to FIGS. 5A, 5B and 6. FIGS. 5A and 5B are a cross-sectional view and an internal schematic configuration diagram of a plastic-sealed semiconductor device in which the stress detection unit 10 is built in the semiconductor element 6 and the processor 5 is provided in the same package 9. In the plastic-sealed semiconductor device, the coefficient of linear expansion of the semiconductor element 6 (in the case of silicon is 3 ×).
10 ^-6 / ° C) and the linear expansion coefficient of lead frame 11 (for copper)
17 × 10 ^-6 / ° C) and linear expansion coefficient of sealing resin (up to 20 × 10 ^-6 /
C.) are different from each other, thermal stress is generated in the package 9 when a temperature change occurs in the package 9. Stress detection is performed for the purpose of preventing or compensating for variations in electrical characteristics due to element cracking and piezoresistive effects due to this stress. Prevention of element cracking due to thermal stress can be realized by the processor 5 outputting to the external device (not shown) that the stress has become an abnormal value by a predetermined value, so that the external device cools. Since it is difficult to build a power source inside the package, the power source 40 is provided outside the package for the usage state mounted on the printed circuit board 50 or the like. When the semiconductor element 6 is small, it is sufficient to provide the stress sensing portion 10 at one place near the central portion of the element surface as shown in FIG. 7, but when the semiconductor element 6 is large. If necessary, a plurality of them may be arranged as described in the first embodiment.

When the semiconductor element 6 is an element such as an A / D converter, a change in the resistance value of the diffusion resistance layer due to the piezoresistive effect leads to defective electrical characteristics or malfunction, so compensation of characteristics according to generated stress is required. Performed by processor 5.

In this case, a minute change in the resistance value leads to a resolution of the electric characteristics of the device and a change in the output, so that it is necessary to detect the stress in detail. Therefore, in order to detect the stress distribution in the element surface, a plurality of stress detecting portions are provided along the diagonal line or the center line from the central portion. Processor 5
Determines the stress distribution by calculation, adjusts the bias voltage, for example, so as to cancel the resistance value fluctuation of each diffusion resistance due to the generated stress, and calculates and outputs the output change accompanying the resistance value change. Feed back to the side to correct the output signal.
In the case of performing the most precise compensation, the stress detecting section is provided in the vicinity of each diffusion resistance that needs adjustment. As the characteristic compensation in this case, the output correction method as described above and a resistance layer having a characteristic opposite to the piezoresistive effect of each diffusion resistance are electrically provided in series, and both are treated as one resistance as a whole. By doing so, a method of automatically suppressing variation in resistance value can be considered. The flow of operation of the processor 5 in this embodiment is shown in FIG. The flow in FIG. 6 is almost the same as the float described with reference to FIG. 5 in the embodiment of FIG. 1, except that step F100 is included in the operation after step F60. That is, when the generated stress σ _m is smaller than the allowable value σ _c, it is determined in step F60 whether or not the memory circuit contains data with warning output. If no data has been input, it is determined that the semiconductor element is in an electrically normal state and the process proceeds to step F100, where the output correction as described above is performed, and then the process returns to step F10. If data with warning output is entered, check the electrical characteristics of the device with step F70, and if there is no abnormality, then step F8
After the warning output data of the memory circuit is erased at 0, the output is corrected at step F100 and the process returns to step F10. If the electrical characteristics are abnormal, the abnormality occurrence data is recorded in the memory circuit at step F90, and the operation ends. In addition, step F90
In this method, an abnormality occurrence signal is output to the outside of the package and the use of the semiconductor device is stopped at the same time.

Further, in this embodiment, as described in the first embodiment, since the piezoresistive coefficient has temperature dependence, a temperature detecting unit is provided in the stress sensing unit for the purpose of detecting stress over a wide temperature range. Is preferred. As the temperature detection method, for example, the temperature dependence of the forward voltage of the semiconductor pn junction can be used. In this case, the temperature of the processor 5 is measured by supplying a constant current to the temperature detecting section and detecting the voltage of the measuring circuit. This temperature data is used for stress calculation. Note that other methods may be used as the temperature detection method. The temperature detection method described in this embodiment can also be used in the first embodiment.

In the present embodiment, it is possible to prevent breakage and malfunction of the element due to the stress generated in the semiconductor element, so that there is an effect that the reliability of the device can be improved. Further, since the electric characteristics of the element can be compensated, stable operation of the equipment using the semiconductor device can be realized.

Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a plan view of an IC card equipped with a semiconductor element 6 having a stress sensing section and a processor built into a package. In this embodiment, two semiconductor elements 6 having the same function are built in the IC card. In a normal use state, input / output with the outside of the card is performed by one element, and the other element is operated in exactly the same manner only in the memory circuit. However, the stress measurement in each element shall always be performed. The operation flow of stress measurement in each element will be described with reference to FIG. At step F10, the stress generated by each stress sensing portion is measured in the measuring circuit. Next, when there are a plurality of stress sensing parts, the maximum value σ _m of the generated stress is obtained in step F20. Then, in step F30, the magnitude relationship between the maximum stress σ _m in the arithmetic circuit and the allowable value σ _c provided in the memory circuit is determined. The setting of the allowable value σ _c is the same as in the first embodiment. When the generated stress σ _m is σ _c or more, σ _m is σ _{c in} step F40.
If it is smaller, proceed to step F60. In step F40, a warning signal is generated from the output circuit in order to notify the outside that the generated stress exceeds the allowable value. As the warning signal, for example, a sound is generated or a warning is displayed on the display unit 12 on the surface of the card. Then, in step F50, the presence of warning signal output is recorded in the memory circuit as data, and the process returns to step F10. In this case, the warning signal is continuously output while the generated stress is larger than the allowable value σ _c . If the generated stress σ _m is smaller than the allowable value σ _c or the user of the card removes the cause of the stress generation by the warning signal and σ _m becomes smaller than σ _c , the process proceeds to step F60. At step F60, it is judged whether or not the data with warning output is stored in the memory circuit. If the data with the warning output is not entered, it is determined that the semiconductor device continues to operate normally, and the process returns to step F10. If the data with warning output is entered, the process proceeds to step F70 to check the electrical characteristics in order to diagnose the presence or absence of a device failure. If there is no abnormality in the element characteristics, the process proceeds to step F80 and the warning output data of the memory circuit is deleted and step F10
Return to. If the element characteristics are abnormal, the process proceeds to step F110. In step F110, the element operation is stopped, abnormal data is recorded in the memory circuit, and the occurrence of abnormality is displayed on the card display unit. When the element operation is stopped, the stored information up to that point is retained. In the above operation flow, if the abnormality occurs in two elements, the card cannot be used, but if the abnormality occurs in only one element, the card can be used continuously. That is, if an error occurs in an element that does not perform input / output of the two elements, the usage state up to that point can be continued, and immediately if an error occurs in the element that is performing input / output. The other element performs input / output operation and retains the card function. It should be noted that when at least one element has an abnormality, the card is to be replaced, and it is possible to temporarily continue the use. In the present embodiment, calculation processing from stress measurement and output of the result are performed independently for each element, but it is possible that the element is destroyed due to the sudden generation of load and failure diagnosis cannot be performed. To be Therefore, the mutual diagnosis system may be configured such that the failure diagnosis is performed by the element having the smaller stress generated by the two elements. In this case, signal transmission to the output circuit is also performed. Further, in the present embodiment, the memory circuit is operated by two elements at the same time, but the memory circuit on the element side which does not normally perform input / output does not always need to be operated at all times, and may be used for backup. In this case, the stored data is transferred at the moment when the stress generated at step F30 exceeds the allowable value in the flow of FIG. Or step F7
A method such as transferring data at the moment when the element characteristic abnormality is found at 0 may be used. In addition, when transferring all data, if it is not necessary to transfer all the data,
It is also possible to use a method of assigning an importance rank to data in advance and transferring the data in descending order of importance. Also, two elements having the same function arranged in the card may be abnormally provided.

In this embodiment, by self-diagnosing the stress generated in the semiconductor element, it is possible to prevent the element from being destroyed in advance, and to make it possible to retain the stored data even if the element is destroyed. Since the heavy system is adopted, there is an effect that the reliability of the IC card device can be improved.

〔The invention's effect〕

As described in detail above, according to the present invention, at a stage before a semiconductor device fails due to the generation of stress, its state is grasped at an early stage and its preventive measures are taken, so that the failure is significantly reduced. can do. Moreover, because of this,
The reliability of the semiconductor device can be significantly improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing an example of a semiconductor device, FIG. 3 is a block diagram of the processor in FIG. 1, FIG. 4 is an operation flow diagram in the embodiment of FIG. 1, and FIGS. 5A and 5B are other examples of the present invention. FIG. 6 is an operation flow chart of the embodiment shown in FIG. 5A and FIG. 5B, and FIGS. 7 to 9 are diagrams showing arrangement examples of stress detecting portions on a semiconductor element. FIG. 10 is a diagram showing another embodiment of the present invention, and FIG. 11 is an operation flow chart in the embodiment of FIG. 5 ... Processor, 6 ... Semiconductor element, 7 ... Power supply, 8 ... Package, 9 ... Package, 10 ... Stress detecting section, 11 ... Lead frame, 20 ... Alarm sound generating section, 30 ... Display section, 40 ... Power supply,
50 ... Printed circuit board, 51 ... Measuring circuit, 52 ... Arithmetic circuit, 53 ...
Memory circuit, 54 ... Input / output circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Tachido 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Machinery Research Institute, Hiritsu Manufacturing Co., Ltd. (56) References JP 58-202559 (JP, A) JP 58-75851 (JP, A) JP 53-87172 (JP, A) Actual development 57-132469 (JP, U) US Patent 4739381 (US, A)

Claims (5)

[Claims] 1. In a semiconductor device in which a semiconductor element is built in a package, a stress detecting means for detecting a stress generated in the semiconductor element itself is incorporated in the semiconductor element, and further an operation is performed by receiving an output of the stress detecting means. The semiconductor device is characterized in that the preventive means is provided in the package. 2. The semiconductor device according to claim 1, wherein the preventive means issues an alarm when the stress detected by the output of the stress detecting means exceeds a predetermined value. A semiconductor device characterized by: 3. A semiconductor device according to claim 1, wherein the preventive means comprises a processor and an alarm unit for issuing an alarm by the output of the processor. 4. A semiconductor device in which a semiconductor element is built in a package, wherein a plurality of semiconductor elements are provided in the same package, and a stress detecting means for detecting a stress generated in each semiconductor element is provided in each semiconductor element. And a preventive means for outputting a preventive signal when the detection output of the stress detecting means exceeds a predetermined value in the package. 5. A semiconductor device according to claim 4, wherein the preventive means comprises a processor and an alarm unit for issuing an alarm according to the output of the processor.