JPH0740579B2 - Internal observation method - Google Patents

Description

The present invention relates to a potential measuring device for a sample surface by an electron beam, and more particularly to an electron beam tester device for measuring a DC voltage level of an LSI with a protective film.

[Conventional technology]

The conventional method for observing the internal operation of LSIs with a protective film using an electron beam tester is Tosho et al. “Impact on the potential measurement of insulating film” (Japan Society for the Promotion of Science, 132nd Committee, 82nd Meeting, Research Committee Material)
As described above, the wiring under the protective film was observed using the high-speed multiple phase scanning method.

There was also a method of observing by opening a window by removing the protective film with an ion beam, as described in “Massahashi et al.,“ LSI Failure Analysis by Electron Beam Tester ”(Technical Research Report of the Institute of Electronics and Communication Engineers, SSD83-152).

[Problems to be solved by the invention]

The above-mentioned first conventional example has a problem that it is effective only when the signal inside the LSI is changing, and the potential cannot be observed when the level is not changing. In the second conventional example, the potential level when the signal does not change can be observed. The problem remains that a special processing device such as an ion beam processing device is required to open the observation window.

An object of the present invention is to solve the problems of the conventional observation technique and to provide an electron beam tester device capable of observing the DC voltage level of LSI internal wiring with a protective film.

[Means for solving problems]

The above-mentioned purpose is the Vcc electrode or GND electrode of the observed circuit,
Alternatively, it can be achieved by superimposing a minute voltage change on both sides, detecting the minute voltage change signal transmitted from the power supply terminal to the output terminal of the circuit with an EB tester, and comparing this with the applied signal to the power supply. It

[Action]

The present invention relates to the ON state (“High”) and OFF of the LSI internal logic circuit.
By using the characteristic of the impedance between the power supply and the output terminal in the state (“Low”), the minute voltage generated by the pulse generator is superimposed on the normal voltage supplied to the Vcc and GND electrodes, The output terminal can be observed without inverting the internal logic depending on the voltage.

〔Example〕

 An embodiment of the present invention will be described below.

FIG. 2 is a sectional view of the CMOS inverter. From the figure, LS
I This shows the principle of the non-contact observation method for internal signals. In the figure, the source P + diffusion layer 7, the drain P + diffusion layer 8 and the gate electrode 2 form a PMOS transistor. Similarly, an NMOS transistor composed of the drain N + diffusion layer 9, the source N + diffusion layer 10 and the gate electrode 2 is formed and combined with a PMOS.
Use a CMOS inverter circuit. The logic of the inverter output 3 is determined according to the input signal of the gate electrode 2. At this time, when the gate input 2 is a constant signal, the output signal 3 also has a constant value. In the LSI internal observation method using the electron beam tester device, when the electron beam 1 is observed through the surface protection film 13, the signal on the surface of the protection film is output because the protection film electrically functions as a capacitance. When 3 is constant, the surface of the protective film
There is no change in the signal of 14 and it is not possible to distinguish between logic "1" and "0". The present invention provides a method of observing the logic level of the output 3 by applying an observation signal to the Vcc / GND signal system as an observation method of the internal logic level in such a state.

The principle of the present invention will be described with reference to FIGS. FIG. 3 shows a case where a logic level "1" is detected. Vcc electrode input signal 1
The voltage change ΔVcc is superimposed on 6 '. When the input signal 15 'of the inverter is at "0" level, the PMOS transistor is on and the NMOS transistor is off. Therefore, the output
18 becomes Vcc + ΔVcc, and in the electron beam observation through the capacitance of the protective film as shown in Fig. 2, the signal change ΔVcc
Is observed. When the input signal 15 'is at "1" level, the PMOS transistor is off and the NMOS transistor is on. The GND applied 17 'is output to the output 18, so in the electron beam observation, the signal 1 input to the Vcc electrode
The 6'voltage change ΔVcc is not observed. Therefore, output 1
The logic level can be identified by the presence or absence of the voltage change ΔVcc of 8 ′.

FIG. 4 shows the case where the voltage change ΔVcc is superimposed on the GND electrode 17, and the PMOS transistor is in the cutoff state as in FIG.
When the NMOS transistor is in the conductive state, the logic level can be identified by the presence or absence of the voltage change ΔVcc of the output 18. Further, FIG. 5 shows the case where the identifiable voltage changes ΔVcc and ΔVcc are superimposed on the Vcc electrode 16 and the GND electrode 17, respectively.
It is possible to identify the logic level depending on which voltage change is output.

FIG. 1 is a configuration diagram of an electron beam tester device having a strobe observation function of the present invention. In FIG. 1, DC power supply
26 and the LSI input signal generation circuit 29 are for operating the observation LSI 19, irradiating the observation LSI 19 with the electron beam 20,
The detector 21 detects the secondary electrons that have passed through the grid 23, so that the potential waveform is displayed by the waveform display 22. Further, the observation using the strobe method can be performed by synchronizing the LSI input signal generation circuit 29 and the electron beam 20 with the phase adjuster 24 via the pulse oscillator 25 and the pulse gate 30. In addition to these devices, this device has a pulse generator 27 that generates a minute voltage to be supplied to the Vcc and GND electrodes of the observation LSI, and an adder circuit 28 that synthesizes the potentials of the DC power supply 26 and the pulse generator 27. It was newly established. The newly installed device will be described below. In the observation LSI 19, the voltage applied to the Vcc electrode 31 and the GND electrode 32 is the pulse signal of ΔVcc, ΔVss generated by the pulse generator 27 and the DC voltage Vcc / GND from the DC power supply 26, via the adding circuit 28. By adding, it becomes Vcc + ΔVcc, GND + ΔVss. In this case, the condition is the pulse voltage Vcc + Δ applied to the Vcc electrode.
Make sure that the lower limit of Vcc does not fall below the logical threshold.
Also, by ensuring that the upper limit of the pulse voltage GND + ΔVss applied to the GND electrode does not exceed the logical threshold,
The internal state can be observed without abnormal operation of the internal logic state with respect to the application of ΔVcc, Vss. further,
In order to observe in the state where the through current does not flow, | V _TH |> V _S −V _G where V _TH is the device threshold voltage, V _{S is the} source applied voltage, and V _G is the gate applied voltage. Can be set as follows.

The electron beam tester apparatus of the present invention can observe the internal logic state regardless of the logic structure. This will be described with reference to FIG. In the CMOS circuit in the figure, as an example, if an arbitrary signal is input to inputs 35 to 39 and it is assumed to be in a constant state, observation points 43 to
46 is either "1", "0", or "indeterminate". By comparing this observed waveform with the applied signals to the Vcc electrode 41 and the GND electrode 42, the logic level can be identified.
In addition, this device is not limited to CMOS circuits, but can also monitor DC voltage levels in PMOS circuits, NMOS circuits, and bipolar circuits. Furthermore, even in analog circuits, ΔVcc and ΔV
Since the impedance ratio with ss is known, it can be used for analog circuit analysis.

〔The invention's effect〕

According to the present invention, in the electron beam tester device, the DC voltage level of the LSI with the protective film can be determined, which is effective for the operation and failure analysis.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an electron beam tester device of the present invention, FIG. 2 is a sectional structural view of a CMOS inverter circuit, and FIG. 3 is an operating state when a pulse voltage is applied to the Vcc electrode of the CMOS inverter circuit. And input / output signals, and FIG. 4 shows the third
Similar to the figure, a diagram showing the case where a pulse voltage is applied to the GND electrode, FIG. 5 is a diagram showing a case where different pulse voltages are applied to the Vcc electrode and the GND electrode as in FIG. 3, and FIG. 6 is a CMOS composite It is a logic diagram of a circuit. 1 ... Electron beam, 2 ... Gate electrode, 3 ... Inverter output, 4 ... Vcc electrode, 5 ... GND electrode, 6 ... Al wiring, 7 ... Source P + diffusion layer, 8 ... Drain P + diffusion layer, 9 ... Drain N + diffusion layer , 10 ... Source N + diffusion layer, 11 ... P-well,
12 ... N substrate, 13 ... Protective film, 14 ... Observation points on protective film, 15,1
5 ', 15 ", 15 ... Inverter input, 16,16', 16", 16 ...
Vcc electrode input, 17,17 ', 17 ", 17 ... GND electrode input, 18,1
8 ', 18 ", 18 ... Inverter output, 19 ... Observation LSI, 20 ... Electron beam, 21 ... Secondary electron detector, 22 ... Waveform display, 23 ... Grid, 24 ... Phase adjuster, 25 ... Pulse oscillator, 26 … DC power supply, 27… Pulse generator, 28… Addition circuit,
29 ... LSI drive circuit, 30 ... EB pulse gate, 31 ... Vcc electrode, 32 ... GND electrode, 33 ... LSI input signal, 34 ... Observation point, 35-
39 ... Composite circuit input, 40 ... Composite circuit output, 41 ... Vcc electrode, 4
2 ... GND electrode, 43 ... Inverter.

Claims (6)

[Claims] 1. A step of installing an LSI pattern with a protective film, which is a sample, on a sample stage in a vacuum container, a step of applying an observation signal in which a DC voltage and a time-varying voltage are superimposed on the sample, The step of irradiating a sample with a primary electron beam emitted from an electron source to a diaphragm protective film by an electron optical system, the step of performing energy analysis and detection of the secondary electron beam from the protective film, and the sample based on the detection result. A method for observing the inside of a sample, characterized by discriminating and observing the logical state of an internal circuit. 2. The method for observing the inside of a sample according to claim 1, wherein the voltage that changes with time is a pulse voltage. 3. The method according to claim 1, wherein the step of applying the observation signal is a step of superimposing and applying to one of a power source and a ground of the sample.
The method for observing the inside of a sample according to any one of items. 4. The step of applying the observation signal to a power supply, wherein the lower limit value of the observation signal is set to be not smaller than a threshold voltage.
The method for observing the inside of a sample described in the item. 5. The inside of the sample according to claim 3, wherein the step of applying the observation signal to the ground is such that the upper limit value of the observation signal does not exceed a threshold voltage. Observation method. 6. The sample is a MOS type circuit, and when the threshold voltage V _TH , the gate voltage V _G , and the source voltage V _S , | V _TH |> V _G −V _S The method for observing the inside of a sample according to claim 4 or claim 5.