JPH0738576A - Cell assembler/disassembler - Google Patents

Abstract

PURPOSE:To simplify the control of buffers on the transmission side and the reception side and to efficiently use the buffers. CONSTITUTION:The cell disassembler is composed of a cell reception circuit 11, buffer 1 for cell disassembler, write control means for cell disassembler, read control means for cell disassembler, and STM line transmission circuit 14, the cell assembler is composed of an STM line reception circuit 15, buffer 2 for cell assembler, write control means 16 and 5 for cell assembler, read control means 17 and 6 for cell assembler and cell transmission circuit 18, and the buffer 2 for cell assembler and the buffer 1 for cell disassembler are composed of areas divided into N pieces, and controlled by the write control means 16 and 5 for cell assembler and the read control means 17 and 6 for cell assembler.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell assembling / disassembling apparatus for transmitting / receiving data via an STM line in which a large number of channels are multiplexed and assembling / disassembling cells for each channel.

[0002]

2. Description of the Related Art Conventionally, a data transmission system is known in which a cell assembled on the transmission side is transmitted via an STM line and a cell received on the reception side is disassembled. At the cell disassembly side (reception side), ATM (Asynchr
onous Transfer Mode: Receives an asynchronous transfer mode (Asynchronous Transfer Mode) cell and returns the original STM (Synchronous Transfer Mode).
e: Synchronous transfer mode) When converting to a data string, that is, when multiplexing AAL (ATM Adaptation Layer) processing, the header VPI (Virtu) of the received ATM cell
al Path Indentifier) / VCI (Virtual Channel Id)
First, the channel of the STM line to be exchanged is identified by the entifier) and the cell is stored in the buffer corresponding to the channel. Under appropriate fluctuation absorption control, the data is read from the buffer in sample units in synchronization with the corresponding TS (time slot) position of the STM multiplex line and converted into STM data. The reception buffer logically corresponds to the channel, and N buffers are required in the case of N line multiplexing.
Considering the capacity of one buffer, for example, if a fixed delay of 6 ms is added to absorb fluctuations, 64 kb / s
In the case of a call, one cell arrives during that time, but 1.5
In the case of Mb / s (64 × n: n = 24), there is a possibility that 24 or more will arrive. That is, for a speed of 64 kb / s, the required buffer amount increases as n increases. If the buffer capacity for each channel is large enough, any speed can be supported, but in this case the amount of memory required is enormous, which is not a practical method.

Therefore, as a method of effectively using the reception buffer memory, a buffer for each channel is not fixedly allocated, but a common memory is prepared as a whole, and a necessary buffer is secured every time a cell is received. Can be considered. However, according to this method, since the buffer is allocated to each cell, the usage of the buffer becomes very efficient, but on the contrary, the buffer control for that purpose becomes complicated. Particularly, in the case of aiming for high multiplexing processing, the complication leads to an increase in processing time, affects the achievable multiplicity, and substantially limits the achievable multiplicity.

On the contrary, on the cell assembly side (transmission side), it is basically necessary to send out the assembled cell immediately, and even if a processing delay occurs due to implementation, the order of several ms is allowed by the system design. Not done. Therefore, the buffer size may be smaller than that on the receiving side, especially 64 kb /
Considering the case of s, the assembly of the cell is about 6 m
Since s, one cell is completely assembled, and the next cell is not completely assembled by the time the cell is completely transmitted. Therefore, the buffer capacity per channel may be one to two cells. But (64k
b / s) × n and n is particularly large, for example, n
When = 96, three cells may continuously occur within one frame (125 μs). If a transmission waiting delay of a cell of another channel or a processing delay due to the implementation due to the multiplexing process occurs in the order of several μs, the buffer capacity becomes 1 to 2
If there are only cells, overflow will occur. Conventionally, a method considering a call of various speeds of (64 kb / s) × n and a high multiplexing process has not been sufficiently studied, so that the cell assembly buffer on the transmission side has a fixed capacity buffer for each channel. It was normal. However, as described above, the transmitting side is required to have a method of appropriately allocating the buffers according to the speed n, as in the receiving side.

[0005]

As described above, if the buffer control is fixedly assigned to each channel in advance, the control can be simplified, but conversely, it may be necessary to effectively use the buffer. There is a problem that the control becomes complicated when trying to realize the allocation flexibility. An object of the present invention is to provide a method of efficiently using a buffer while aiming at simplification of control by using fixed allocation as a basis.

[0006]

According to the present invention, in order to achieve the above object, an input cell can transmit information at a speed of n times (n ≧ 1) times a basic speed of 64 kb / s. In a cell disassembling device for converting into channel information of a synchronous transfer mode (STM) line multiplexed with N channels at 64 kb / s conversion, the cell disassembling device comprises a cell receiving circuit, a cell disassembling device buffer, and a cell disassembling device. The write control means, the cell disassembly device read control means, and the STM line transmission circuit are provided. The cell disassembly device buffer is composed of N divided areas, and the area is a specific number k1 of cell buffers. And a write control means for the cell disassembling device for the cell disassembling device corresponding to the channel number of the STM line to be output based on the information in the cell header of the cell receiving circuit output. The area number to be written to the buffer and the cell buffer number in the area are calculated, and when the cell buffer number in the area becomes k1, the cell buffer number is initialized and the order of n area numbers to be used is calculated. The area number to be accessed next is output by the first memory that has designated, and write control of the cell disassembly device buffer is performed.
The area number to be read from the cell disassembly device buffer corresponding to the channel number to be output by the M line transmission circuit, the cell buffer number in the area, and the data to be transmitted to the STM line out of the cell information stored in the cell buffer. The STM data read address indicating the position is calculated, and when the cell buffer number in the area becomes k1, the cell buffer number is initialized, and the second memory that specifies the order of the n area numbers to be used is used. The area number to be accessed next is output, the write control of the cell disassembly device buffer is performed, and the output of the cell disassembly device buffer is output to the STM line transmission circuit.

In addition, the input cell can transmit information at a speed n times the basic speed of 64 kb / s.
In a cell assembling apparatus for making cells in asynchronous transfer mode (ATM) in a state where N-channel multiplexed synchronous transfer mode (STM) lines are converted to kb / s, the cell assembling device includes an STM line receiving circuit, A cell assembling device buffer, a cell assembling device write control means, a cell assembling device reading control means, and a cell transmission circuit, and the cell assembling device buffer is composed of N areas. The area has a specific number of k2 cell buffers, and the cell assembly device write control means writes the cell assembly device buffer write area number corresponding to the channel number to be output by the STM line sending circuit, and the area. Cell buffer number in the internal buffer and the cell information stored in the cell buffer that should be written from the STM line. The STM data write address indicating the data position is calculated, and when the cell buffer number in the area becomes k2, the cell buffer number is initialized and the third memory that specifies the order of n area numbers to be used The write control of the cell assembling device buffer is performed by outputting the area number to be accessed next, and the cell assembling device read control means causes the channel number of the STM line corresponding to the information of the cell header to the cell transmission circuit. The read area number to the buffer for cell assembling device corresponding to the above and the cell buffer number in the area are calculated, and when the cell buffer number in the area becomes k2, the cell buffer number is initialized and used. Do n
By the fourth memory that specifies the order of the area numbers,
Next, by writing the area number to be accessed, write control of the cell assembling device buffer is performed, and the output of the cell assembling device buffer is output to the cell transmission circuit. Further, a cell assembling / disassembling apparatus is configured from the above cell disassembling apparatus and cell assembling apparatus.

[0008]

When the cell assembling / disassembling apparatus of the present invention is used, 1
One buffer capacity may be a capacity required when used as a 64 kb / s call, and is (n) in the case of (64 kb / s) × n.
This has an effect that the control of each buffer can be performed easily and the control information memory necessary for the control can be reduced.

[0009]

EXAMPLE A first example of the present invention will be described. Now 64
Consider a case where a call having a speed of (64 kb / s) × n is multiplexed in a line having a capacity capable of N-channel multiplexing at a speed of kb / s. 64 kb on STM lines
Time to send 1 sample (8 bits) at a speed of / s 12
N samples are time-position multiplexed at 5 μs. When that time position is called a time slot (TS), it is 125 μs.
There are N valid TSs in one frame of 64 kb / s
Channels, that is, one of the T if n = 1
Communication is performed by occupying S. Therefore, the channel number (time slot number T
S) can be made to correspond one-to-one, and N cell assembling device buffers and disassembling device buffers can be fixedly allocated in correspondence with their channel numbers (time slot numbers TS). Ie 64k
In the case of a b / s call, the cell assembly / disassembly number to be used can be obtained from the channel number (time slot number TS), the address for storing the received TS data can be obtained, and the storage location of the received cell can be addressed. You can easily.

When the speed is (64 kb / s) × n, the required buffer capacity is variable according to n, and the TS allocation method is variable for each call. Therefore, the buffers can be fixedly allocated. It will be difficult. However, considering that the required buffer capacity of a channel having a speed of (64 kb / s) × n is n times that of a 64 kb / s call,
It is only necessary to use n fixed-capacity 64 kb / s buffers as buffers for the channel. That is, in the case of a speed of (64 kb / s) × n, communication is performed by occupying n TSs in one frame, so that each of the n TSs is 6 as a cell assembly / disassembly device buffer.
A buffer corresponding to each channel number (time slot number TS) when used as 4 kb / s may be used. 64 kb / s because n buffers are used
It can use n times the capacity of a call and can reasonably use the buffer without increasing the overall capacity. The n buffers used in this way are buffers corresponding to the TS used by the (64 kb / s) × n channel, and therefore do not overlap with the buffers used by other channels.

The above-described first embodiment of the present invention will be described in detail with reference to FIG. In FIG. 1, 1 is a cell disassembling device buffer, 2 is a cell assembling device buffer, and 3 to 6 are write / read address control circuits of the respective buffers, which are the central components of the first embodiment. Also, 7 and 10 are cell multiplexed lines, and 8 and 9 are STM.
Multiplex line, 11 cell receiving circuit, 12 write control circuit, 13 read control circuit, 14 STM line sending circuit, 15 STM line receiving circuit, 16 write control circuit, 17 read control circuit, 18 cell It is a sending circuit.

The cell disassembling apparatus buffer 1 and the cell assembling apparatus buffer 2 are composed of N areas each having a capacity of storing k1 and k2 cells, for example, TS1 (time slot 1) is 64 kb. /
When used as a channel for s, the area of BNUM (buffer area number) 1 is used as a buffer for the cell assembling / disassembling device of that channel, and TS1 to TS
If 6 is set to a 384 kb / s (64 × 6: n = 6) channel, that channel uses 6 areas of BNUM1 to 6 as its buffers. At this time, the address control units 3 to 6 determine which of the N areas each channel uses and which position in the area to write or read. In the above example, when TS1 to TS6 are respectively set as 64 kb / s channels, for example, BNUM1 to 6
Should be used as a buffer for each channel, and if set as a 384 kb / s channel, BNUM1-6 should be used as a buffer for that channel. That is, even if the channel speed can be arbitrarily changed, it is not necessary to increase the total buffer capacity according to the maximum speed.

However, a problem is how to easily control the addressing by using the n separate buffer areas as a buffer of one channel. As the address control means, specifically, means for controlling the writing of the cells arriving at the cell disassembly device buffer (cell reception buffer) (3, 12 in FIG. 1) and read control means for the cell disassembly device buffer (the same as the above). 4, 13), write control means (5, 16) and read control means (6, 17) of the buffer for cell assembling apparatus, and processing combining them.

An embodiment relating to the addressing control method of the cell reception buffer of the present invention will be described with reference to FIG. Figure 2
1 schematically shows a portion including the cell disassembly device buffer 1, the address control circuit 3, the cell reception circuit 11, and the write control circuit 12 shown in FIG. As shown in FIG. 2, the address control circuit 3 for controlling the write address to the cell disassembly device buffer 1 has three tables 10.
1 (TABL1), 102 (TABL2), 103 (T
ABL 3).

101 (TABL1) is a cell header (V
Channel number (CHN: 10 for each PI / VCI) value
It is a table where 4) is written. 102 (TABL2)
Is a table storing the control information for each channel number CHN. The types of the control information include information necessary for determining whether the received cell is correct, information necessary for obtaining a memory address for storing the cell in the buffer, and the like. As information necessary for the latter, information indicating the buffer area number (BNUM: 105),
For example, assuming that the area has a capacity capable of storing k1 cells, there is information (CEN: 106) indicating which number (cell number) of the k1 cells is stored, and these are stored in a table. It is written in 102 (TABL2).

Reference numeral 103 (TABL3) is a table having a buffer area number (BNUM) as an address, and a BNUM to be used next is written for each BNUM. An example of the contents of this table is shown in FIG. In the example of FIG. 3, TS1 (time slot 1), TS3, TS5, TS
Occupy 6 TSs of 7, TS9 and TS11 and 384k
The case where a channel of b / s (64 kb / s × 6: n = 6) is set is shown. These 6 TSs are 6 each
The buffer area number (BNUM) assigned when used as a 4 kb / s call is 1, 3, 5, 7, 9,
If it is 11, the BNU is also used for this 384 kb / s call.
Controlled to use M1, 3, 5, 7, 9, 11. Information that the six buffer areas are used is written in the TABL3. That is, the value of 3 of BNUM used next is written in the address of BNUM1. Similarly, the address of BNUM3 has the value 5 of the next used BNUM, the address of BNUM5 has the value 7 of the next used BNUM, and the address of BNUM7 has the value 9 of the next used BNUM. , B
The value of 11 of BNUM to be used next is set to the address of NUM9, and the value of B to be used next is set to the address of BNUM11.
The value of 1 of NUM is written.

Next, the addressing control operation of the cell reception buffer of FIG. 2 will be described with reference to the specific example of FIG. In FIG. 2, the cell input from the cell multiplex line 7 is received by the cell receiving circuit 11, and the content of the cell header, for example, the value of VPI / VCI is output to the multiplex line 10.
The value of the VPI / VCI is converted to the channel number CHN by TABL1, and then the buffer area number BN written in the address of the channel number CHN from TABL2.
Calculate the values of UM and cell number CEN. As a result, the position in the cell disassembling device buffer where the cell input to the cell receiving circuit 11 should be written is determined. When the buffer area number BNUM is "1" and the cell number CEN is "1", the buffer 1 for cell disassembling apparatus in FIG.
You can write in the first area of. Based on the values of the buffer area number BNUM and the cell number CEN, the write control circuit 12 converts the value into a real address, and the above write processing is performed.

Next, the buffer area number BNUM105
And the value of the cell number CEN is updated by 1 by the update control circuit 108 of the cell number CEN 106, and rewritten to "2". Therefore, when the next cell of the same channel is input, that cell is stored at the position of the cell number CEN = 2 of the buffer area number BNUM = 1. If the value of k1 is 4, the area of BNUM1 becomes full at the time when the cell is stored at the position of BNUM = 1 and CEN = 4. At this time, TABL3 is searched with BNUM = 1 as an address, and a value of "3" is obtained as shown in FIG. Therefore, TABL
BNUM and CEN of 2 are rewritten to values of "3" and "1", respectively. This causes the next cell of the same channel to be addressed to the CEN = 1 position of BNUM = 3, thus this 384 kb / s channel is buffer area number 1, 3, 5, 7, 9, 11, Again 1,
Six buffer areas can be used as if they were one continuous buffer, such as 3, 5, ....

The above is an example of n = 6, but n may be any value, and when n = 1, that is, in the case of 64 kb / s, the same process can be executed, and as a result, one buffer area is obtained. Just use it. Further, in the example shown in FIG. 2, the address control circuit 3 is set to the tables TABL1, TABL2,
Although it is composed of three types of table of TABL3, it is actually possible to combine them into one table or divide them into more tables. The cell header (VPI / VCI) is the channel number C.
There is a one-to-one correspondence with HN, and T if there is no need to change
It is also possible to remove the table corresponding to ABL1. In addition, about these points, the same can be said also about the Example demonstrated below.

FIG. 4 shows the reading control means of the cell disassembly device buffer (reception side) in the first embodiment of the present invention. In FIG. 4, reference numeral 20 is an input line for information indicating the position of the time slot TS of the STM multiplex line 8, and for example, a value counted by a frame pulse and a clock is input as time slot information. 110 (TABL4)
Is a table for searching the input time slot number (TSN) for which channel data is included in the time slot, and 111 (TABL5) is a table in which the control information corresponding to the channel is included. As a concrete example,
In the TABL 5, a buffer area number BNUM, a cell number CEN, and a byte number ACT are used as information for obtaining an address for reading data from the cell disassembly device buffer.
R is listed, and the real address is calculated from those values,
After that, the update circuit 113 updates the address.
Since one byte of data is read by accessing one time slot TS, the byte number ACTR is set to 1 after reading.
Update. When the reading of one cell length is completed, the cell number CEN is updated by 1, and the byte number ACTR is returned to the initial value, for example, "1". If you know that all the cells in the buffer have been read by the cell number CEN,
As in the case described with reference to FIG. 2, the next buffer area number BNUM is read from the table TABL3, and the table TBL3 is read.
The buffer area number BNUM of ABL5 is replaced with that value. As described above, when comparing FIG. 2 and FIG. 4, basically the same control operation is performed except that the address information in byte units in FIG. 4 increases. Also, FIG.
The table (TABL3) of reference numerals 103 and 112 in FIG. 4 can be shared by using a known technique in consideration of the race condition.

FIG. 5 shows the write control to the cell assembling device buffer during cell assembling (transmission side). In FIG. 5, reference numeral 21 is a TS number control line of information indicating the position of the time slot TS of the STM multiplexing line 9. 120 (TABL6) is a table for searching which channel data is recorded in the time slot from the input time slot number (TSN).
Reference numeral 121 (TABL7) is a table in which control information corresponding to channels is recorded. As a specific example, the TABL 7 has a buffer area number BNUM, a cell number CEN, and a byte number ACTR as information for obtaining an address for writing data in the cell assembly device buffer 128.

An example of cell assembly will be described with reference to FIG. The storage address of the data of the TS number from the STM multiplex line receiving circuit 15 inputted through the TS number control line 21 in the buffer for cell assembling device is the buffer area number B of the table 121 (TABL7).
Obtained from the values of NUM, cell number CEN, and byte number ACTR, the data is written in the buffer, and then the value of byte number ACTR is updated by 1. At this time, if the value of the byte number ACTR indicates a value indicating that the cell length has been stored, it is known that the cell assembly is completed in the cell buffer, and the cell transmission control side executes the reading and transmitting process of the cell. Done. The read address of the cell data is obtained from the values of the buffer area number BNUM and the cell number CEN at that time. Buffer area number BNU
The values of M and the cell number CEN may be updated in the same manner as described with reference to FIG. In this way, even if cells of the same channel are assembled with different buffer area numbers, the cells can be read and transmitted as if the cells were assembled in sequence in one buffer.

As described above, the device of the present invention is an AT
It is applied between the M multiplex line and the STM multiplex line to perform mutual conversion. Since the cells arriving from the ATM line have fluctuations, when controlling the reading of the cells written in the cell disassembly device buffer, for example, the address control of the present invention after a certain delay from the time when the cells first arrive after the call setup. The reading of data will be started according to. At this time, if the additional delay is large, the number of cells written in the cell disassembling apparatus buffer increases, so that the capacity k1 of the buffer area may be appropriately determined so that the buffer overflow does not occur. That is, depending on the system to which the system is actually applied, k1 may be increased in the case of a system having a large fluctuation amount, and may be decreased in the opposite case to set an appropriate value of k1. Further, even if a cell arrives with a delay larger than the fluctuation absorption amount or even if cell loss occurs, for example, a cell with a silent pattern may be written in the cell disassembly device buffer under the address control of the present invention, Even in such a case, there is no problem in applying the present invention.

As described above, in the first embodiment of the present invention, the required buffer capacity can be reasonably used according to the channel speed. But,
Considering the control memory capacity required for this control, N = 20
In the case of 16 (assuming 150 Mb / s for the line), the table TABL3 has a capacity of about 22 kbits. The second embodiment of the present invention is based on the above table TABL.
It is a device that can perform the same control without the above.

Now, in a line having a capacity capable of N-channel multiplexing at a speed of 64 kb / s, if a buffer composed of N areas having a capacity required for a channel of 64 kb / s is prepared, (64 kb / s) The total buffer capacity is sufficient by allocating n areas to calls of speed xn. The problem is how to specify which n to use for each channel. When identifying which channel from the header of the received cell and determining the storage address of the buffer from the memory in which the control information for each channel is written, the information about which n cells to use is also placed in that memory. . In order to correspond to an arbitrary n, it is necessary for each channel to have an area capable of carrying information as much as possible to correspond to the maximum n. For example, if the maximum value of n is 96 (7 bits), an area having a size of 7 bits × 96 is required as control information for one channel. If the maximum number of channels (value of N) is 2016, the capacity is about 1.4 Mbits only in that area.
Therefore, the table TABL3 in the first embodiment of the present invention shown in FIG. 2 can be suppressed to about 22 kbits. In the second embodiment, the contents of the table TABL3 are folded into TABL1 and TABL2, and the control information amount of both is not increased, and the memory amount can be reduced by an amount unnecessary for the table TABL3. it can.

FIG. 6 shows a second embodiment of the present invention. Figure 6
In 41, a cell multiplex line 41 and a cell receiving circuit 42 output the header information of the received cell to the line 43.
Based on the information, a buffer address for storing the cell is obtained by the address control circuit 44, and is stored in the cell disassembly device buffer 46 by the cell disassembly device buffer write circuit 45. The address control circuit of 44 determines a buffer area number (BNUM) used by the channel based on the header content from 43 and a buffer area number (BNL).
UM), a cell position (cell number: CEN) to be stored in the area and a table (TABL2) in which a buffer area number to be used next is recorded. Figure 6
Among them, 47 is TABL1 and 49 is TABL2. The channel corresponding to a certain header (VPI / VCI) is (6
If n areas are used at a speed of 4 kb / s) × n, one of the n areas may be written in the buffer area number BNUM48 of the table 47 (TABL1). In the table 49 (TABL2), each BNUM to be used may be set in an area having n BNUM as an address so that there is no contradiction.

Explaining with a concrete example, the channel of a certain header (VPI / VCI) is (64 kb / s) ×
6 (= 384 kb / s).
Also, the buffer area number BN used by that channel
When UM is set to 1 to 6, TABL2 is set so that when the buffer area number BNUM1 is searched, 2 is obtained as the next buffer area number. FIG. 7 shows only the area 50 of the next BNUM of TABL2, and the case of the above example is shown. For TABL1, for example, BNU
Write 1 as M. First, when the cell of the channel is received, BNUM1 is obtained from TABL1, and TAB is obtained.
CEN = 1 is obtained from L2, and the cell is stored in the first area of the buffer area number BNUM1 of the cell disassembly device buffer. After that, CEN is updated by 1, and the next cell is stored in the second of BNUM1. When this operation is continued and CEN = k1, that is, BN
When all the cells are stored in UM1, the value of 2 as the next BNUM is obtained from TABL2, and the BNUM of TABL1 is obtained.
The area of is rewritten to 2. CEN of TABL2 is initialized and reset to 1. Therefore, the next cell is BNUM2
The address is controlled so as to be stored in the area of CEN = 1. Reference numeral 53 in FIG. 6 is such an update circuit, which reads the next BNUM from the TABL2, writes BNUM to the TABL1, updates CEN, and the like. In this way 1
The cells will be sequentially stored in the six areas 6 to 6. The above is an example of n = 6, but n may be any value,
In the case of n = 1, that is, in the case of 64 kb / s, the same processing can be executed, and in that case, only one buffer area is used as a result.

FIG. 8 shows a configuration relating to the read control of the cell assembling device buffer. Since reading is performed in sample units, not in cell units, information indicating the position of a sample in one cell (AC
Although the point that TR) has increased is different from that shown in FIG. 6, the other points are the same. First, the BNUM is calculated from the time slot TS using the table TABL3,
From table BBL4 from that BNUM, CEN, A
The value of CTR is read and the address of the data carrying the TS is obtained. After reading, the address is updated by updating the ACTR by 1. When the cell is completely read by ACTR, CEN is updated. The method of updating control with the value of CEN is the same as the method of FIG. In this way, data can be read from each of the n buffers on a sample-by-sample basis, similar to the receiving side of the cell.

FIG. 9 shows the structure relating to the write address control of the buffer for the cell assembling apparatus, which is basically the same as that shown in FIG. 8 and is the same as that shown in FIG. Number) to obtain the buffer address for storing the data. Since the operation procedure is the same as that in FIG. 8, description thereof will be omitted.

Finally, a simplified correspondence diagram is shown in FIGS. 10 and 11 so that the correspondence between the constituent elements described in the claims of the present application and the embodiment can be clarified.

[0031]

When the cell assembling / disassembling apparatus of the present invention is used, one buffer capacity may be a capacity required when used as a 64 kb / s call, and in the case of (64 kb / s) × n, n buffer capacity is required. You can easily control the buffer,
In addition, the control information memory required for the control can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining writing control to a cell disassembly device buffer according to the present invention.

FIG. 3 is a specific example of a table TABL3 in the present invention.

FIG. 4 is a diagram for explaining read control of a cell disassembly device buffer according to the present invention.

FIG. 5 is a diagram for explaining write control to a buffer for a cell assembling device according to the present invention.

FIG. 6 is a diagram for explaining another example of write control to the cell disassembly device buffer according to the present invention.

FIG. 7 is a specific example of a table TABL2 in the present invention.

FIG. 8 is a diagram for explaining a table operation during reading of the cell disassembly device buffer according to the present invention.

FIG. 9 is a diagram for explaining a table operation at the time of writing a buffer for a cell assembling apparatus according to the present invention.

FIG. 10 is a diagram schematically showing the configuration according to claim 1 of the present invention.

FIG. 11 is a diagram schematically showing a configuration according to claim 2 of the present invention.

[Explanation of symbols]

 1 Buffer for Cell Disassembling Device 2 Buffer for Cell Assembling Device 3, 4, 5, 6 Address Control Circuit 7, 10 Cell Multiplexing Line 8, 9 STM Multiplexing Line 11 Cell Receiving Circuit 12 Write Control Circuit 13 Read Control Circuit 14 STM Line Sending circuit 15 STM line receiving circuit 16 Writing control circuit 17 Reading control circuit 18 Cell sending circuit

Claims (3)

[Claims] 1. A synchronous transfer mode (STM) in which N bits are multiplexed in 64 kb / s conversion of an input cell, which can transmit information at a speed of n times (n ≧ 1) times the basic speed of 64 kb / s. ) In a cell disassembling device for converting into channel information of a line, the cell disassembling device includes a cell receiving circuit, a cell disassembling device buffer, a cell disassembling device write control means, a cell disassembling device read control means, and an STM. A line transmission circuit, and the cell disassembly device buffer is composed of N divided areas, and the area is a specific number k
The cell decomposing device write control means has one cell buffer, based on information of a cell header of the cell receiving circuit output,
A write area number (BNUM) to the cell disassembly device buffer corresponding to a channel number (time slot number TS) of the STM line to be output and a cell buffer number (CEN) in the area are calculated, When the cell buffer number in the area becomes k1, the cell buffer number is initialized, and the area number to be accessed next is output by the first memory which specifies the order of the n area numbers to be used. The cell disassembling device read control means is for controlling the writing of the cell disassembling device buffer, and the cell disassembling device corresponding to a channel number (time slot number TS) to be output by the STM line sending circuit. Area number (BNUM) read from the buffer for cell, cell buffer number (CEN) in the area, and the cell The STM data read address (ACTR) indicating the data position to be transmitted to the STM line in the cell information stored in the buffer is calculated, and when the cell buffer number (BNUM) in the area becomes k1, A second cell buffer number (CEN) is initialized and the order of n area numbers to be used is specified.
Of the memory for outputting the area number to be accessed next, and controlling the writing of the cell disassembly device buffer, and outputting the output of the cell disassembly device buffer to the STM line transmission circuit. Cell disassembly device. 2. The input cell is 64 kb, which has a basic speed of 64 kb / s and can transmit information at a speed n times that speed.
/ S conversion N-channel multiplexed synchronous transfer mode (S
Asynchronous transfer mode (AT
M) in the cell assembling device, wherein the cell assembling device includes: an STM line receiving circuit, a cell assembling device buffer, a cell assembling device write control means, a cell assembling device read control means, and a cell transmission device. And a buffer for the cell assembling device, the area being divided into N areas, and the area is a specific number k
The cell assembly device write control means has two cell buffers, and the cell assembly device buffer write area number corresponding to the channel number (time slot number TS) to be output by the STM line transmission circuit. (BNUM)
The cell buffer number (CEN) in the area and the STM data write address (ACTR) indicating the data position to be written from the STM line in the cell information stored in the cell buffer are calculated, and the cell buffer in the area is calculated. When the number becomes k2, the cell buffer number (CEN) is initialized, and the third memory designating the order of the n area numbers to be used outputs the area number to be accessed next. The cell assembler buffer write control is performed, and the cell assembler read control means includes a channel number (time slot number TS) of the STM line corresponding to information in a cell header to the cell transmission circuit.
When the read area number (BNUM) to the buffer for cell assembling device and the cell buffer number (CEN) in the area are calculated, and the cell buffer number (CEN) in the area becomes k2, First, the cell buffer number (CEN) is initialized, and the area number to be accessed next is output by the fourth memory in which the order of the n area numbers to be used is specified. A cell assembling apparatus for performing write control, which outputs the output of the cell assembling apparatus buffer to the cell transmitting circuit. 3. A cell assembling / disassembling apparatus comprising the cell disassembling apparatus according to claim 1 and the cell assembling apparatus according to claim 2.