JPH0738549B2 - Multistage amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistage amplifier for amplifying high frequency signals such as microwave signals, and more particularly to a multistage amplifier suitable for power amplification.

[0002]

2. Description of the Related Art A conventional multi-stage amplifier of this type, particularly a multi-stage amplifier for power amplification, has an M element as an amplifying element for high frequency signals.
Amplifiers using ES FETs were connected in multiple stages to obtain the required gain. Further, in order to obtain a required amplification output, a MES FET having a large gate width has been used as an amplification element of a post-stage amplifier.

On the other hand, in recent years, the above MES FET
In place of the above, a heterojunction FET has been widely used and put into practical use as a microwave signal amplifying element having high gain and low noise characteristics. The heterojunction FET is used as an amplifying element of a multistage amplifier that requires low noise and high gain, and contributes to a reduction in the number of amplification stages of the multistage amplifier that handles a small signal region.

[0004]

A multi-stage amplifier having a heterojunction FET as an amplifying element for both the front and rear amplifiers has a problem in that when the gate width of the heterojunction FET is increased to increase the saturation output, The gain is higher than that of the multi-stage amplifier using MES FET in both the front and rear stages. However, since the saturation output per gate width of the heterojunction FET is almost the same as that of the MES FET,
When the gain and saturation output of the multi-stage power amplifier using the heterojunction FET is designed to be the same as that of the multi-stage power amplifier using the MES FET having the same gate width as an amplifying element, the input of the multi-stage power amplifier using the heterojunction FET is reduced. The output linearity is inferior to that of the multistage power amplifier using the MES FET.

Therefore, an object of the present invention is to provide a multi-stage amplifier for amplifying power of a high frequency signal with good input / output linearity while maintaining low noise characteristics and moderately high gain characteristics.

[0006]

The multistage amplifier of the present invention comprises:
It includes a pre-stage amplifier that uses a heterojunction FET as an amplification element to amplify a high frequency signal, and a post-stage amplifier that uses a MES FET as an amplification element and receives the amplified high frequency signal from the pre-stage amplifier.

Further, one of the multistage amplifiers of the present invention is a MES having a gate width substantially the same as the gate width of the heterojunction FET and a prestage amplifier for amplifying a high frequency signal by using the heterojunction FET as an amplification element. It includes a post-stage amplifier which uses the FET as an amplifying element and receives the high frequency signal amplified from the pre-stage amplifier.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
2 is a perspective view of the embodiment shown in FIG.

Referring to FIGS. 1 and 2 together, this multistage amplifier is mounted on a printed wiring board 11 having a ground conductor 12 on the back surface. On the surface of the printed wiring board 11, the connection lines 6a, 6b, 6c and 6d and the open stubs 3a, 3b, 3c, 3d, 3e and 3f,
Pattern wiring is performed between the ground conductor 12 and the ground conductor 12 so as to have an appropriate value of characteristic impedance and line length. Further, another circuit element of the multistage amplifier, which will be described later, is mounted on the surface of the printed board 11.

The high frequency signal S1 such as a microwave band signal received by the input terminal 1 is passed through the connection line 6a and the chip capacitor 2a for signal coupling to the gate terminal of the heterojunction FET 5 which is an amplifying element of the preamplifier. Supplied.
The heterojunction FET 5 amplifies the high frequency signal S1,
An amplified signal S2 is produced at the drain terminal. Amplified signal S2
Is connected to the MES F which is the amplification element of the post-stage amplifier via the connection line 6b, the chip capacitor 2b and the connection line 6c.
It is supplied to the gate terminal of ET7. MES FET5
Amplifies the amplified signal S2 and produces an output signal S3 at the drain terminal. This output signal S3 is the chip capacitor 2
is supplied to the output terminal 8 via c and the connection line 6d,
It becomes the output signal of this multistage amplifier.

The open stub 3a connected to the gate terminal of the heterojunction FET 5 forms the input matching circuit of the preamplifier. Further, the open stubs 3b and 3c connected to different positions on the connection line 6b and the open stubs 3d and 3e connected to different positions on the connection line 6c together with the connection lines 6b and 6c form a multi-stage structure. Form an interstage matching circuit for the amplifier. further,
The open stub 3f connected to the drain terminal of the MES FET 7 forms an output matching circuit of the post-stage amplifier.

The two source terminals of the heterojunction FET 5 are connected to the ground conductor 12 via the through holes 13a and 13b, respectively, and the two source terminals of the MES FET 7 are connected to the ground conductor 12 via the through holes 13c and 13d. Respectively connected to. Further, each of the gate terminals of the heterojunction FET 5 and the MES FET 7 receives a gate bias voltage from bias (voltage) terminals 9a and 9c via RF choke coils 4a and 4c, respectively. Further, each of the drain terminals of the heterojunction FET 5 and the MES FET 7 receives the drain bias voltage from the bias terminals 9b and 9d via the RF choke coils 4b and 4d, respectively. RF choke coil 4
a prevents the high frequency signal S1 from leaking to the bias terminal 9a, the RF choke coils 4b and 4c prevent the amplified signal S2 from leaking to the bias terminals 9b and 9c, and the RF choke coil 4d prevents the output signal S3 from leaking. Leakage to the bias terminal 9d is prevented.

Here, the heterojunction type FET 5 which is the amplification element of the pre-stage amplifier and the MES FET 7 which is the amplification element of the post-stage amplifier in this multi-stage amplifier have substantially the same gate width and saturation output.

The reason why the gate widths of the heterojunction FET 5 and the MESFET 7 which are one of the characteristics of this multistage amplifier are made substantially equal to each other will be described below.

In this multistage amplifier, a heterojunction FE is used.
When the gate width of T5 is made wider than the gate width of MES FET7, the saturation output level of the front stage amplifier becomes larger than that of the rear stage amplifier, and the ratio of contribution of the front stage amplifier to the non-linear characteristic becomes small, so that the linearity of this multi stage amplifier is improved. Is done. However, increasing the gate width of the heterojunction FET 5 increases the drain current of the FET 5, and therefore increases the power consumption of the preamplifier, which is not preferable. Further, an increase in the gate width of the heterojunction FET 5 increases the area of the semiconductor chip on which the FET 5 is mounted, and reduces the number of FETs 5 that can be taken out from a unit area of a semiconductor wafer. It causes inconvenience such as price increase.

On the other hand, if the gate width of the heterojunction FET 5 is made smaller than that of the MES FET 7, the non-linearity of this multi-stage amplifier is reduced because the saturation output level of the pre-stage amplifier is reduced. Is also unfavorable, since the ratio of contribution of C.sub.1 increases and the amount of deterioration of linearity increases.

Therefore, in the multistage amplifiers of FIGS. 1 and 2, the heterojunction FET 5 and the MES FET 7 are considered in terms of balance of power consumption, price and nonlinear characteristics.
It can be seen that it is desirable to set the gate widths of the two to be almost equal to each other.

FIG. 3 is a diagram showing the input / output characteristics of the multistage amplifier of this embodiment in comparison with the prior art.

A shows the input / output characteristics of this embodiment, and B shows a heterojunction FE as an amplifying element also in the latter stage amplifier.
Heterojunction FET with the same characteristics (same gate width) as T5
The input-output characteristic of the multistage amplifier using is shown. It is apparent that the A according to the present embodiment is superior in the linearity of the input / output characteristic although the gain is somewhat smaller. This multistage amplifier basically maintains the low noise characteristic due to the effect of the high gain and low noise characteristic of the heterojunction FET 5 used for the preamplifier.

[0021]

As described above, according to the present invention, since the heterojunction FET is used as the amplification element of the front stage amplifier and the MES FET is used as the amplification element of the rear stage amplifier, the heterojunction FET is used as the amplification element in both the front and rear stages. It has an excellent linearity of input / output characteristics as compared with a multi-stage amplifier, and has an effect that a higher gain can be obtained in both front and rear stages as compared with a multi-stage amplifier using an MES FET as an amplification element. It is useful as a power amplifier that maintains noise characteristics.

The above-mentioned effect becomes more remarkable by making the gate width of the heterojunction FET and the gate width of the MES FET substantially equal to each other.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a perspective view of the same embodiment.

FIG. 3 is a diagram showing input / output characteristics of the multistage amplifier of the same embodiment in comparison with a conventional technique.

[Explanation of symbols]

 1 Input terminal 2a-2c Chip capacitor 3a-3f Open stub 4a-4d RF choke coil 5 Heterojunction type FET 6a-6d Connection line 7 MES FET 8 Output terminal 9a-9d Bias (voltage) terminal

Claims (3)

[Claims] 1. A front-stage amplifier that uses a heterojunction FET as an amplification element to amplify a high-frequency signal, and a rear-stage amplifier that uses a MES FET as an amplification element to receive the high-frequency signal amplified from the front-stage amplifier. And multi-stage amplifier. 2. The multistage amplifier according to claim 1, wherein the gate width of the heterojunction FET and the gate width of the MES FET are substantially the same. 3. A front-stage amplifier for amplifying a high frequency signal by using a heterojunction FET as an amplification element, and the heterojunction F
MES having almost the same gate width as the ET gate width
A multi-stage amplifier comprising: a post-stage amplifier which uses an FET as an amplification element and receives the high frequency signal amplified from the pre-stage amplifier.