JPH0738338A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPH0738338A
JPH0738338A JP18411693A JP18411693A JPH0738338A JP H0738338 A JPH0738338 A JP H0738338A JP 18411693 A JP18411693 A JP 18411693A JP 18411693 A JP18411693 A JP 18411693A JP H0738338 A JPH0738338 A JP H0738338A
Authority
JP
Japan
Prior art keywords
capacitor
voltage
input terminal
amplifier circuit
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18411693A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Saito
斎藤  光弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP18411693A priority Critical patent/JPH0738338A/en
Publication of JPH0738338A publication Critical patent/JPH0738338A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide an integrated circuit capable of suppressing the lowering of S/N due to a high frequency electromagnetic noise voltage induced to a ground line GL, while keeping a simple circuit configuration. CONSTITUTION:A plus input terminal of a first stage integral amplifier circuit (first stage amplifier circuit) 11 is connected to a ground line GL through a capacitor C' and a resistance element Rb for reducing an EMI, which are connected in series to each other. Between the + input terminal of the first stage amplifier circuit 11 and the ground line GL, the capacity is connected by the capacitor C', therefore, an external high frequency electromagnetic noise voltage (EMI noise voltage) intrudes through the capacitor C', but a voltage drop is generated in the resistance element Rb by a charge/discharge current of the capacitor C', therefore, an EMI noise voltage Vn applied to the + input terminal is reduced by this voltage drop.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、集積回路に関する。FIELD OF THE INVENTION This invention relates to integrated circuits.

【0002】[0002]

【従来技術】従来、入力信号電圧を積分し、かつ、増幅
する差動増幅回路を初段増幅回路として採用する初段積
分方式の集積回路が知られている。この初段積分方式の
集積回路の一例を図2に示す。100は初段積分増幅回
路であって、オペアンプ101の直流増幅率KdcはR
s/R=Rc/Riとおけば、Rs/Rとなる。増幅さ
れて出力される交流電圧成分は積分用の帰還コンデンサ
Cを通じて−入力端に帰還され、抑圧され、これにより
積分がなされる。
2. Description of the Related Art Conventionally, there is known an integrated circuit of a first stage integration system which employs a differential amplifier circuit which integrates and amplifies an input signal voltage as a first stage amplifier circuit. FIG. 2 shows an example of this first-stage integration type integrated circuit. Reference numeral 100 denotes a first-stage integral amplifier circuit, and the DC amplification factor Kdc of the operational amplifier 101 is R
If s / R = Rc / Ri, then Rs / R. The amplified and output AC voltage component is fed back to the negative input terminal through the feedback capacitor C for integration, and is suppressed, whereby integration is performed.

【0003】C’は+入力端と接地ラインGLとを接続
する位相補償用のコンデンサであり、帰還コンデンサC
による−入力端電位の位相遅延と同じ位相遅延を+入力
端に生じさせて出力電圧の位相遅延を補償(相殺)す
る。回路の積分時定数はCRにより決定される。また、
入力信号電圧Viが差動電圧ではなく、−入力端に入力
される信号電圧0ある場合も本質的に同じであり、この
場合には接地端Gが入力端Bを兼ねるので、B端子及び
抵抗Riは省略され、Rcはオフセット補償抵抗であ
る。200は、初段増幅回路100から入力される積分
増幅電圧Voを処理する次段の電子回路である。
C'is a capacitor for phase compensation which connects the + input terminal and the ground line GL, and is a feedback capacitor C.
The same phase delay as the phase delay of the-input terminal potential due to is generated at the + input terminal to compensate (cancel) the phase delay of the output voltage. The integration time constant of the circuit is determined by CR. Also,
This is essentially the same when the input signal voltage Vi is not a differential voltage and there is a signal voltage 0 input to the − input end. In this case, the ground end G also serves as the input end B, so that the B terminal and the resistor are connected. Ri is omitted and Rc is an offset compensation resistor. Reference numeral 200 is an electronic circuit of the next stage that processes the integrated amplified voltage Vo input from the first-stage amplifier circuit 100.

【0004】この初段積分増幅回路100は、入力信号
電圧Viに混入する高周波ノイズ電圧または信号電圧中
の不要交流成分を低減しつつ、入力信号電圧Viの直流
成分又は低周波成分を選択的に増幅できる。
The first-stage integration amplifier circuit 100 selectively amplifies a DC component or a low frequency component of the input signal voltage Vi while reducing a high frequency noise voltage mixed in the input signal voltage Vi or an unnecessary AC component in the signal voltage. it can.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記し
た初段積分増幅回路100は、コンデンサC’を通じて
接地ラインGLに容量的に接続されているので、接地ラ
インGLに誘導される高周波電磁ノイズ電圧(いわゆる
EMIノイズ電圧)がこのコンデンサC’を通じてオペ
アンプ100の+入力端に侵入し、出力電圧のSN比を
低下させるという大きな問題があった。特に、この問題
は、車体電位を擬似的に接地電位とするとともに、火花
放電が頻繁に行われるエンジンルーム内に設置される車
両用電子機器において極めて重要な課題となっていた。
However, since the above-described first-stage integral amplifier circuit 100 is capacitively connected to the ground line GL through the capacitor C ′, the high-frequency electromagnetic noise voltage (so-called) induced on the ground line GL (so-called). There is a big problem that the EMI noise voltage) penetrates into the + input terminal of the operational amplifier 100 through the capacitor C ′ and reduces the SN ratio of the output voltage. In particular, this problem has been a very important issue in vehicle electronic devices installed in an engine room where the vehicle body potential is artificially set to the ground potential and spark discharge is frequently performed.

【0006】この問題を解決する案として、初段で入力
信号電圧の増幅だけを行い、次段の積分回路で積分を行
うことも考えられる。しかし、この場合には、オペアン
プを2段接続する必要があり、回路構成の複雑化、内部
ノイズ電圧の増大、消費電力の増加などの問題が生じて
しまう。本発明は上記問題点に鑑みなされたものであ
り、単純な回路構成を維持しつつ、接地ラインGLに誘
導される高周波電磁ノイズ電圧によるSN比低下を良好
に抑圧可能な集積回路を提供することを、その目的とし
ている。
As a solution to this problem, it may be considered that only the input signal voltage is amplified in the first stage and the integration circuit is integrated in the second stage. However, in this case, it is necessary to connect the operational amplifiers in two stages, which causes problems such as a complicated circuit configuration, an increase in internal noise voltage, and an increase in power consumption. The present invention has been made in view of the above problems, and provides an integrated circuit capable of favorably suppressing a decrease in SN ratio due to a high frequency electromagnetic noise voltage induced in a ground line GL while maintaining a simple circuit configuration. Is the purpose.

【0007】[0007]

【課題を解決するための手段】本発明の集積回路は、一
方の電極が入力端に接続され他端が接地ラインに接続さ
れるコンデンサを有し、外部から前記入力端に信号電圧
が入力される初段増幅回路を備える集積回路において、
前記初段増幅回路は、前記コンデンサと直列に接続され
るEMI低減用の抵抗素子を備えることを特徴としてい
る。
An integrated circuit according to the present invention has a capacitor having one electrode connected to an input end and the other end connected to a ground line, and a signal voltage is input to the input end from the outside. In an integrated circuit equipped with a first-stage amplifier circuit,
The first-stage amplifier circuit is characterized by including a resistance element connected in series with the capacitor for reducing EMI.

【0008】一態様において、コンデンサは初段積分増
幅回路の位相補償用コンデンサである。また、初段積分
増幅回路が−入力端と出力端とを帰還コンデンサで接続
するオペアンプ形式である場合、この抵抗素子に合わせ
て帰還コンデンサと直列に対応する抵抗値の抵抗素子を
介設して、位相補償することができる。
In one aspect, the capacitor is a phase compensating capacitor of the first-stage integration amplifier circuit. Further, when the first-stage integration amplifier circuit is an operational amplifier type in which the input terminal and the output terminal are connected by a feedback capacitor, a resistance element having a resistance value corresponding to the feedback capacitor in series is provided in accordance with this resistance element, Phase compensation is possible.

【0009】[0009]

【作用及び発明の効果】初段増幅回路の入力端は、互い
に直列接続されたコンデンサ及び抵抗素子を通じて接地
ラインに接続されている。本発明の特徴をなす抵抗素子
はEMI低減用である。初段増幅回路の入力端と接地ラ
イン間にコンデンサが接続される場合には、外部高周波
電磁ノイズ電圧(EMIノイズ電圧)はこのコンデンサ
を通じて主に侵入する。すなわち、初段増幅回路の入力
端では信号電圧が極めて小さいので、侵入して信号電圧
に重畳される外部高周波電磁ノイズ電圧は大きくSN比
を劣化させる。
The input end of the first-stage amplifier circuit is connected to the ground line through a capacitor and a resistance element that are connected in series with each other. The resistance element that is a feature of the present invention is for reducing EMI. When a capacitor is connected between the input end of the first-stage amplifier circuit and the ground line, the external high frequency electromagnetic noise voltage (EMI noise voltage) mainly enters through this capacitor. That is, since the signal voltage is extremely small at the input end of the first-stage amplifier circuit, the external high frequency electromagnetic noise voltage that enters and is superimposed on the signal voltage greatly deteriorates the SN ratio.

【0010】本発明で新設したコンデンサと直列接続さ
れる抵抗素子は、このコンデンサを通じて初段増幅回路
の入力端へ流れる外部高周波電磁ノイズ電流を低減し、
これにより、集積回路の耐EMI特性を大幅に向上す
る。また、新設する抵抗素子はモノリシック又はハイブ
リッド集積回路として簡単に集積することができ、回路
構成を複雑化したり、消費電力を増加させたりすること
が無い。
The resistor element connected in series with the capacitor newly provided in the present invention reduces the external high frequency electromagnetic noise current flowing to the input end of the first stage amplifier circuit through this capacitor,
This greatly improves the EMI resistance of the integrated circuit. Further, the newly provided resistance element can be easily integrated as a monolithic or hybrid integrated circuit, and does not complicate the circuit configuration or increase power consumption.

【0011】[0011]

【実施例】本発明の集積回路の一実施例を図1を参照し
て説明する。この集積回路は、その差動入力端A,Bに
入力信号電圧Viが入力される初段積分増幅回路11
と、この初段積分増幅回路11の出力電圧を処理して所
望の信号電圧Voを出力する電子回路2とからなる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the integrated circuit of the present invention will be described with reference to FIG. This integrated circuit includes a first-stage integration amplifier circuit 11 in which an input signal voltage Vi is input to its differential input terminals A and B.
And an electronic circuit 2 that processes the output voltage of the first-stage integral amplifier circuit 11 and outputs a desired signal voltage Vo.

【0012】初段積分増幅回路1は、入力信号電圧Vi
を積分し、かつ、増幅するオペアンプ回路であって、オ
ペアンプ11の−入力端は抵抗Rを通じて集積回路の入
力端Aに接続され、その+入力端は抵抗Riを通じて集
積回路の入力端Bに接続され、これら差動入力端A,B
間に信号電圧Viが入力される。オペアンプ11の出力
端は、帰還コンデンサC及び帰還コンデンサCと直列接
続された抵抗Raとを通じて−入力端に接続され、更に
オペアンプ11の出力端は、抵抗Rsを通じて−入力端
に接続されている。
The first-stage integration amplifier circuit 1 has an input signal voltage Vi.
Is an operational amplifier circuit that integrates and amplifies, the negative input terminal of the operational amplifier 11 is connected to the input terminal A of the integrated circuit through the resistor R, and the positive input terminal is connected to the input terminal B of the integrated circuit through the resistor Ri. These differential input terminals A and B
The signal voltage Vi is input between them. The output terminal of the operational amplifier 11 is connected to the-input terminal through the feedback capacitor C and the resistor Ra connected in series with the feedback capacitor C, and the output terminal of the operational amplifier 11 is connected to the-input terminal through the resistor Rs.

【0013】オペアンプ11の+入力端は抵抗Rcを通
じ、内部接地ラインGL’、接地ラインGLを通じて接
地電極(車体)に接地されている。同様に、オペアンプ
11の+入力端はコンデンサC’及びコンデンサC’と
直列接続された抵抗Rbを通じ、内部接地ラインG
L’、接地ラインGLを通じて接地電極(車体)に接地
されている。
The + input terminal of the operational amplifier 11 is grounded to the ground electrode (vehicle body) through the resistor Rc, the internal ground line GL 'and the ground line GL. Similarly, the + input terminal of the operational amplifier 11 is connected to the internal ground line G through the capacitor C ′ and the resistor Rb connected in series with the capacitor C ′.
It is grounded to the ground electrode (vehicle body) through L ′ and the ground line GL.

【0014】この実施例では、R=Ri,Rs=Rc,
Ra=Rb,C=C’とする。以下、この初段積分増幅
回路1の作動を説明する。このオペアンプ101の直流
増幅率KdcはRs/Rとなる。入力信号電圧Viの交
流信号成分はオペアンプ11で増幅されて積分用の帰還
コンデンサCを通じて−入力端に帰還され、抑圧され、
これにより積分すなわち入力信号電圧Viの交流信号成
分が低減される。回路の積分時定数はCRにより決定さ
れる。
In this embodiment, R = Ri, Rs = Rc,
Ra = Rb and C = C '. The operation of the first-stage integral amplifier circuit 1 will be described below. The DC amplification factor Kdc of the operational amplifier 101 is Rs / R. The AC signal component of the input signal voltage Vi is amplified by the operational amplifier 11, fed back to the negative input terminal through the feedback capacitor C for integration, and suppressed.
As a result, integration, that is, the AC signal component of the input signal voltage Vi is reduced. The integration time constant of the circuit is determined by CR.

【0015】C’は+入力端と接地ラインGLとを接続
する位相補償用のコンデンサであり、帰還コンデンサC
による−入力端電位の位相遅延と同じ位相遅延を+入力
端に生じさせて出力電圧の位相遅延を補償(相殺)す
る。本実施例の特徴をなす抵抗Rb(本発明でいう抵抗
素子)は、接地ラインGL及び内部接地ラインGL’に
誘導される外部高周波電磁ノイズ電圧(EMIノイズ電
圧)VnによるコンデンサC’の充放電電流に対し、電
圧降下を生じさせ、オペアンプ11の+入力端に印加さ
れるEMIノイズ電圧Vnを低減する。
C'is a capacitor for phase compensation which connects the + input terminal and the ground line GL, and is a feedback capacitor C.
The same phase delay as the phase delay of the-input terminal potential due to is generated at the + input terminal to compensate (cancel) the phase delay of the output voltage. The resistor Rb (resistive element in the present invention), which is a feature of this embodiment, is used to charge and discharge the capacitor C ′ by the external high frequency electromagnetic noise voltage (EMI noise voltage) Vn induced in the ground line GL and the internal ground line GL ′. A voltage drop is generated with respect to the current, and the EMI noise voltage Vn applied to the + input terminal of the operational amplifier 11 is reduced.

【0016】これにより、初段積分増幅回路1の耐EM
Iノイズ性は大幅に向上する。ただ、位相補償用のコン
デンサC’と直列に抵抗Rbを接続することにより、位
相補償用のコンデンサC’を流れる位相補償電流の位相
すなわち+入力端に印加される電圧の位相も再度変化し
てしまう。そこで本実施例では、帰還コンデンサCと直
列に抵抗Raを接続することにより、−入力端に印加さ
れる電圧の位相も再度同じように位相変化させ、これに
より、抵抗Rbによる+入力端電位の位相再変化による
影響を相殺している。
Thus, the EM resistance of the first-stage integral amplifier circuit 1 is improved.
The I noise characteristic is significantly improved. However, by connecting the resistor Rb in series with the phase compensating capacitor C ′, the phase of the phase compensating current flowing through the phase compensating capacitor C ′, that is, the phase of the voltage applied to the + input terminal also changes again. I will end up. Therefore, in the present embodiment, by connecting the resistor Ra in series with the feedback capacitor C, the phase of the voltage applied to the-input end is changed again in the same manner, whereby the potential of the + input end due to the resistor Rb is changed. The effect of the phase change is offset.

【0017】もちろん、この抵抗Raにより積分時定数
が変化するが、それは抵抗Rの抵抗値を調節して補償す
ればよい。好適例において、コンデンサC’と抵抗Rb
とはEMIノイズ電圧Vnから見ればローパスフィルタ
となること、及びEMIノイズ電圧Vnの帯域が数十M
Hz以上であることから、その時定数C’Rbは、10
-8〜10-9とされる。
Of course, the resistance Ra changes the integration time constant, which can be compensated by adjusting the resistance value of the resistance R. In a preferred example, capacitor C'and resistor Rb
Is a low-pass filter when viewed from the EMI noise voltage Vn, and the band of the EMI noise voltage Vn is several tens of M
Since it is above Hz, the time constant C'Rb is 10
-8 to 10 -9 .

【0018】なお上記実施例では、R=Ri、Rs=R
c、C=C’としたが、これらの等値関係が厳密でなく
ても効果が得られることは当然である。また、R=R
i、Rs=Rc、C=C’とする代わりに、Rs/R=
Rc/Riとしてもよい。この場合には、−入力端側の
時定数CRに対して+入力端側の時定数C’Riを等し
くするために、Ri=CR/C’とすることが好まし
い。
In the above embodiment, R = Ri, Rs = R
Although c and C = C ′ have been described, it is natural that the effect can be obtained even if the equivalence relation between them is not strict. Also, R = R
Instead of i, Rs = Rc, C = C ′, Rs / R =
It may be Rc / Ri. In this case, it is preferable to set Ri = CR / C ′ in order to make the time constant C′Ri on the + input end side equal to the time constant CR on the −input end side.

【0019】更に、+入力端側の時定数C’Rbに対し
て帰還端側の時定数CRaを等しくするために、Ra=
C’Rb/Cとすることが好ましい。更に入力信号電圧
Viが差動電圧ではなく、−入力端に入力される信号電
圧であってもよい。この場合には、接地端Gが入力端B
を兼ねるので、B端子及び抵抗Riは省略され、Rcは
オフセット補償抵抗として、R/Rsの値とされる。
Further, in order to make the time constant CRa on the feedback end side equal to the time constant C'Rb on the + input end side, Ra =
C'Rb / C is preferable. Further, the input signal voltage Vi may be a signal voltage input to the-input terminal instead of the differential voltage. In this case, the ground end G is the input end B
Therefore, the B terminal and the resistor Ri are omitted, and Rc is the value of R / Rs as an offset compensation resistor.

【0020】このようにすれば、初段で増幅とともに積
分を行う簡単な回路構成及び消費電力低減を実現できる
にもかかわらず、接地ラインGLに誘導される高周波電
磁ノイズ電圧によるSN比低下を良好に抑圧することが
でき、特に車載電子機器用途において、効果的である。
In this way, although a simple circuit configuration for performing amplification and integration in the first stage and reduction in power consumption can be realized, the SN ratio is favorably reduced due to the high frequency electromagnetic noise voltage induced in the ground line GL. It can be suppressed, and is particularly effective in in-vehicle electronic device applications.

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例の集積回路の回路図である。FIG. 1 is a circuit diagram of an integrated circuit of this embodiment.

【図2】従来の集積回路の回路図である。FIG. 2 is a circuit diagram of a conventional integrated circuit.

【符号の説明】[Explanation of symbols]

1は初段積分増幅回路、C’はコンデンサ、Rbは抵抗
(抵抗素子)
1 is a first-stage integral amplifier circuit, C'is a capacitor, Rb is a resistor (resistive element)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一方の電極が入力端に接続され他端が接地
ラインに接続されるコンデンサを有し、外部から前記入
力端に信号電圧が入力される初段増幅回路を備える集積
回路において、 前記初段増幅回路は、前記コンデンサと直列に接続され
るEMI低減用の抵抗素子を備えることを特徴とする集
積回路。
1. An integrated circuit comprising a first-stage amplifier circuit in which one electrode is connected to an input end and the other end is connected to a ground line, and a signal voltage is input to the input end from the outside, An integrated circuit characterized in that the first-stage amplifier circuit comprises a resistance element for reducing EMI, which is connected in series with the capacitor.
JP18411693A 1993-07-26 1993-07-26 Integrated circuit Pending JPH0738338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18411693A JPH0738338A (en) 1993-07-26 1993-07-26 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18411693A JPH0738338A (en) 1993-07-26 1993-07-26 Integrated circuit

Publications (1)

Publication Number Publication Date
JPH0738338A true JPH0738338A (en) 1995-02-07

Family

ID=16147666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18411693A Pending JPH0738338A (en) 1993-07-26 1993-07-26 Integrated circuit

Country Status (1)

Country Link
JP (1) JPH0738338A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1312652C (en) * 2002-01-14 2007-04-25 Lg.飞利浦Lcd有限公司 Data transmission device and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1312652C (en) * 2002-01-14 2007-04-25 Lg.飞利浦Lcd有限公司 Data transmission device and method

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