JPH0738275B2 - Read-only semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a vertical read-only semiconductor memory device (hereinafter, vertical ROM
)), Particularly to a vertical ROM capable of preventing malfunction due to noise on the power supply or ground.

[Prior Art] FIG. 5 shows a conventional vertical ROM. This vertical ROM includes four memory cells MCi0 to MCi3 and memory cells MCi0 to MCi formed by N-channel MOSFETs as shown in FIG.
N-channel select MOSFET for selecting i3
A memory cell block 1 having MSi connected in series, a memory cell array 2 having a plurality of memory cell blocks 1 arranged in a column direction and a row direction, and a plurality of column lines D0 connecting the memory cell blocks 1 in the column direction. To D3, a plurality of row lines W00 to W33 connecting the memory cells MCi0 to MCi3 forming the memory cell block 1 in the row direction, and the address signals AY1 to ▲.
Y decoder 31 that receives ▼ as input and output YD of Y decoder 31
A column selection circuit 3 which is driven by 0 to YD3 and comprises N selectors YS0 to YS3 for selecting the column lines D0 to D3, and a column selection circuit 3 and an address signal AX0 to ▲ ▼ are input to a row line W00. ~ Row selection circuit 4 for selecting W33
And a memory cell block selection circuit 5 for selecting the memory cell block 1 by driving the selection MOSFET MSi by inputting the address signals AB0 to ▲ ▼, and stored in the selected memory cell in the memory cell array 1. It is composed of a sense amplifier 6 for reading data.

In FIG. 5, the Y-decoder 31 and the NOR gate (NOR) constituting the memory cell block selection circuit 5 are the P-channel MOSFET P01 and the NOR gate (NOR) as shown in FIG.
The NAND gate (NAND) that is composed of P02 and N-channel MOSFETs N01 and N02 and is between the power supply terminal VCC and the ground terminal VSS and that constitutes the row selection circuit 4 is a P-channel type as shown in FIG. 2 (c). It consists of MOSFETs P11 and P12 and N-channel type MOSFETs N11 and N12. As shown in FIG. 2 (c), the row selection circuit 4 in FIG.
And a NAND gate configured between the ground terminal VSS.

The operation will be briefly described below. For example, if the address signals AY0 and AY1 are at high level, the output of the Y decoder 31
YD0 becomes high level, YD1 to YD3 become low level, N-channel type MOSFET YS0 forming Y selector 32 turns on, YS1
~ YS3 is turned off, column line D0 is selected, and address signal A
If B0 and AB1 are at high level, the output BS0 of the memory cell block selection circuit 5 becomes high level and BS1 to BS3 become low level, and the output BS0 of the selected memory cell block selection circuit
The select MOSFET that composes the memory cell block driven by is turned on and is therefore connected to the selected column line D0, and the output BS of the selected memory cell block circuit
The memory cell block in which the select MOSFET driven by 0 exists is selected. Furthermore, address signals AX0 and AX1
Is high level, the line lines W00, W10, W20, W30 are selected as low level, and the line lines W01 ~ W03, W11 ~ W13, W21 ~ W23, W are selected.
31 to W33 become high level and become non-selected, and the memory cells existing in the selected memory cell block and driven by the selected row line are in the selected state. If the selected memory cell is an N-channel depletion MOSFET, the selected column line D0 and the ground terminal VSS are electrically connected via the selecting MOSFET because the gate potential is on even when the gate potential is low. On the other hand, if the selected memory cell is an N-channel enhancement MOSFET, the gate potential is at a low level, so the selected column line D0 is electrically cut off and the selected column line D0 is electrically disconnected. The sense amplifier 6 detects whether D0 and the ground terminal VSS are electrically connected or disconnected, and the data stored in the memory cell is read.

[Problems to be Solved by the Invention] In the conventional vertical ROM described above, since the power is directly applied to the row selection circuit, the power supply terminal and the ground terminal are coupled with low impedance, and the noise on the power supply terminal is reduced. The noise transmitted to the ground terminal or riding on the ground terminal is transmitted to the power supply terminal and the sense amplifier or the like malfunctions.

That is, in the vertical ROM, as shown in FIG. 6 (a), the selected row line Wi0 is connected to the ground terminal VSS through the N-channel MOSFETs NX00 and NX0 that form the row selection circuit, and is not selected. The row lines Wi1, Wi2 and Wi3 are connected to the power supply terminal VCC via P-channel type MOSFETs PX1, PX2 and PX3 which form a row selection circuit. N-channel type MOSFE
T NX00 and NX0 are connected to resistors RNX00 and RXN0 and P-channel type MOSF
ET PX1, PX2, and PX3 are replaced with resistors RPX1, RPX2, and RPX3, and the gate capacitance of unselected memory cells MCi1, MCi2, and MCi3 that are turned on when the power supply voltage is applied to their gates is set to Ci1, Ci2.
And Ci3 and the on-resistances are represented by RMCi1, RMCi2, and RMCi3, the equivalent circuit shown in FIG. 6 (b) is obtained. Although the gate capacitance and on-resistance of the selected memory cell MCi0 are not shown in FIG. 6 (b), since the gate is at the ground potential, it is turned off when the selected memory cell MCi0 is an N-channel type enhancement MOSFET. This is because. When the selected memory cell MCi0 is an N-channel depletion MOSFET, it is turned on, and the on resistance is the gate capacitance and the ground terminal V via the resistors RNX00 and RNX0.
Although the selected memory cell MCi0 is connected to SS, the selected memory cell MCi0 operates in almost the same manner as in the case of the N-channel type enhancement MOSFET.
Description of the case of a channel depletion MOSFET is omitted.

Further, the resistors RPX1, RPX2 and RPX3 shown in FIG. 6 (b) are connected in parallel to replace the resistor RPX, and the gate capacitors Ci1, Ci2 and Ci3 are connected in parallel to replace the capacitor CC, and the on-resistances RMCi1 and RMCi are replaced.
When 2 and RMCi3 are connected in series and replaced with a resistor RMC, the equivalent circuit shown in FIG. 6 (c) is obtained, and in a large capacity vertical ROM with a large number of memory cells, for example, RPX = 1.0Ω, C
C = 10000PF and RMC = 0.1Ω.

Here, as shown in FIG. 6 (d), the power source v and the power source terminal
Parasitic impedance ZVCC between VCC and ground pin VSS
And ZGND exist, for example, lZVCCl = 10Ω, lZGNDl = 10Ω
And lRPX + 1 / jWCC + RMCl = 1.1Ω (W = 2πf: f
= 100MHz), the parasitic impedance ZVCC existing between the power supply v and the power supply terminal VCC and the ground terminal VSS.
Power supply terminal VCC and ground terminal V
SS is coupled with a low impedance of 1.1Ω. For example, when noise of 1.0V and f = 100MHz is applied to the power supply terminal VCC, the noise VNGND transmitted to the ground terminal VSS is expressed by the following formula, VNGND = 1.0V x lZGNDl / lZGNDl + lRPX + 1 / jWCC + RMCl = 0.9V. From the result of the above formula, most of the noise riding on the power supply terminal VCC is transmitted to the ground terminal VSS, and the ground of the sense amplifier is also connected to the ground terminal VSS. The sense amplifier etc. malfunctions. Also, ground terminal VSS
If 1.0V, f = 100MHz noise is present on the power supply terminal VC
Similarly, the noise VNVCC transmitted to C becomes VNVCC = 1.0V x lZVCCl / lZVCCl + lRPX + 1 / jWCC + RMCl = 0.9V, and most of the noise riding on the ground pin VSS is also transmitted to the power supply pin VCC and the power supply for the sense amplifier etc. Since the noise is transmitted to the power supply terminal VCC, the sense amplifier and the like may malfunction.

[Means for Solving the Problems] The gist of the present invention is to provide a memory cell block in which a plurality of memory cells and a select transistor for selecting the plurality of memory cells are connected in series in a column direction and a row direction. A plurality of memory cells arranged in a row direction, a plurality of column lines connecting the memory cell blocks in a column direction, a plurality of row lines connecting memory cells forming the memory cell block in a row direction, and an address. A column selection circuit configured by a column decoder that receives a signal and a column selector that is driven by the output of the column decoder and that selects the column line;
A row selection circuit that receives an address signal and selects the row line; a memory cell block selection circuit that receives the address signal and drives the selection transistor to select the memory cell block; and the memory cell array. In a read-only semiconductor memory device including a sense amplifier for reading data stored in a selected memory cell in the memory cell, power is applied to a load element of the row selection circuit via a resistance element.

[Differences from the Prior Art of the Invention] The present invention is different from the above-described conventional vertical ROM in that the power supply terminal and the ground terminal are not coupled with low impedance.

[Embodiment] First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the present invention. For example, four memories composed of N-channel MOSFETs as shown in FIG. 2 (a). Cells MCi0 to MCi3 and memory cells
Memory cell block 1 in which N-channel select MOSFETs MSi for selecting MCi0 to MCi3 are connected in series
A memory cell array 2 in which a plurality of memory cell blocks 1 are arranged in the column direction and the row direction, a plurality of column lines D0 to D3 connecting the memory cell blocks 1 in the column direction, and a memory cell block 11 Memory cells MCi0 to MCi3 A plurality of row lines W00 to W33 connected in the row direction and address signals AY0 to ▲
N for selecting the column lines D0 to D3 driven by the Y decoder 31 and the outputs YD0 to YD3 of the Y decoder 31 to which ▼ is input.
Y selector 3 composed of channel type MOSFET YS0 to YS3
2 column select circuit 3 and address signals AX0 to ▲
A row selection circuit 4 for selecting the row lines W00 to W33 with ▼ as an input, and a memory cell block selection for driving the selection MOSFET MSi with an address signal AB0 to ▲ ▼ as an input to select the memory cell block 1 The NAND (see FIG. 2 (c)), which is composed of the circuit 5 and the sense amplifier 6 for reading the data stored in the selected memory cell in the memory cell array 1, and which constitutes the row selection circuit 4, is a resistance element.
It is connected to the power supply pin VCC via RX. The Y decoder 31 and the memory cell block selection circuit 5 in FIG.
FIG. 2 (b) shows the configuration of the NOR constituting the row selection circuit 4
The structure of the NAND constituting the above is shown in FIG. 2 (c).

Next, the operation of reading the data stored in the selected memory cell in the memory cell array 1 is completely the same as the case of the conventional vertical ROM described above, and therefore the description thereof is omitted here.

In the first embodiment shown in FIG. 1, since the NAND configuring the row selection circuit 4 is connected to the power supply terminal VCC via the resistance element RX, the power supply terminal VCC to the resistance element RX to the row selection circuit 4 are connected to each other. The equivalent circuit composed of the resistance RPX equivalent to the P-channel MOSFET to be constructed, the gate capacitance CC of the memory cell, the on-resistance RMC of the memory cell, and the ground terminal VSS is as shown in FIG. Parasitic impedances ZVCC and ZGND exist between the power supply terminal VCC and the ground terminal VSS. In FIG. 3, for example, RX = 100Ω, RPX = 1.0
Ω, CC = 10000PF, RMC = 0.1Ω, lZVCCl = 10Ω and lZGND
If l = 10Ω, lRX ＋ RPX ＋ 1 / jWCC ＋ RMCl ＝ 101.1Ω
(W = 2πf: f = 100MHz) and becomes lZVCCl or lZGND
Compared with l, power supply terminal VCC and ground terminal VSS are 101.1
Since it is coupled with Ω with a high impedance, for example, when noise of 1.0V, f = 100MHz is applied to the power supply terminal VCC,
The noise VNGND that is transmitted to the ground terminal VSS is expressed by the following formula: VNGND = 1.0V x lZGNDl / lRX + RPX + 1 / jWCC + RMCl + lZGNDl = 0.09V. From the result of the above formula, the noise on the power supply terminal VCC becomes 1/10 or less and almost no noise is transmitted to the ground terminal VSS, and the noise transmitted to the ground terminal VSS causes the sense amplifier to malfunction. There is no such thing.

In addition, when noise of 1.0V, f = 100MHz is applied to the ground terminal VSS, the noise VNVCC transmitted to the power supply terminal VCC is also VNVCC = 1.0V × lZVCCl / lZVCCl + lRX + RPX + 1 / jWCC + RMCl = 0.09V, and the noise is transmitted to the ground terminal VSS. Noise also power supply pin VCC
The noise transmitted to the power supply terminal VCC does not cause the sense amplifier to malfunction.

In the first embodiment shown in FIG. 1, the address signal
When AX0 to ▲ ▼ changes, the output of one selected NAND among the four NANDs configuring the row selection circuit 4 changes from high level to low level, and the output of one non-selected NAND outputs low level. To high level, but the remaining 2 NAs
The output of ND maintains a high level, and the gate capacitance of the memory cell connected to the output of the NAND that maintains this high level operates as a smoothing capacitance. NAND and power supply terminals that compose the selection circuit 4
Even if VCC is connected, the operation of the row selection circuit 4 is not adversely affected. Moreover, in an actual vertical ROM, a memory cell block is composed of 8 or 16 memory cells, and when the address signal changes in the NAND which constitutes the row selection circuit, 6 or 16 out of 8 Of these, 14 keep the high level, and the gate capacitance of the memory cell maintained by the output of the NAND that maintains this high level becomes a very large smoothing capacitance, and the resistance element RX of about 100Ω selects the row. It has no adverse effect on the operation of the circuit. Further, it is apparent that the same effect can be obtained by connecting an N-channel MOSFET whose gate is connected to the power supply terminal VCC instead of the resistance element RX.

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment according to the present invention.
In the first embodiment shown in FIG. 1, the NAND constituting the row selection circuit 4 is changed to the 3-input NAND as shown in FIG. 2 (d), and the NAND for driving the column lines W00 to W13 is used. Column line W2
A NAND for driving 0 to W33 is provided to drive column lines W00 to W13
By applying the address signals AB1 and ▲ ▼ input to the memory cell block selection circuit 5 to the NAND and the NAND that drives the column lines W20 to W33, the NAND that drives the column lines W00 to W13 or the column lines W20 to W33. It is configured to select only one of the NAND that drives the.

Also in the second embodiment according to the present invention shown in FIG. 4, the NAND constituting the row selection circuit is connected to the power supply terminal via the resistance element RX.
Since it is connected to VCC,
It is obvious that the same effect as that of the embodiment is obtained, and the description thereof is omitted here.

Further, for example, when the address signals AB1 and AX1 are at high level and the address signal AX0 changes from high level to low level, in the first embodiment shown in FIG. 1, the column line W0
The four lines 0, W10, W20 and W30 change from the low level to the high level and become the non-selected state, and the four column lines W01, W11, W21 and W31
The book changes from high level to low level and is in the selected state,
Eight column lines W02, W03, W12, W13, W22, W23, W32 and W33 are maintained at a high level, but in the second embodiment shown in FIG. 4, two column lines W00 and W10 are used. The book changes from the low level to the high level to the non-selected state, and the two column lines W01 and W02 change from the high level to the low level to the selected state, and the column line W0
Since 12, W03, W12, W13, W20 to W23, W30 to W33 maintain the high level, the smoothing capacity is larger (1.
Therefore, it is possible to set a larger value for the NAND element that constitutes the row selection circuit 4 and the resistance element RX that is connected to the power supply terminal VCC, and therefore the impedance of the power supply terminal VCC and the ground terminal VSS. Can also be set to a higher value, and the noise on the power supply terminal VCC can be more difficult to be transmitted to the ground terminal VSS. Further, similarly, there is also an effect that noise riding on the ground terminal VSS can be more difficult to be transmitted to the power supply terminal VCC.

[Effects of the Invention] As described above, according to the present invention, by applying power to the row selection circuit via the resistance element, the sense amplifier due to noise transmitted from the power supply terminal to the ground terminal or from the ground terminal to the power supply terminal. This has the effect of preventing malfunctions such as

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention, and FIGS. 2 (a) to (d) are circuit diagrams showing a memory cell block configuration, a NOR configuration, and two types of NAND configurations, respectively. FIG. 3 is an equivalent circuit diagram for explaining the operation of the first embodiment, and FIG.
FIG. 6 is a circuit diagram showing a second embodiment of the present invention, FIG. 5 is a circuit diagram showing a conventional vertical ROM, and FIGS. 6A to 6D are equivalent circuits for explaining the operation of the conventional example. It is a figure. MCi0 to MCi3 …… Memory cells, MSi …… MOSFE for selection
T, 1 ... Memory cell block, 2 ... Memory cell array, D0-D3 ... Column line, W00-W33 ... Row line, 31 ... Y decoder, 32 ... Y selector, 3 ... Column selection circuit, 4 ... Row selection circuit, 5 ... Memory cell block selection circuit, 6 ...
Sense amplifier, VCC …… Power supply terminal, VSS …… Ground terminal, P01, P02, P11, P12, P21, P22, P23, PX1, PX2, PX3 …… P
Channel type MOSFET, YS0 to YS3, N01, N02, N11, N12, N21, N
22, N23, NX00, NX0 ... N-channel MOSFET, RNX00, RNX
0, RPX1, RPX2, RPX3, RMCi1, RMCi2, RMCi3, RPX, RMC, RX ...
Resistance, Ci1, Ci2, Ci3, CC ... Capacity, ZVCC, ZGND ... Parasitic impedance, V ... Power supply.

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cell blocks each having a plurality of memory cells and select transistors for selecting the plurality of memory cells connected in series are arranged in a column direction and a row direction. A plurality of column lines that connect the memory cell blocks in the column direction, a plurality of row lines that connect the memory cells that form the memory cell block in the row direction, a column decoder that receives an address signal, and the column. A column selection circuit driven by the output of the decoder and configured by a column selector for selecting the column line, an address signal as an input, a row selection circuit for selecting the row line, and an address signal as an input, A memory cell block selection circuit that drives the select transistor to select the memory cell block; and a selected memory cell block in the memory cell array. In read-only semiconductor memory device including a sense amplifier for reading data stored in Moriseru, the load element of the row selection circuit through a resistive element, a read-only semiconductor memory device and applying the power.