JPH0738001A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To form a floating gate easily without lowering the degree of integration by forming a side-wall oxide film on the side wall of a polysilicon layer to be a floating gate, and providing a spacer oxide film additionally so as to cover the oxide film. CONSTITUTION:A parallel beltlike laminated part G composed of a polysilicon layer 5a, a silicon nitride film 8, and a silicon oxide film 11 is selectively formed on a thermal oxide film 4 formed on the surface of a semiconductor substrate 1. A side-wall oxide film 5d sacrificial is formed on the side wall of the polysilicon layer 5a of the first conductor layer of the beltlike laminated part G, and a spacer oxide film 7' is formed so as to cover the side-wall oxide film 5d. Consequently, it becomes possible to prevent the length of a gate or channel from shrinking, by suppressing the generation of gate bird's beaks in the next thermal oxidation process by this spacer oxide film 7'. Besides, gate sections G1-G4 are averaged by the spacer oxide film 7'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device in which a floating gate can be formed by a self-alignment method or thermal oxidation while increasing the degree of integration by setting a small gate length. And is suitable for, for example, a method for manufacturing a non-volatile semiconductor memory device having two transistors having a common source diffusion layer as a minimum unit. In particular, the source / drain diffusion layer is used as a wiring layer and The present invention relates to a method for manufacturing a semiconductor memory device in which a relatively thick thermal oxide film is formed on a diffusion layer.

[0002]

2. Description of the Related Art FIG. 13A is a sectional view showing a conventional nonvolatile semiconductor memory device, in which a field oxide film 2 is formed on a semiconductor substrate 1. The field oxide film 2
A common source diffusion layer 3s and a drain diffusion layer 3d are formed between them, and a polysilicon layer 5a (a conductor layer such as doped polysilicon) which is a floating gate is formed on the silicon oxide film (tunnel oxide film) 4. Has been done. Relatively thick thermal oxide films 2a and 2b are formed on the surfaces of these diffusion layers, and an interlayer insulating layer 6 is formed thereon to form a wiring layer (word line) 7. A memory cell is formed by the transistors M _{11a and} M _11b each including a common source diffusion layer 3s and floating diffusion gates adjacent to the drain diffusion layers 3d on both sides thereof. An example of an equivalent circuit diagram of a nonvolatile semiconductor memory device using the memory cell is shown in FIG.
It is shown in (b). W _{1 to} Wn are word lines,
S ₁ is a source line and B ₁ is a bit line, and memory cells including transistors M _11a, M _11b ... _Are arranged in a matrix.

Next, FIG. 14 shows another example of the semiconductor memory device, and shows a cross-sectional view of the main part of the gate portion thereof. As shown in FIG. 14A, the silicon oxide film 4, the polysilicon layer 5a and the silicon nitride film 8 are formed on the semiconductor substrate 1 by using the resist film 9 as an etching mask.
Subsequently, as shown in FIG. 14B, dopant is ion-implanted using the resist film 9 as a mask to form a drain diffusion layer (not shown) and a source diffusion layer 3s. Then, a relatively thick thermal oxide film 2b is formed on the surfaces of the drain diffusion layer and the source diffusion layer 3s by heat treatment, and subsequently, the wiring layer 10 such as a word line is formed. After that, an interlayer insulating layer, a metal wiring layer, a protective film, and the like are applied, wire bonding is performed, and a semiconductor memory device is formed.

[0004]

In the semiconductor memory device as described above, at least one of the unit memory cells has the structure shown in FIG.
A semiconductor memory device including two transistors having a common source diffusion layer as shown in 3 requires an extremely large area as compared with a semiconductor memory device in which a unit memory cell includes one transistor. Therefore, in a semiconductor memory device including this type of memory cell, it is a very important technical subject to improve the degree of integration and increase the reliability without lowering the yield.

In particular, in this type of semiconductor memory device, in order to enhance the insulating properties of the adjacent transistors, the thermal oxide film 2a is formed on the surface of the source diffusion layer 3s and the drain diffusion layer 3d so as to surround the periphery of the floating gate. , 2b are formed. However, in such a manufacturing process, as shown in FIG.
As shown in FIG. 2, the thermal oxide films 2a and 2b are formed, and at the same time, the polysilicon layer 5 to be the floating gate is formed.
There is a drawback that the gate bird's beak B is easily formed under a. That is, if the gate bird's beak B is formed under the polysilicon layer 5a, the gate length is narrowed, which may deteriorate the characteristics of the device.
Therefore, it is necessary to set the gate length of the mask in advance in consideration of the loss, and it is necessary to set the gate length larger than necessary. As a result, there is a drawback that the degree of integration is reduced.

Further, as shown in FIG. 14C, when the thermal oxide film 2b is formed on the surfaces of the drain diffusion layer and the source diffusion layer 3s, at the same time, a very thick sacrificial layer is formed on the sidewall of the polysilicon layer 5a. Sidewall oxide film 2c is formed.
The formation of the side wall oxide film 2c has a drawback that the gate length of the polysilicon layer 5a to be the floating gate is reduced. Therefore, in the conventional method for manufacturing a semiconductor memory device, the mask gate length is set to an unnecessarily large size in consideration of the generation of the bird's beak B and the loss of the gate length due to the formation of the sacrificial sidewall oxide film 2c. It is necessary to set a large value, and as a result, there is a drawback that the integration degree is reduced.

Further, as is clear from FIGS. 13 (a) and 14 (c), the source diffusion layer 3s and the drain diffusion layer 3 are formed.
When the thermal oxide films 2a and 2b formed on the surface of d are formed,
The gate bird's beak B raises the peripheral edge of the polysilicon layer 5a, which may damage the floating gate formed of the polysilicon layer 5a.
The stepped portion becomes prominent. In this state,
If a wiring layer such as a word line is formed so as to be orthogonal to the source diffusion layer 3s and the drain diffusion layer 3d, there is a risk that the wiring layer may be stepped at the step portion, and this may damage the floating gate. Therefore, there is a defect that the reliability of the device is deteriorated and the device life is shortened, and there is a defect that the yield is reduced.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor memory device in which a floating gate can be easily formed without lowering the degree of integration. It is intended. It is another object of the present invention to provide a method for manufacturing a semiconductor memory device in which the electric characteristics of the memory cells are uniform and the element life is long.

[0009]

In order to solve the above problems, a method of manufacturing a semiconductor memory device according to the present invention will be described based on the principle manufacturing process of FIG. A first silicon oxide film is formed on the surface of the semiconductor substrate 1, and a first conductor layer, a first silicon nitride film, and a second silicon oxide film are laminated on the first silicon oxide film. Then, Fig. 1
As shown in (a), the second silicon oxide film and the underlying first silicon nitride film and the like are selectively removed, and the first conductor layer is formed on the first silicon oxide film 4. (Polysilicon layer) 5a, first silicon nitride film 8 and second silicon oxide film 11 are formed into a strip-shaped laminated portion G. As shown in FIG. 1B, a sidewall oxide film 5d is formed on the sidewall of the first conductor layer 5a of the strip-shaped laminated portion G through a thermal oxidation process, and a dopant is ion-implanted to form a drain diffusion layer and a source. The diffusion layer 3s is formed. As shown in FIG. 1C, a spacer / polysilicon layer 7 covering the side wall of the second silicon oxide film 11 of the strip-shaped laminated portion G and the silicon nitride film 8 and the side wall oxide film 5d.
To form. As shown in FIG. 1 (d), after removing the silicon oxide film 11 on the surface layer of the strip-shaped laminated portion G, a thermal oxide film 2b 'is formed on the surfaces of the drain diffusion layer and the source diffusion layer 3s to form a spacer polysilicon. Layer 7 becomes spacer oxide film 7 '. A wiring layer 10 of a second conductor layer made of a polysilicon layer or a polycide layer is formed, and a floating gate is formed through a thermal oxidation process by the self-alignment method using the wiring layer 10 as a mask.

Further, following the above manufacturing process, the drain diffusion layer and the source diffusion layer 3s are formed so as to be substantially orthogonal to each other.
A second conductor layer made of a polysilicon layer or a polycide layer is patterned to form a plurality of parallel wiring layers 10, and the first silicon nitride film and the first silicon nitride film are formed by a self-alignment method using the wiring layers as a mask. Lower first
After removing the conductor layer (polysilicon layer) 5a, the side wall of the first conductor layer immediately below the wiring layer is oxidized through an oxidation step to form a floating gate. Further, following the above manufacturing process, a second conductor layer made of a polysilicon layer, a polycide layer or the like is patterned so as to be substantially orthogonal to the drain diffusion layer and the source diffusion layer 3s, and a plurality of parallel layers are formed. After the wiring layer 10 is formed, the first silicon nitride film and the underlying first conductor layer (polysilicon layer 5a) are etched and thinned by a self-alignment method using the wiring layer as a mask. The first conductor layer is oxidized to form a floating gate. Further, following the above manufacturing process, a second conductor layer made of a polysilicon layer, a polycide layer or the like is patterned so as to be substantially orthogonal to the drain diffusion layer and the source diffusion layer 3s, and a plurality of parallel layers are formed. A wiring layer 10 is formed, and the first silicon nitride film and the underlying first conductor layer (polysilicon layer 5a) are oxidized by a self-alignment method using the wiring layer as a mask to form a floating gate. .

[0011]

According to the method of manufacturing a semiconductor memory device according to the present invention, as described above, a polysilicon layer, a silicon nitride film, and a polysilicon layer are formed on the thermal oxide film formed on the surface of the semiconductor substrate.
A parallel strip-shaped laminated portion made of a silicon oxide film is selectively formed, a sacrificial sidewall oxide film is formed on the sidewall of the polysilicon layer of the first conductor layer of the strip-shaped laminated portion, and the sidewall oxide film is formed. A spacer oxide film is formed so as to cover, and the spacer oxide film suppresses the generation of gate bird's beaks in the next thermal oxidation step to prevent the gate length or the channel length from being reduced. The film flattens the gate portion.

Further, a portion covered with the wiring layer by etching the first conductor layer by a self-alignment method using the wiring layer as a mask or by thermal oxidation of the first conductor layer using the wiring layer as a mask. Since the polysilicon layer is used as a floating gate, an error due to mask alignment does not occur, and the electrical characteristics of the memory cell are uniform. In addition, the polysilicon layer between the elements, which is a strip-shaped laminated portion, is made of a silicon oxide film to enhance the insulating property, and the polysilicon layer is etched to flatten the step portion.

[0013]

(Embodiment 1) An embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIG.
Description will be given based on (a) to FIG. 5 (a) and FIG. 2 (b) to FIG. 5 (b) which are cross-sectional views taken along the line xx ′. Incidentally, the method of manufacturing a semiconductor memory device according to the present invention includes, for example, as shown in FIG. 13A, a memory cell having a basic unit of two transistors having a common source diffusion layer, and At least one of the memory cells has such a structure, and a semiconductor memory device in which at least two such memory cells are provided in series or in parallel to form a unit memory cell is targeted.

First, after the semiconductor substrate is pretreated, a thermal oxide film (silicon oxide film) having a thickness of about 100 Å is formed on the surface of the semiconductor substrate by thermal oxidation, and a field oxide film is selectively formed. Of course, when a CMOS transistor is included, a well forming step is performed. A thickness of about 20 is formed on the thermal oxide film formed on the semiconductor substrate by the CVD method.
A 00Å polysilicon layer is formed. The polysilicon layer is ion-implanted with a dopant such as phosphorus to form a conductive doped polysilicon layer. Alternatively, a material that is previously doped with a dopant such as phosphorus may be deposited by the CVD method.
Furthermore, a silicon nitride film with a thickness of about 100Å is formed, and C
A silicon oxide film having a thickness of about 2000 Å is deposited by the VD method. Thus, the thermal oxide film, the polysilicon layer, the silicon nitride film and the silicon oxide film are laminated on the surface of the semiconductor substrate. A thin silicon oxide film is formed on the surface of the polysilicon layer by a diffusion process.

After that, as shown in FIGS. 2A and 2B, after a resist film is deposited on the surface silicon oxide film, the exposed silicon oxide film is used as a mask and the underlying silicon film. The nitride film and the like are selectively removed, and openings for forming source / drain diffusion layers are formed. In this etching step, the strip-shaped laminated portion G in which the polysilicon layer 5a, the silicon nitride film 8 and the silicon oxide film 11 are sequentially laminated is formed on the thermal oxide film 4. Although not shown, the plurality of strip-shaped laminated portions G are formed in parallel with each other. The thermal oxide film 4 is also etched to some extent in this etching process.

Following the above manufacturing steps, as shown in FIG.
(B) shows a step of forming the sidewall oxide film 5d and the diffusion layer. By heat-treating at a relatively low temperature (about 850 ° C.), the side surface of the polysilicon layer 5a is about 1
A 50 Å sacrificial sidewall oxide film 5d is formed. Further, although the thermal oxide film 4 is somewhat removed in the previous etching process, the thickness of the thermal oxide film 4 is about 10 by this oxidation process.
It becomes 0Å. Subsequently, the thermal oxide film 4 and the polysilicon layer 5
A dopant such as phosphorus is ion-implanted by a self-alignment method using the strip-shaped laminated portion G formed of a, the silicon nitride film 8 and the silicon oxide film 11 as a mask to form the source diffusion layer 3s and the drain diffusion layer. Source diffusion layer 3 _S
Etc. are also used as a wiring layer. Then, FIG.
As shown in (a) and (b), about 150 by the CVD method.
A polysilicon layer is deposited to a thickness of 0Å, after which a spacer polysilicon layer 7 is formed by anisotropic etching. (It is desirable to dope the spacer / polysilicon layer 7 with a dopant such as arsenic or phosphorus.)

As shown in FIGS. 5A and 5B, after the silicon oxide film 11 is removed, a thin oxide film is formed on the surface of the silicon nitride film 8 by thermal oxidation (pyrogenic oxidation), and the drain is formed. A thermal oxide film 2b 'having a thickness of about 2000Å is formed on the surface of the diffusion layer or the source diffusion layer 3s. Further, the spacer / polysilicon layer 7 is oxidized and the silicon oxide film is altered to become a pacer oxide film 7 '. Then, in order to form a word line, a thickness of about 2 is formed by a CVD method.
A conductive layer consisting of a 000 Å polysilicon layer and a tungsten suicide layer having a thickness of about 2000 Å is formed. Further, a polysilicon layer, a silicon nitride film, a silicon oxide film, or the like is deposited if necessary. After that, the conductive layer is
The wiring layer 10 which is patterned by etching and serves as a word line orthogonal to the source / drain diffusion layer is formed. After that, a floating gate is formed by the polysilicon layer 5a by the self-alignment method using the wiring layer 10 as a mask, and then by a normal manufacturing process.
An interlayer insulating layer, a metal wiring layer and a protective film are formed.

(Embodiment 2) Next, another embodiment of the method for manufacturing a semiconductor memory device of the present invention will be described with reference to FIGS. After the spacer / polysilicon layer 7 is formed on the side wall of the strip-shaped laminated portion G as in the above-described embodiment, the spacer / polysilicon layer 7 is transformed into a silicon oxide layer through an oxidation process, and the drain diffusion layer or the source diffusion layer is A thermal oxide film 2b 'is formed on the surface of the layer 3s. Silicon oxide film 1
1 is removed to expose the silicon nitride film 8. continue,
The thickness of about 200 is formed by the CVD method to form the word line.
A conductive layer composed of a 0Å polysilicon layer and a tungsten silicide layer having a thickness of about 2000Å is formed. Similar to the above embodiment, a polysilicon layer, a silicon nitride film, a silicon oxide film, or the like is deposited as needed.

After that, as shown in FIG. 6A, the wiring layer 10 such as a polysilicon layer is patterned. FIG. 6B is a sectional view taken along the line xx ', and the polysilicon layer 5a is left in this manufacturing process. Figure 6
(C) its y-y 'is a cross-sectional view taken along line shows the gate portion G ₁ to the wiring layer 10 is formed. continue,
As shown in FIG. 7A, the polysilicon layer 5a is formed by the self-alignment method using the wiring layer 10 as a mask.
Are removed and a floating gate is formed. Figure 7
7B is a sectional view taken along the line xx ′, in which the polysilicon layer 5a in this portion is removed, and FIG.
(C) is a cross-sectional view taken along the line yy ', in which the polysilicon layer 5a is left as a floating gate by the self-alignment method using the wiring layer 10 as a mask. Then, the side surface of the polysilicon layer 5a is oxidized to form a floating gate. According to the above-described manufacturing process, as shown in the perspective view of FIG. 8, the polysilicon layer 5a is removed by the self-alignment method using the wiring layer 10 as a mask, and the floating gate is formed through the oxidation process. Two transistors having the common diffusion layer 3s and provided with the gate portions G ₁ and G ₂ are formed. After that, the interlayer insulating layer,
A metal wiring layer and the like are formed to form a semiconductor memory device.

(Embodiment 3) Next, another embodiment of the method for manufacturing a semiconductor memory device of the present invention will be described with reference to FIGS. In the third embodiment, after the wiring layer 10 is patterned as shown in the first embodiment, the following manufacturing process is performed. 9B is a sectional view taken along the line xx ′ of FIG. 9A, and FIG. 9B is a sectional view taken along the line yy ′ of FIG. As is clear from this figure, after the wiring layer 10 is formed in the patterning step, the polysilicon layer 5a around the wiring layer 10 is etched to a half thickness by the self-alignment method using the wiring layer 10 as a mask. .

Then, as shown in FIG. 10A and their cross-sectional views of FIG. 10B and FIG. 10C, a comparison is made with the polysilicon layer 5a 'which has been halved in thickness by the oxidation process. A thick thermal oxide film 2d is formed. By forming the relatively thick thermal oxide film 2d in the element isolation region in this manner, a floating gate is formed by the polysilicon layer 5a whose side surface is protected by the thermal oxide film 2d. Since insulation and flattening between elements can be achieved, the degree of integration can be improved and the yield can be improved. Then, an interlayer insulating layer, a metal wiring layer, and a protective film are formed by a normal manufacturing process. In this embodiment, by controlling the thickness of the polysilicon layer 5a exposed between the wiring layers 10, it is possible to control the thickness according to the level difference of the gate portion G ₃ and planarize.

(Embodiment 4) Next, another embodiment of the method for manufacturing a semiconductor memory device of the present invention will be described with reference to FIGS. Through the same manufacturing process as that of the first embodiment, as shown in FIGS. 11A, 11B, and 11C, the wiring layer 10 is patterned and formed, and silicon around the wiring layer 10 is formed. The nitride film 8 is removed. Thereafter, as shown in FIGS. 12A, 12B, and 12C, the polysilicon layer 5a exposed between the wiring layers 10 is not removed, and the insulating properties of adjacent transistors are maintained by a thermal oxidation process. Then, a relatively thick silicon oxide film 2e is formed to form an element isolation region. By this thermal oxidation step, the polysilicon layer 5a under the wiring layer 10 becomes a floating gate.

In the thermal oxidation step, it is desirable to protect the surface of the wiring layer 10 with an oxidation resistant thin film such as a silicon nitride film. When the silicon oxide film 2e is formed in the thermal oxidation step, the diffusion depth of the source / drain diffusion layer tends to be deep. If such a tendency is strong, a lamp annealing step is performed after the ion implantation. RTA (rapi by
It is desirable that the source / drain diffusion layer be a shallow diffusion layer so that it does not become a deeper thermal diffusion layer than necessary by adopting a d thermal annealing) process. In this embodiment, the step portion of the gate portion G ₄ is flattened by forming the spacer oxide film 7'and the silicon oxide film 2e,
It is possible to suppress the occurrence of step breakage of the wiring layer 10 and to form the silicon oxide film 2e between adjacent transistors.
Is formed, the insulating property is maintained.

As described in Embodiments 1 to 4, in the method of manufacturing a semiconductor memory device of the present invention, the sidewall oxide film is formed and the spacer oxide film is formed in order to suppress the generation of gate bird's beak. Has been formed. The spacer oxide film of the embodiment is formed by performing silicon oxidation by thermal oxidation of the polysilicon layer, but the present invention is not limited to this embodiment, and other semiconductor materials such as a silicon nitride film may be used. That is clear. Further, the floating gate is not limited to the doped polysilicon layer,
Obviously, it may be a conductor film having another conductivity. Further, the formation of the sidewall oxide film and the spacer oxide film suppresses the generation of gate bird's beaks,
Since the polysilicon layer of the gate part is not easily affected by it,
The distance between the gate electrode and the source / drain diffusion layer below it,
That is, the length in the channel direction that contributes to the tunnel current is
Conventionally, it was about 0.1 μm, but about 0.2 μm
It is possible to secure a channel length of about m. Of course, the film thickness of the gate oxide film can be formed extremely stably in the region where the tunnel current flows.

In particular, it is extremely effective as a method for manufacturing a semiconductor memory device in which unit memory cells share a source diffusion layer and gate electrodes are formed adjacent to each other. By using the manufacturing method, the floating gate is not damaged by the generation of the gate bird's beak, and the variation in the electrical characteristics of the memory cell can be reduced. Therefore, according to the method of manufacturing a semiconductor memory device of the present invention, since the variation due to the mask alignment does not occur, the yield can be improved as compared with the conventional method, and the number of times data can be rewritten can be more than doubled. You can

[0026]

As described above, according to the present invention, the sidewall oxide film is formed on the side wall of the polysilicon layer to be the floating gate, and the spacer oxide film is provided so as to cover the sidewall oxide film. Therefore, even if a relatively thick thermal oxide film is formed on the surface of the source / drain diffusion layer, this spacer oxide film prevents the bird's beak from occurring in the lower layer of the gate portion. There is an advantage that the channel length can be formed and the gate length and the channel length can be set to the required minimum dimension, and therefore, the effect of increasing the degree of integration is obtained. In addition, the spacer oxide film used to control the generation of the gate bird's beak is used to insulate the floating gate and also to reduce the step difference in the gate portion, so that the adhesion of the wiring layer such as the word line is improved. There is an advantage to get. Further, by a self-alignment method using a wiring layer such as a word line as a mask, the silicon nitride film or the polysilicon layer located in the element isolation region can be etched, or the polysilicon layer can be thermally oxidized. Since the floating gate is formed by the manufacturing process, there are advantages that errors due to these mask alignments do not occur, the degree of integration is not reduced, and the yield is improved.

Further in accordance with the present invention, a flash EPR
If a non-volatile semiconductor memory device such as an OM is formed based on this manufacturing method, the floating gate is not damaged by the generation of a gate bird's beak. Also improved,
The device life can be extended, and since the gate length or the channel length is set by forming the first gate portion, the variation in the electrical characteristics of the memory cell can be extremely reduced. Therefore, there is an advantage that the yield of the nonvolatile semiconductor memory device can be further improved.

[Brief description of drawings]

1A to 1D are cross-sectional views showing a principle manufacturing process in a method of manufacturing a semiconductor memory device according to the present invention.

2A is a plan view showing a manufacturing process of the first embodiment of the present invention, and FIG. 2B is a sectional view taken along the line xx ′.

3A is a plan view showing a manufacturing process subsequent to FIG. 2, and FIG. 3B is a sectional view taken along line xx ′ thereof.

4A is a plan view showing the manufacturing process following FIG. 3, and FIG. 4B is a cross-sectional view taken along the line xx ′.

5A is a plan view showing a manufacturing process subsequent to FIG. 4, and FIG. 5B is a sectional view taken along line xx ′ thereof.

6A is a plan view showing a manufacturing process of a second embodiment of the present invention, FIG. 6B is a sectional view taken along line xx ′ of FIG.
(C) is a sectional view taken along the line yy '.

7A is a plan view showing a manufacturing process following FIG. 6, FIG. 7B is a sectional view taken along line xx ′, and FIG. 7C is a view taken along line yy ′. FIG.

FIG. 8 is a perspective view of a semiconductor memory device according to a second embodiment.

9A is a plan view showing a manufacturing process of a third embodiment of the present invention, FIG. 9B is a sectional view taken along line xx ′ of FIG.
It is sectional drawing which followed the yy 'line of (c).

10A is a plan view showing a manufacturing process subsequent to FIG. 9, FIG. 10B is a sectional view taken along line xx ′, and FIG. 10C is taken along line yy ′. FIG.

11A is a plan view showing a manufacturing process of a fourth embodiment of the present invention, FIG. 11B is a sectional view taken along line xx ′ of FIG.
It is sectional drawing which followed the yy 'line of (c).

12A is a plan view showing a manufacturing process subsequent to FIG. 11, FIG. 12B is a sectional view taken along line xx ′ of FIG.
Is a sectional view taken along the line yy '.

13A is a sectional view showing an example of a conventional method for manufacturing a semiconductor memory device, and FIG. 13B is an equivalent circuit diagram thereof.

14A to 14C are cross-sectional views showing an example of a conventional method for manufacturing a semiconductor memory device.

[Explanation of symbols]

G band-shaped laminated part G _{1 to} G ₄ gate part 1 semiconductor substrate 2a, 2b thermal oxide film 2b′2d thermal oxide film 2e silicon oxide film 3s source diffusion layer 3d drain diffusion layer 4, 4 ′ thermal oxide film (silicon oxide film) 5a, 5a 'Polysilicon layer (doped polysilicon layer) 5d Sidewall oxide film 7 Space polysilicon layer 7'Space oxide film 8 Silicon nitride film 10 Wiring layer 11 Silicon oxide film

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor memory device, wherein a relatively thick thermal oxide film is formed on the surface of a source / drain diffusion layer, wherein at least a first silicon oxide film and a first conductive film are formed on a semiconductor substrate. Stacking a body layer, a first silicon nitride film, and a second silicon oxide film, and selectively removing the second silicon oxide film and the underlying first silicon nitride film Etching step of forming parallel strip-shaped laminated portions selectively left by exposing the silicon oxide film of No. 1 or the surface of the semiconductor substrate, and sidewall oxidation on the side wall of the first conductor layer of the strip-shaped laminated portions. A step of forming a film, a step of ion-implanting a dopant to form a source / drain diffusion layer by a self-alignment method using the strip-shaped laminated portion as a mask, and a step of the strip-shaped laminated portion. A spacer forming step of attaching a silicon nitride film or a polysilicon film to the portion, and after the spacer forming step, the second silicon oxide film on the surface layer of the strip-shaped laminated portion is removed to expose the first silicon nitride film. Then, an oxidation step of partially growing a thermal oxide film on the surface of the source / drain diffusion layer by thermal oxidation, a first silicon nitride film of the strip-shaped laminated portion and a first conductor layer thereunder are formed. And a step of forming a floating gate through a patterning and oxidation step, and a method of manufacturing a semiconductor memory device. 2. A method of manufacturing a semiconductor memory device, wherein a relatively thick thermal oxide film is partially formed on the surface of a source / drain diffusion layer, wherein at least a first silicon oxide film and a first silicon oxide film are formed on a semiconductor substrate. A step of stacking and forming a first conductor layer, a first silicon nitride film and a second silicon oxide film; and selectively removing the second silicon oxide film and the underlying first silicon nitride film and the like. An etching step of forming parallel strip-shaped laminated portions selectively left by exposing the surface of the first silicon oxide film or the surface of the semiconductor substrate, and a sidewall of the first conductor layer of the strip-shaped laminated portions. An oxidation step of forming a sidewall oxide film; a diffusion step of ion-implanting a dopant to form a source / drain diffusion layer by a self-alignment method using the strip-shaped laminated portion as a mask; A spacer forming step of providing a silicon nitride film or a polysilicon film on the stepped portion of the laminated portion, and after the spacer forming step, the second silicon oxide film on the surface layer of the strip-shaped laminated portion is removed to remove the first silicon. An oxidization step of exposing the nitride film and partially growing a thermal oxide film on the surface of the source / drain diffusion layer by thermal oxidation, and patterning a second conductor layer to the source / drain diffusion layer. Forming a plurality of parallel wiring layers that are substantially orthogonal to each other, and removing the first silicon nitride film of the strip-shaped laminated portion and the first conductor layer therebelow by a self-alignment method using the wiring layers as a mask. And a step of forming a floating gate through an oxidation step, and a method of manufacturing a semiconductor memory device. 3. A method of manufacturing a semiconductor memory device in which a relatively thick thermal oxide film is partially formed on the surface of a source / drain diffusion layer, wherein at least a first silicon oxide film and a first silicon oxide film are formed on a semiconductor substrate. A step of stacking and forming a first conductor layer, a first silicon nitride film and a second silicon oxide film; and selectively removing the second silicon oxide film and the underlying first silicon nitride film and the like. An etching step of exposing the first silicon oxide film or the surface of the semiconductor substrate to form a parallel strip laminated portion selectively left, and a step portion of the first conductor layer of the strip laminated portion. An oxidation step of forming a sidewall oxide film on the substrate, a diffusion step of ion-implanting a dopant to form the source / drain diffusion layer by a self-alignment method using the strip-shaped laminated portion as a mask, A spacer forming step of providing a silicon nitride film or a polysilicon film on the step portion of the layer portion, and after the spacer forming step, the second silicon oxide film on the surface layer of the strip-shaped laminated portion is removed to remove the first silicon. After exposing the nitride film, an oxidation step of partially growing a thermal oxide film on the surface of the source / drain diffusion layer by thermal oxidation, and patterning a second conductor layer to form the source / drain diffusion layer. Forming a plurality of parallel wiring layers that are substantially orthogonal to each other, and removing the first silicon nitride film of the strip-shaped laminated portion by a self-alignment method using the wiring layer of the second conductor layer as a mask An etching step for thinning the underlying first conductor layer, and a step for oxidizing the first conductor layer in the strip-shaped laminated portion to form a floating gate. Method for manufacturing semiconductor memory device. 4. A method of manufacturing a semiconductor memory device, wherein a relatively thick thermal oxide film is partially formed on a surface of a source / drain diffusion layer, wherein at least a first silicon oxide film and a first silicon oxide film are formed on a semiconductor substrate. A step of stacking and forming a first conductor layer, a first silicon nitride film and a second silicon oxide film; and selectively removing the second silicon oxide film and the underlying first silicon nitride film and the like. An etching step of exposing the first silicon oxide film or the surface of the semiconductor substrate to form a parallel strip laminated portion selectively left, and a step portion of the first conductor layer of the strip laminated portion. An oxidation step of forming a sidewall oxide film on the substrate, a diffusion step of ion-implanting a dopant to form the source / drain diffusion layer by a self-alignment method using the strip-shaped laminated portion as a mask, A spacer forming step of providing a silicon nitride film or a polysilicon film on the step portion of the layer portion, and after the spacer forming step, the second silicon oxide film on the surface layer of the strip-shaped laminated portion is removed to remove the first silicon. After exposing the nitride film, an oxidation step of partially growing a thermal oxide film on the surface of the source / drain diffusion layer by thermal oxidation, and patterning a second conductor layer to form the source / drain diffusion layer. A step of forming a plurality of parallel wiring layers that are substantially orthogonal to each other; and using the wiring layer of the second conductor layer as a mask to remove the first silicon nitride film of the strip-shaped laminated portion, 1. A method of manufacturing a semiconductor memory device, comprising the step of oxidizing the conductor layer 1 to form a floating gate.