JPH0737398A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by cutting a fuse of a fuse selector for selecting a spare word line with a specific address, and activating a spare decoder in synchronization with a clock signal. CONSTITUTION:When a memory cell Mik in which a defect occurs in a memory cell array 1 is replaced with a redundancy memory cell MSjk, a fuse of a fuse selector 12 is out in order to select a spare word line WLSj by a specific address. Thus, a spare decoder 5 is activated in synchronization with a clock signal CLK by a spare decoder activating circuit 11, driving capacity of the line WLSj is enhanced by a word line buffer 13, and supplied to the array 1. Thus, the signal CLK is regulated to control activating time of the decoder 5, thereby reducing a current flowing to the decoder 5. In this manner, an unnecessary current flowing to a redundant memory is suppressed to reduce power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a semiconductor memory, and more particularly to a semiconductor integrated circuit having a large-capacity semiconductor memory or a semiconductor memory mounted together on the same chip. As a control signal of the spare decode circuit for decoding the spare word line, by activating the spare decode circuit by using a clock signal and / or a signal from a circuit means for detecting the use of the redundant memory cell, The present invention relates to a semiconductor integrated circuit in which unnecessary current flowing in a redundant memory cell is suppressed to reduce power consumption.

[0002]

2. Description of the Related Art In recent years, the capacity of a semiconductor memory mounted on a semiconductor integrated circuit has been increased, and a technique of a redundant circuit for replacing a defective bit with a redundant memory cell has been indispensable. Further, the capacity of a semiconductor memory mounted on a chip together with a logic circuit has been increasing, and redundant circuit technology has become important as one of integrated circuit technologies. Further, there is a strong demand for lower power consumption of semiconductor memories, and a technique for reducing current consumption as much as possible is important.

FIG. 8 shows an example of the configuration of a spare decode circuit in a conventional semiconductor integrated circuit having redundant memory cells.

In FIG. 1, the conventional spare decode circuit 101 comprises a spare decode activation circuit 111, a word line buffer circuit 113, and a fuse selection circuit 112.
Only the chip activation signal CE is supplied as a control signal.

Spare decode circuit 10 having such a configuration
In No. 1, when the chip is activated, the spare decoding circuit 101 is activated by the chip activation signal CE, and a steady current always flows through the spare decoding circuit 101. Further, even when the redundant memory cell does not have to be used, a steady current is passed through the redundant memory cell, which leads to an increase in current consumption of the entire semiconductor integrated circuit.

[0006]

As described above, in the conventional semiconductor integrated circuit having the redundant memory cell, the semiconductor integrated circuit chip in the spare decode circuit for decoding the spare word line of the redundant memory cell is When is activated, the spare decode circuit is always activated by the chip activation signal, and a steady current is caused to flow to the redundant memory cell, which increases the current consumption of the entire semiconductor integrated circuit. there were.

The present invention solves the above problems,
The purpose is to use a clock signal as a control signal of a spare decoding circuit for decoding a spare word line of a redundant memory cell and / or a signal from a circuit means for detecting the use of the redundant memory cell. An object of the present invention is to provide a semiconductor integrated circuit in which an unnecessary current flowing in a redundant memory cell is suppressed by activating a circuit to reduce power consumption.

[0008]

In order to solve the above-mentioned problems, the first feature of the present invention is, as shown in FIG. 1, redundant memory cells MSjk (j = 1 to m, k = 1 to p; m). , P is an arbitrary positive integer), and the redundant memory cell MSjk by decoding the address signal Add.
A spare decode circuit 5 for selecting a spare word line WLSj for
A spare decoder activation circuit 11 that activates the spare decode circuit 5 in synchronization with the clock signal CLK, and a fuse selection circuit 12 that selects a predetermined spare word line WLSj for a specific address by cutting a fuse. It is to have.

A second feature of the present invention is that, in the semiconductor integrated circuit according to claim 1, as shown in FIG. 7, the spare decode circuit 5 includes a specific spare word line WLS.
A second fuse S that is blown to indicate that j is used
The spare decoder activation circuit 11 includes a second fuse circuit 14 including Fj and detecting a disconnection of the second fuse SFj and outputting a use detection signal SIGN. The spare decode circuit 5 is activated based on the use detection signal SIGN.

A third feature of the present invention is that in the semiconductor integrated circuit according to claim 1 or 2, the clock signal CLK is a system clock SCLK as shown in FIG. 2 (1). .

Further, a fourth feature of the present invention is that in the semiconductor integrated circuit according to claim 1 or 2, as shown in FIG. 2B, the spare decode circuit 5 has a value of the address signal Addin. An address change detection circuit 8 for detecting a change is provided, and the clock signal CLK is
This is the output ACLK of the address change detection circuit 14.

[0012]

In the semiconductor integrated circuit of the first feature of the present invention, as shown in FIG. 1, the spare decode circuit 5 includes a spare decoder activation circuit 11, a fuse selection circuit 12, and a word for each spare word line SLj. The line buffer circuit 13 is provided with a block 6j. It is also conceivable that the spare decoder activation circuit 11 is common to all the blocks 61 to 6m and the block 6j is composed of the fuse selection circuit 12 and the word line buffer circuit 13.

In the memory cell array 1, when replacing a defective memory cell with a redundant memory cell, the fuse of the fuse selection circuit 12 is cut so as to select the spare word line WSLj at a specific address, and the spare decoder is activated. The memory decoding circuit 11 activates the spare decode circuit 5 (signal line 51) in synchronization with the clock signal CLK, and further the word line buffer circuit 13 enhances the drive capability of the spare word line WSLj to increase the memory cell array 1
Is being supplied to.

As described above, the activation time of spare decode circuit 5 can be controlled by adjusting clock signal CLK, and the current flowing through spare decode circuit 5 can be reduced. As a result, redundant memory cells can be obtained. A semiconductor integrated circuit with reduced power consumption can be realized by suppressing unnecessary current flowing in the circuit.

Further, in the semiconductor integrated circuit of the second feature of the present invention, as shown in FIG. 7, the spare decode circuit 5 is formed by adding the second fuse circuit 14 to the semiconductor integrated circuit of the first feature. .

When a specific spare word line WLSj is used, the second fuse SFj is blown, and the second fuse circuit 14 detects that the second fuse SFj has been blown and outputs a use detection signal SIGN. Then, the spare decoder activation circuit 11 activates the spare decoding circuit 5 based on the use detection signal SIGN in synchronization with the clock signal CLK.

Thus, when the redundant memory is used, this is detected and the activation time of the spare decoding circuit 5 is controlled by adjusting the clock signal CLK, as in the semiconductor integrated circuit of the first feature. Spare decode circuit 5
The current flowing through can be reduced.

Further, in the semiconductor integrated circuit of the third feature of the present invention, as shown in FIG.
Is generated based on the system clock SCLK, and the activation time of the spare decode circuit 5 is controlled by adjusting the clock signal CLK to reduce the current flowing through the spare decode circuit 5.

In the case of the synchronous memory, since there is a clock signal (SysCLK) input from the outside, the spare decode circuit 5 can be activated for a required time by using this clock signal to reduce the flowing current. it can.

Further, in the semiconductor integrated circuit of the fourth feature of the present invention, as shown in FIG.
Is provided with an address change detection circuit 8 for detecting that the value of the address signal Addin has changed.
By using LK as the output ACLK from the address change detection circuit 14, the activation time of the spare decode circuit 5 is controlled by adjusting the clock signal ACLK, and the current flowing through the spare decode circuit 5 is reduced.

In the case of the asynchronous memory, if the means 8 for detecting the change of the address and generating the control clock pulse is provided inside, the current can be reduced as in the synchronous memory.

As described above, according to the semiconductor integrated circuit having the redundant memory cell of the present invention, the spare decode circuit 5 is used.
It is possible to reduce the current flowing in the. Further, even in the case of a cache memory mounted on a chip such as a microprocessor, a configuration having a redundant circuit has come to be adopted, and the field of such a memory configuration is also adopted. The invention is effective.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a semiconductor integrated circuit according to the first embodiment of the present invention.

As shown in the figure, the semiconductor integrated circuit of this embodiment has a memory cell array 1 having a redundant memory cell region 1s, an address decoder 3, and word lines WLi.
A decode circuit including a word line buffer circuit 4i for each (i = 1 to n; n is an arbitrary positive integer), and a spare decode for decoding the address signal Add to select the spare word line WLSj for the redundant memory cell MSjk. It is composed of a circuit 5. The memory of this embodiment is assumed to be a synchronous memory.

In the semiconductor integrated circuit of this embodiment, a spare decode circuit 5 is provided for each spare word line SLj, and a block 6j including a spare decoder activation circuit 11, a fuse selection circuit 12, and a word line buffer circuit 13. Are configured. It is also conceivable that the spare decoder activation circuit 11 is common to all the blocks 61 to 6m and the block 6j is composed of the fuse selection circuit 12 and the word line buffer circuit 13.

Spare decoder activation circuit 11 activates spare decoding circuit 5 in synchronization with clock signal CLK when chip activation signal CE is active. In addition, the fuse selection circuit 12 selects a predetermined spare word line WLSj for a specific address by cutting the fuse.

FIG. 2A is a block diagram of a buffer circuit for the system clock SysCLK input from the outside, which is provided in the semiconductor integrated circuit in the case of the synchronous memory. In the buffer circuit 7, the system clock Sy
A clock signal SCLK is generated as the clock signal CLK to be supplied to the spare decoder activation circuit 11 by adjusting the sCLK based on the necessary delay.

FIG. 3 is a circuit configuration diagram showing a detailed circuit configuration of the spare decoder activation circuit 11 of this embodiment. The clock signal CLK controls the time for activating the PMOSFET (Q1) to suppress the steady current flowing from the PMOSFET (Q1) to the fuse selection circuit 12 (signal line 51).

Further, circuit examples of the word line buffer circuit 13 are shown in FIGS. 4 (1) and 4 (2). Fuse selection circuit 12
Since the driving force of the signal operated by the control of 1 is small, it is necessary to buffer the signal (see FIG. 4 (1)). Further, the spare decoder activation circuit 11 receives the clock signal CLK (S
CLK), the output 51 of the spare decoder activation circuit 11 must be fixed because it is in a high impedance state when it is not activated. Therefore, NOT
The configuration shown in FIG. 4B is obtained by adding the PMOSFET (Q3) to the gate GN2.

Furthermore, a configuration example of the fuse selection circuit 2 is shown in FIG.
It shows in (3). When the fuse Fq (q = 0 to r) at the position corresponding to the decode line that needs to be replaced is cut,
When accessing the decode line that needs to be replaced, there is no current path drawn by the power supply Vss, and the spare word line can be activated instead.

In the present embodiment, when replacing a defective memory cell in the memory cell array 1 with a redundant memory cell, a spare word line WSL at a specific address is used.
The fuse of the fuse selection circuit 12 is blown so as to select j, and the spare decoder activation circuit 11 outputs the clock signal SCL when the chip activation signal CE is active.
The spare decode circuit 5 (signal line 51) is activated in synchronization with K, and the word line buffer circuit 13 further enhances the drive capability of the spare word line WSLj and supplies it to the memory cell array 1.

As described above, in the semiconductor integrated circuit of this embodiment, the activation time of the spare decode circuit 5 can be controlled by adjusting the clock signal SCLK, and the current flowing through the spare decode circuit 5 can be reduced. As a result, it is possible to realize a semiconductor integrated circuit in which unnecessary current flowing in the redundant memory cell is suppressed and power consumption is reduced.

(Second Embodiment) In the semiconductor integrated circuit of the second embodiment, it is assumed that the memory is an asynchronous memory. FIG. 2B shows a block diagram of the clock signal generating means 8 in the semiconductor integrated circuit of the second embodiment. Other components are the same as those of the semiconductor integrated circuit of the first embodiment.

In the present embodiment, in the case of an asynchronous memory, the address change detection circuit 8 provided in the semiconductor integrated circuit for detecting a change in the value of the address signal Addin input from the outside is used as a clock. It is used as a means for generating the signal CLK. The address change detection circuit 8 is
Based on the external address signal Addin, the clock signal AC is used as the clock signal CLK to be supplied to the spare decoder activation circuit 11 after adjustment such as giving a necessary delay.
Generate LK.

That is, the clock signal CLK is used as the output ACLK from the address change detection circuit 14, the activation time of the spare decode circuit 5 is controlled by adjusting the clock signal ACLK, and the current flowing through the spare decode circuit 5 is reduced. .

(Third Embodiment) In the semiconductor integrated circuit of the third embodiment, a large capacity memory is assumed. In a large-capacity memory, the memory cell array 1 is usually divided into several memory blocks for memory access management.

In the semiconductor integrated circuit of this embodiment, for each memory block MBj, as in the first embodiment, a spare decoder activation circuit 11, a fuse selection circuit 12, and a word line buffer circuit 13 are provided. The block 6j is provided.

FIG. 5 is a circuit configuration diagram showing a detailed circuit configuration of the spare decoder activation circuit 11 of this embodiment. The control signal supplied to spare decoder activation circuit 11 includes clock signal CLK and chip activation signal CE, as well as signal block selection signal BS indicating that the block 6j is selected.

That is, when the block selection signal BS is active and the chip activation signal CE is active,
The spare decode circuit 5 (signal line 51) is activated in synchronization with the clock signal SCLK or ACLK, and the word line buffer circuit 13 further enhances the drive capability of the spare word line WSLj and supplies it to the memory cell array 1.

As a result, the same effects as those of the first and second embodiments can be obtained even for a large capacity memory divided into several memory blocks.

(Fourth Embodiment) FIG. 6 shows a block diagram of a spare decode circuit in a semiconductor integrated circuit according to a fourth embodiment of the present invention. FIG. 7 is a circuit diagram showing details of the spare decode circuit of the fourth embodiment.

As shown in FIGS. 6 and 7, in the semiconductor integrated circuit of this embodiment, the spare decode circuit 5 includes the second fuse circuit 14, the spare decoder activation circuit 11, and the fuse for each spare word line SLj. A block 6j including a selection circuit 12 and a word line buffer circuit 13 is provided and configured.

Similar to the first embodiment, the spare decoder activation circuit 11 activates the spare decoding circuit 5 in synchronization with the clock signal CLK, and the fuse selection circuit 12 is activated.
Disconnects the fuse to select a predetermined spare word line WLSj for a specific address.

The second fuse circuit 14 has a NOT gate GN3 for receiving the inverted signal CE # of the chip activation signal,
A second fuse SFj, which is connected between the NOT gate GN3 and the power supply Vss and cut to indicate that the specific spare word line WLSj is used, is provided when the specific spare word line WLSj is used. The second fuse (signature fuse) SFj is blown. If the second fuse SFj is cut off, there is no current path drawn by the power supply Vss, and the use detection signal SIGN which is an output becomes active.

Spare decoder activation circuit 11 activates spare decode circuit 5 in synchronization with clock signal CLK when use detection signal SIGN is active. Further, the fuse selection circuit 12 selects a predetermined spare word line WLSj for a specific address by cutting the fuse, and further, the word line buffer circuit 1
3, the drive capability of the spare word line WSLj is increased and the spare word line WSLj is supplied to the memory cell array 1.

As described above, in the semiconductor integrated circuit of the present embodiment, when the specific spare word line WLSj is used, the second fuse SFj is cut off, and based on the use detection signal SIGN in synchronization with the clock signal CLK. Since the spare decode circuit 5 is activated, the current flowing through the spare decode circuit 5 can be reduced.

[0048]

As described above, according to the present invention, when replacing a defective memory cell in a memory cell array with a redundant memory cell, a fuse of a fuse selection circuit is selected so that a spare word line is selected at a specific address. Therefore, the spare decoder activation circuit synchronizes with the clock signal to activate the spare decoding circuit. Therefore, the activation time of the spare decoding circuit can be controlled by adjusting the clock signal. The current flowing through the spare decode circuit can be reduced, and as a result, an unnecessary current flowing through the redundant memory cell can be suppressed to provide a semiconductor integrated circuit with reduced power consumption.

Further, according to the present invention, when the specific spare word line is used, the second fuse is cut off and the second fuse is cut off.
The fuse circuit detects that the second fuse has been blown and outputs a usage detection signal, and the spare decoder activation circuit activates the spare decoding circuit based on the usage detection signal in synchronization with the clock signal. Therefore, when the redundant memory is used, this can be detected and the activation time of the spare decoding circuit can be controlled by adjusting the clock signal to reduce the current flowing through the spare decoding circuit.

Further, in the case of a synchronous memory or the like, since there is a system clock from the outside, the spare decode circuit is activated for the necessary time as the clock signal, so that the current flowing through the spare decode circuit is reduced. be able to.

Further, in the case of an asynchronous memory or the like, the spare decode circuit is provided with an address change detection circuit for detecting a change in the value of the address signal, and the output of the address change detection circuit is used as a clock signal for the spare decode circuit. By controlling the activation time of the circuit, the current flowing through the spare decoding circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a clock signal generating means in a spare decode circuit of each embodiment of the present invention, FIG. 2 (1) shows a case of generating from a system clock (first embodiment),
FIG. 2B is a configuration diagram in the case where a change in the address value is detected and generated (second embodiment).

FIG. 3 is a circuit configuration diagram of a spare decoding circuit according to a first embodiment of the present invention.

FIG. 4 is a detailed circuit diagram of components in the spare decoding circuit according to each embodiment of the present invention, and FIGS.
Is a word line buffer circuit, and FIG. 4C is a circuit diagram of a fuse selection circuit.

FIG. 5 is a circuit configuration diagram of a spare decoding circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a spare decoding circuit in a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a spare decoding circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a spare decode circuit in a semiconductor integrated circuit including a conventional redundant memory cell.

[Explanation of symbols]

1 Memory Cell Array 1S Redundant Memory Cell Region Mik (i = 1 to n) Memory Cell MSjk (j = 1 to m) Redundant Memory Cell 2 Word Line Decode Circuit 3 Address Decoder 4i Word Line Buffer Circuit 5 Spare Decode Circuit 6j Spare Decode Circuit block 7 Buffer circuit 8 Address change detection circuit 11 Spare decoder activation circuit 12 Fuse selection circuit 13 Word line buffer circuit 14 Second fuse circuit Add, Addin, A0 to Ar Address signal CLK Clock signal ACLK, SCLK Clock signal SysCLK system Clock CE Chip activation signal CE # Inversion signal of chip activation signal CE BLk, BLk # Bit line WLi Word line WLSj Spare word line BS block selection signal 51 Spare decoder activation time Output SIGN using detection signals Q1~Q3, Q40 ~Q4r, Q5~Q8 MOSFE
T GNA1 NAND gate GN1 to GN3 NOT gate F0 to Fr First fuse SFj Second fuse (signature fuse) Vcc, Vss Power supply 101 Spare decode circuit 111 Spare decode activation circuit 112 Fuse circuit 113 Word line buffer circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsukasa Shiratori 25, Kawasaki-ku, Kawasaki-shi, Kanagawa Honcho, Honcho, 1

Claims (4)

[Claims] 1. A memory cell array having redundant memory cells, and a spare decoding circuit for decoding an address signal to select a spare word line for the redundant memory cell, wherein the spare decoding circuit is synchronized with a clock signal. And a spare decoder activation circuit for activating the spare decode circuit and a fuse selection circuit for selecting a predetermined spare word line for a specific address by cutting a fuse. circuit. 2. The spare decode circuit includes a second fuse that is cut to indicate that a specific spare word line is used, and a use detection signal is detected by detecting that the second fuse has been cut. 2. The second fuse circuit for outputting the above, wherein the spare decoder activation circuit activates the spare decoding circuit based on the use detection signal in synchronization with a clock signal. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the clock signal is a system clock. 4. The spare decode circuit has an address change detection circuit for detecting a change in the value of the address signal, and the clock signal is an output of the address change detection circuit. The semiconductor integrated circuit according to claim 1.