JPH0736570A - Integrated circuit chip mounting structure - Google Patents

Abstract

PURPOSE:To provide an integrated circuit chip mounting structure in which plural instruction processors can be connected to a system controller without deteriorating the performance of a computer system, or sacrificing the maintenance or reliability of the system. CONSTITUTION:In an integrated circuit chip mounting structure in a parallel computer equipped with a system controller and plural instruction processors, an integrated circuit chip group 4 constituting a system controller 16 is mounted on a main substrate 1, integrated circuit chip group 3 constituting each instruction processor 15a-15d is mounted on each of plural slave substrates 2, and the instruction processor is constituted of one slave substrate. Then, the plural slave substrates 2 on which the instruction processors are constituted are mounted on the main substrate, and the parallel computer is constituted on one main substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit chip mounting structure for constructing an electronic computer, and more particularly to an integrated circuit chip mounting suitable for mounting a parallel type large-scale electronic computer having a plurality of instruction processors. It is about structure.

[0002]

2. Description of the Related Art In recent electronic computers, in order to improve processing performance, a so-called parallel computer configuration is widely used in which a plurality of instruction processors are connected to one system controller and each instruction processor cooperates to perform information processing. Has been adopted. In this parallel computer system, how to perform signal transmission between the system controller and the instruction processor at high speed and at low cost is a key to improve the performance of the computer system. As shown in the block diagram of FIG. 11, the conventional multiprocessor type large-scale parallel computer has instruction processors 15a to 15d, a system controller 16, and a main memory 1.
7 and its mounting structure is as shown in FIG. ◆ That is, the instruction processors 15a to 1
5d and the system controller 16 are composed of several tens to several hundreds of integrated circuit chip groups 3 and 4 mounted on a plurality of sub boards 21 and 22 which are usually ceramic module boards, and each of the instruction processors 15a to 15a. The signal from 15d is connected to the system controller 16 via the cable connector 5 and the cable 6. In addition, the main storage device 1
7 is also connected to the system controller 16 via the cable connector 5 and the cable 6. On the other hand, in small computer devices such as microprocessors and workstations, each instruction processor and system control device are connected by a bus, and signals are transmitted in a time division manner between these devices.

[0003]

In the conventional large-scale parallel computer, the signals from each instruction processor are directly connected to the system controller without passing through a bus or the like, which allows the system controller for a plurality of instruction processors to operate. Responsiveness is enhanced. Since one or a plurality of instruction processors are connected to the system control device, the number of signal input / output terminals obtained by multiplying the number of input / output signals of one instruction processor by the number of connected instruction processors is required. In a typical example of a conventional large-scale parallel computer, the number of input / output signals required for one instruction processor, that is, the number of logic signals is about 1000. Therefore, if eight instruction processors are connected to one system controller, the system controller requires about 8000 signal input / output terminals. ◆ In addition, in order to operate normally as a computer system, in addition to the system controller and instruction processor,
Since the main storage device and the input / output control device are required, the system control device also needs signal terminals for exchanging signals with these devices, and it is necessary to handle a total of about 10,000 signals. ◆ Looking at this in the conventional example of FIG. 6,
In the instruction processors 15a to 15d, the cable connector 5
However, the system control device 16 requires five sets of cable connectors, and the occupied area of the device is increased accordingly. Here, considering the situation that the integrated circuit chip is highly integrated and the instruction processor can be realized with only one conventional sub-board, the above-mentioned problem becomes more remarkable. This situation is shown in the block diagram of FIG. 12 and FIG. In FIG. 7, due to the high integration of the integrated circuit chip 3, each of the instruction processors 15a to 15d is realized by one sub-board 2, and its mounting area can be reduced. However, the system controller 16 determines that the required number of integrated circuit chips 4 is equal to the instruction processors 15a to 15a.
Although it is almost equal to d, taking out the input / output pins from the back surface of the slave substrate 23 becomes a bottleneck, and the extra huge slave substrate 23 is required. That is, since the required number of integrated circuit chips is almost the same in the instruction processors 15a to 15d and the system control device 16, if the same mounting system can be applied, it is very efficient in terms of manufacturing cost and workability. Nevertheless, in reality, since the numbers of input and output signals of both are significantly different, a special mounting system is required as a system control device.

On the other hand, in the field of small computers such as microprocessors and workstations, signals are transmitted in a time division manner using a bus for connection between a system control unit, an instruction processor, a main storage unit, an input / output control unit and the like. This prevents an increase in the number of input / output signals of the system control device and thus the number of input / output signal pins. When price is more important than performance, such as microprocessors and workstations, time-division transmission using such a bus is extremely efficient for reducing the pin count of the system controller. It's a good way. ◆ However, in the case of high performance by transmitting signals at the maximum speed that the mounting system can tolerate, like a large parallel computer, the bus configuration causes performance degradation and is a bottleneck for improving overall system performance. Become.

An object of the present invention is to provide an integrated circuit chip capable of connecting a large number of instruction processors to a system controller without degrading the performance of the computer system and without sacrificing the maintainability and reliability of the system. It is to provide a mounting structure and realize a computer device characterized by the mounting structure.

[0006]

To achieve the above object, in mounting an integrated circuit chip of a parallel computer having a system controller and a plurality of instruction processors, an integrated circuit chip group constituting the system controller on a main board. A plurality of slave boards, each of which is equipped with an integrated circuit chip group that constitutes each instruction processor, and one slave board constitutes an instruction processor. The parallel computer is mounted on a board so that the parallel computer is constructed on one main board. ◆ Also, I / O pins for connecting the main board and the sub board are provided on the lower surface of the sub board, and the pitch of the through holes in the main board is smaller than the pitch of the I / O pins provided on the bottom surface of the sub board. I am trying to become. ◆ In addition, an integrated circuit chip that constitutes a cache memory device of a parallel computer is mounted on the main board. ◆ In addition, one or more slave boards that constitute the main memory of the parallel computer are mounted on the main board. ◆ Also, the power supplied to the main board is supplied to the area on the main board where the integrated circuit chips that form the system control device are mounted and the area where each slave board on which the instruction processor is mounted is mounted via the power bus. Power is supplied from the outside so that the power supply to the slave substrate can be stopped while the main substrate is operating. ◆ Furthermore, the sub board, whose power supply is stopped while the main board is operating, can be inserted and removed from the main board.

[0007]

First, since the system controller having a large number of input / output pins is mounted on the main board which does not need to take out the pins from the back side, the subsystem for the system controller which is larger than necessary only for taking out the pins is provided. There is no need to make a board. ◆
Secondly, since the slave board forming the instruction processor is directly mounted on the main board forming the system controller, a cable and a cable connector for connecting the instruction processor and the system controller are not required, and the mounting area is reduced. It can be reduced. ◆ Thirdly, in the main board constituting the system controller, the pitch of through holes for connecting signals to the integrated circuit chips is made smaller than the arrangement pitch of the input / output pins on the back surface of the conventional slave board. The mounting area of the integrated circuit chip constituting the system control device can be reduced as compared with the case where the integrated circuit chip is mounted on the slave substrate, and the mounting density is further improved. Fourth, there is a method of improving the access time by using a cache memory when access is concentrated from a plurality of instruction processors to one main memory, but in this case, control of the cache memory and the main memory is performed. Is performed by the system controller, so by mounting the system controller and the cache memory on the main board at the same time, it is possible to shorten the access time from the system controller to the cache memory and improve the controllability of the entire system. it can. Fifth, the instruction processor and the main processor are seen from the system controller by simultaneously mounting the slave board constituting the instruction processor and the slave board constituting the main memory device on the main board constituting the system controller. The storage devices will appear to be at the same distance. This enables high-speed processing without a cache memory, such as when a plurality of instruction processors concentrate access to a single main storage device, reduces the number of chips required in the system, reduces costs, and improves reliability. It is possible to improve. ◆ Sixth, while the main board is in operation, it is possible to stop the power supply to any of the above-mentioned sub boards, and stop the instruction processor that has malfunctioned due to some failure, thus wasting power. You can save. ◆ Seventh, while the main board is in operation, the sub board whose power supply has been stopped can be inserted into and removed from the main board, and the instruction processor, which has malfunctioned due to some failure, stops the entire system. Instead, it becomes possible to replace it with a good one.

[0008]

1 is a perspective view showing a first embodiment of the present invention, and FIG. 8 is a block diagram showing the structure of FIG. A central processing unit 100 of a parallel computer is composed of a main board 1 on which a sub board 2 is mounted, and an integrated circuit constituting one instruction processor (15a to 15d) on each of the four sub boards 2. The chip group 3 is mounted on the main board 1 and the integrated circuit chip group 4 constituting the system control device 16 is mounted. Further, on the main board 1, a cable connector 5 for joining a cable 6 that connects the main storage device 17 and the system control device 16 is mounted. Here, the main substrate 1 can be manufactured by using the printed wiring board technology, and the slave substrate 2 can be manufactured by using the ceramic module board technology. Here, the pitch of the input / output pins (not shown) on the back surface of the slave board 2 is about 2 mm, and the through-hole pitch of the main board is about 1.3 mm, and the system controller is mounted on the conventional slave board. Compared to the case, integrated circuit chip 4
The mounting pitch of can be reduced. Further, for connection between the main board 1 and the slave board 2, it is possible to apply the surface connection type connector 13 used in the mounting system of the conventional large-scale parallel computer.

In the first embodiment, the system controller 16
Integrated circuit chip group 4 and instruction processor 15a
Since the signal connection between each of the sub-boards 2 on which ~ 15d is mounted is performed using the fine wiring in the main board 1, it is not necessary to route a large amount of signal cables as in the conventional case, and from this point as well, It is possible to connect more instruction processors to the system controller. In the present embodiment, the case where the number of instruction processors is four has been described as an example, but the present invention is not limited to the number of instruction processors, and will be described in another embodiment below. Including the above, it is possible to apply to implementation of a system control device to which an arbitrary number of instruction processors are connected.

FIG. 2 is a perspective view showing a second embodiment of the present invention, and FIG. 9 is a block diagram showing the structure of FIG. In the second embodiment, in addition to the first embodiment, the integrated circuit chip group 7 forming the cache memory is mounted on the main substrate 1. As a result, the mounting distance between the integrated circuit chip group 4 forming the system control device and the integrated circuit chip group 7 forming the cache memory can be shortened, and the time required to access the cache memory can be shortened.

FIG. 3 is a perspective view showing a third embodiment of the present invention, and FIG. 10 is a block diagram showing the configuration of FIG. In the third embodiment, the main storage device 17 which is a separate housing in the first embodiment is mounted on the slave board 9,
This is mounted on the main substrate 1. This allows
Since the cable (6 in FIG. 1) between the integrated circuit chip group 8 forming the main memory device 17 and the integrated circuit chip group 4 forming the system control device 16 can be removed, the mounting distance can be shortened. Access time can be shortened. Therefore, the performance of the entire system can be improved without placing a cache memory as in the second embodiment.

FIG. 4 is a perspective view showing a fourth embodiment of the present invention. In the fourth embodiment, the power to be supplied to the main board 1 is mounted in two areas where the slave board 2 on which the instruction processors 15a to 15b are mounted is mounted, and the integrated circuit chip group 4 which constitutes the system controller 16 is mounted. Total 3 in 1 area
Since the DC power supplies 20a, 20b, and 20c are supplied to the power supply buses 10 and 11 by dividing the power supply buses 10 and 11, the DC power supply 20a or 20c to any slave board 2 is stopped to operate due to some failure. It is possible to stop the operation of the instruction processor that has become defective and save unnecessary power.

FIG. 5 is a perspective view showing a fifth embodiment of the present invention. In the fifth embodiment, since the main board 1 and the slave board 2 are connected by the module connector 13, the power supply to the instruction processor 15b is stopped according to the fourth embodiment. By removing the slave board 2 from the module connector 13 portion shown, the instruction processor 15b, which has malfunctioned due to some failure while the main board 1 is operating, is replaced with a good one without stopping the entire system. It becomes possible.

Incidentally, in the third to fifth embodiments shown in FIGS. 3 to 5, in order to prevent the drawings from being complicated, the configuration is such that the number of instruction processors mounted on the main board is two. However, the present invention is not limited to the number of instruction processors as in the case of the description of the first embodiment. In addition, although the present invention is applied to a multiprocessor parallel computer in each of the above-described embodiments, the present invention is not limited to the multiprocessor parallel computer, but is applicable to various parallel computers such as SIMD. It goes without saying that it is possible.

[0015]

According to the present invention, it is possible to connect a large number of instruction processors to a system controller without degrading the performance of the computer system and without sacrificing the maintainability and reliability of the system. A circuit chip mounting structure can be provided. ◆ By constructing a large-scale parallel computer etc. using this integrated circuit chip mounting structure, a large-scale parallel computer etc. with lower cost and higher processing capacity can be realized as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a perspective view showing a first embodiment of the present invention.

FIG. 2 is a perspective view showing a second embodiment of the present invention.

FIG. 3 is a perspective view showing a third embodiment of the present invention.

FIG. 4 is a perspective view showing a fourth embodiment of the present invention.

FIG. 5 is a perspective view showing a fifth embodiment of the present invention.

FIG. 6 is a perspective view showing a first conventional example.

FIG. 7 is a perspective view showing a second conventional example.

FIG. 8 is a block diagram showing the configuration of FIG.

FIG. 9 is a block diagram of the configuration of FIG.

FIG. 10 is a block diagram of the configuration of FIG.

11 is a block diagram of the configuration of FIG.

12 is a block diagram of the configuration of FIG. 7.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 main board 2 slave board which comprises an instruction processor 3 integrated circuit chip group which constitutes an instruction processor 4 integrated circuit chip group which constitutes a system controller 5 cable connector 6 cable 7 integrated circuit chip group which constitutes a cache memory 8 main memory Integrated circuit chip group constituting device 9 Sub-board constituting a part of main memory device 10 Power potential power bus 11 Ground potential power bus 12 Input / output pin 13 Module connector 14 Package connector 15a to 15d Instruction processor 16 System controller 17 Main storage device 20a to 20c DC power supply device 100 Central processing unit

Claims (6)

[Claims] 1. An integrated circuit chip mounting structure in a parallel computer comprising a system control device and a plurality of instruction processors, wherein an integrated circuit chip group constituting the system control device is mounted on a main board, and a plurality of sub-boards. An integrated circuit chip group that constitutes each of the instruction processors is mounted on each of the above, and an instruction processor is configured by one sub-board, and a plurality of sub-boards on which the instruction processors are configured are mounted on the main board. An integrated circuit chip mounting structure, wherein the parallel computer is mounted on the main board so as to constitute the parallel computer. 2. The integrated circuit chip mounting structure according to claim 1, wherein input / output pins for connecting the main board and the sub board are provided on the lower surface of the sub board, and through holes are arranged in the main board. An integrated circuit chip mounting structure, wherein a pitch is smaller than an arrangement pitch of input / output pins provided on the lower surface of the slave substrate. 3. The integrated circuit chip mounting structure according to claim 1 or 2, wherein an integrated circuit chip constituting a cache memory device of a parallel computer is mounted on the main substrate. Chip mounting structure. 4. The integrated circuit chip mounting structure according to claim 1 or 2, wherein one or more slave boards constituting a main memory of a parallel computer are mounted on the main board. Integrated circuit chip mounting structure. 5. The integrated circuit chip mounting structure according to claim 1, wherein an area on which an integrated circuit chip group forming the system control device for supplying power to the main board is mounted is provided on the main board. And supplying power to the sub-boards on which the sub-boards on which the instruction processor is configured are externally supplied via a power bus and stopping the power supply to the sub-boards while the main board is operating. An integrated circuit chip mounting structure, which is capable of 6. The integrated circuit chip mounting structure according to claim 5, wherein the sub-board whose power supply is stopped while the main board is operating can be inserted into and removed from the main board. Chip mounting structure.