JPH07335832A - Semiconductor protective device - Google Patents

Abstract

PURPOSE:To prevent breakdown due to a surge current by controlling concentration of the surge current to the end part of a first-conductivity-type region which will become an input protective resistor. CONSTITUTION:Any one of the second first-conductivity-type isolating region 10 which is joined and isolated from the first-conductivity-type substrate 1 by the second-conductivity-type buried region 11 or trench-shaped insulator region is provided to the second-conductivity-type region 3 provided between one end side of the first-conductivity-type region 5 which will become an input protection resistor and the first first-conductivity-type isolating region 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection device having a large surge resistance.

[0002]

2. Description of the Related Art As a conventional semiconductor protection device, for example, there is one shown in FIGS. 3 and 4 (Japanese Patent Laid-Open No. 57-6).
8071). Both figures show the part related to the input protection resistance in the semiconductor protection device. The N-type epitaxial layer 2 is epitaxially grown on the main surface of the P-type substrate 1, and the N-type epitaxial layer 2 surrounds the P-type isolation region 4 in the surroundings. And an N-type region 3 which is separated by junction is formed. The input protection resistor 20 is formed by the P-type region 5 formed on the main surface of the N-type region 3. A first P ⁺ type region 8 is formed on one end side of the main surface of the P type region 5, and a second P ⁺ type region 9 is formed on the other end side. The first P ⁺ type region 8 is connected to the input terminal 16 and the second P ⁺ type region 9 is connected.
Is connected to at least one of a protection diode (not shown) and a protected internal circuit. P ⁺ type regions 6 and 7 connected to the V _ss terminal on the main surface of the P type isolation region 4
Are formed. A diode 25 is formed by the junction between the P-type region 5 and the N-type region 3, and a diode 24 is formed by the junction between the P-type isolation region 4 and the N-type region 3. PN having the P-type region 5 as an emitter, the N-type region 3 as a base, and the P-type isolation region 4 as a collector
A P-type transistor 21 is formed, and a PNP-type transistor 22 having the P-type region 5 as an emitter, the N-type region 3 as a base, and the P-type substrate 1 as a collector is formed. PN
The collector of the P-type transistor 22 is connected to the V-type via the resistor 23 formed of the P-type substrate 1 and the P-type isolation region 4.
It is connected to the _ss terminal.

When an overvoltage surge (hereinafter, simply referred to as a surge) is applied to the input protection resistor having such a configuration, the internal circuit is protected by the following action. (A) When a positive surge is applied to the input terminal 16 with respect to the V _ss terminal, the diode 25 is forward-biased and the diode 24 is reverse-biased.
1, 22 turn on. Surge current is input terminal 16
To the V _ss terminal through the diodes 24 and 25 or the PNP transistor 21 or 22. (B) When a negative surge is applied to the input terminal 16 with respect to the V _ss terminal, the diode 25 is reverse biased and the diode 24
Is forward-biased, the reverse transistor of the PNP type transistor 21 and the reverse transistor of the PNP type transistor 22 are turned on. The surge current _flows from the V _ss terminal to the diodes 24 and 25, the reverse transistor of the PNP type transistor 21, or the PNP type transistor 22.
Flows to the input terminal 16 through the reverse transistor of.

[0004]

However, such a conventional semiconductor protection device has the following problems. (A) When a positive surge is applied to the input terminal 16 with respect to the V _ss terminal. The surge current concentrates at the end of the P-type region 5 near the first P ⁺ -type region 8 for the following reason. As a result, the semiconductor protection device is easily destroyed. In the series circuit of the diodes 24 and 25, the parasitic resistance (not shown) inside the P-type region 5 on the anode side of the diode 25 and the parasitic resistance inside the N-type region 3 at the connection point between the diodes 24 and 25 (not shown). The presence of the surge current causes the surge current flowing through the diodes 24 and 25 to be the shortest path, that is, from the end of the P-type region 5 near the first P ⁺ -type region 8 to the P-type isolation region 4 facing this end. Take the route to. The surge current flowing through the PNP-type transistor 21 is a path where the emitter resistance (not shown) by the P-type region 5 is minimized and the base length is the shortest, that is, the P-type region near the first P ⁺ -type region 8. The path from the 5th end to the P-type isolation region 4 facing this end is taken. An electron current due to breakdown of the diode 24 laterally flows from the P-type region 5 to the vicinity of the main surface of the N-type region 3. Therefore, due to the emitter current concentration effect, PNP
The emitter-base bias of the p-type transistor 21 is P
It becomes strongest at the end of the mold region 5. Therefore, the current flowing through the PNP type transistor 21 concentrates at the end of the P type region 5. Even if the distance between the P-type region 5 and the P-type isolation region 4 on the first P ⁺ -type region 8 side is increased to decrease the current amplification factor α of the PNP-type transistor 21, the P The current concentration at the end of the mold region 5 is not sufficiently improved. Therefore, the semiconductor protection device is easily damaged by the surge current.

(B) When a negative surge is applied to the input terminal 16 with respect to the V _ss terminal. The surge current concentrates at the end of the P-type region 5 near the first P ⁺ -type region 8 for the following reason. As a result, the semiconductor protection device is easily destroyed. P
Regarding the breakdown voltage of the junction formed by the type region 5 and the N-type region 3, the value at the end of the P-type region 5 is generally lower than the value at the bottom of the P-type region 5, and the above-mentioned (a) Due to the action, the breakdown current of the diode 25 is concentrated at the end of the P-type region 5. By the same operation as the above (a), the PNP
The current flowing through the reverse transistor of the type transistor 21 is
At the end of the P type region 5, it concentrates in the vicinity of the P ⁺ type region 8. A resistor 23 is connected in series to the emitter of the reverse transistor of the PNP transistor 22.
Therefore, when a surge current flows through the resistor 23, the emitter-base bias of the reverse transistor of the PNP type transistor 22 decreases. Therefore, PNP transistor 2
The reverse transistor of 2 cannot fully bypass the surge current. Further, as in the case of (a) above, even if the distance between the P-type region 5 and the P-type isolation region 4 on the P ⁺ -type region side is increased, the end portion of the P-type region 5 due to the current of the diode 25 described above. The current concentration on is not sufficiently relaxed. Therefore, the semiconductor protection device is easily damaged by the surge current.

The present invention has been made by paying attention to such a conventional problem, and suppresses the surge current concentration at the end portion of the first conductivity type region serving as the input protection resistance to prevent the breakdown due to the surge. It is an object of the present invention to provide a semiconductor protection device that can be manufactured.

[0007]

In order to solve the above-mentioned problems, the present invention firstly provides a second surface on a main surface of a first conductivity type substrate.
The conductive type region is formed by being joined and separated from the surroundings in the first first conductive type isolation region, and the first conductive type region serving as an input protection resistor is formed on the main surface of the second conductive type region. 1
One end side of the conductivity type region is connected to either the input terminal or the output terminal and the other end side is connected to at least one of the protection diode and the protected internal circuit, and the first conductivity type isolation region is connected to the low potential terminal. Alternatively, in a semiconductor protection device connected to either of a power supply terminal, a second conductive type region is provided between the one end side of the first conductive type region and the first first conductive type isolation region. The gist of the present invention is to provide either a second first-conductivity-type isolation region or a trench-type insulator region which is separated from the first-conductivity-type substrate by a conductive-type buried region.

Second, a first first-conductivity-type high-concentration region is formed on one end side of the first-conductivity-type region, and the first first-conductivity-type high-concentration region is connected to the input terminal or the output terminal. A second high-concentration region of the first conductivity type is formed on the other end side of the first-conductivity type region while being connected to one of the regions, and the second high-concentration region of the first conductivity type is formed into the protection diode or the protected region. The gist is that it is connected to at least one of the internal circuits.

[0009]

In the above structure, first, the second conductivity type buried region is provided in the second conductivity type region between the one end side of the first conductivity type region and the first isolation region of the first conductivity type. By providing either the second conductivity type isolation region or the trench type insulator region which is separated from the first conductivity type substrate by junction, the junction between the first conductivity type region and the second conductivity type region and the first The surge current flowing through both diodes formed by the junction between the first-conductivity-type isolation region and the second-conductivity-type region is applied to one end side of the first-conductivity-type region and to the first end facing the one-end side. The shortest path to the first conductivity type isolation region cannot flow.
Therefore, the surge current concentration on the one end side of the first conductivity type region is alleviated. Further, in a parasitic transistor having the first conductivity type region as an emitter, the second conductivity type region as a base, and the first first conductivity type isolation region as a collector, a parasitic transistor is provided between the emitter and one end side of the first conductivity type region. Parasitic resistance 15 in series
The parasitic resistance 15 lowers the emitter-base bias and suppresses the current value. Therefore, the surge current concentration on the one end side of the first conductivity type region is alleviated. When a second first-conductivity-type isolation region is further provided, a parasitic transistor having the first-conductivity-type region as an emitter, the second-conductivity-type region as a base, and the second first-conductivity-type isolation region as a collector, and The second isolation region of the first conductivity type is the emitter, the isolation region of the second conductivity type is the base,
A parasitic transistor having the collector of the first isolation region of the first conductivity type is formed, but the combined base ground current amplification factor in which both parasitic transistors are connected in series is smaller than the current amplification factor of the single parasitic transistor. Surge current concentration on one end side of the conductivity type region is mitigated. As described above, the surge current density flowing through each parasitic diode or each parasitic transistor is reduced, and the surge current is not concentrated on a specific parasitic diode or parasitic transistor, and the surge current is concentrated on one end side of the first conductivity type region. Since this is mitigated, the semiconductor protection device is prevented from being damaged by the surge.
In addition, since the second isolation region of the first conductivity type only surrounds a part of the first conductivity type region, the impedance of the protection device at the time of applying a surge does not become excessive, and the internal circuit of the protected internal circuit against the surge is prevented. Protection is guaranteed.

Secondly, when the surface concentration of the first conductivity type region is low, the first first conductivity type high concentration region is formed on one end side of the first conductivity type region and the first concentration is on the other end side. By forming the second high-concentration region of the first conductivity type, the ohmic contact can be surely made and the proper operation of the semiconductor protection device is guaranteed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIG. 1 and FIG. 2, the same or equivalent members and parts as those in FIG. 3 and FIG. First, the structure of the semiconductor protection device will be described. In the present embodiment, an end portion of the P-type region 5 near the first P ⁺ -type region 8 and a P-type isolation region 4 facing the end portion are formed. A second P-type isolation region 10 is formed in the N-type region 3 between. The second P-type isolation region 10 and the P-type substrate 1 are junction-separated by the N-type buried region 11. P in the vicinity of the first P ⁺ type region 8
A PNP transistor 12 is formed which has the type region 5 as an emitter, the N type region 3 as a base, and the second P type isolation region 10 as a collector, and the second P type isolation region 10 is an emitter and an N type region. Based on 3,
P using the first P-type isolation region 4 as a collector
The NP type transistor 13 is formed. In addition, the P-type region 5 near the first P ⁺ -type region 8 is the emitter, and the N-type region 3 is
Is formed as a base, and the PNP type transistor 14 having the first P type isolation region 4 as a collector is formed.
The emitter of the PNP type transistor 14 is connected to the first P ⁺ type region 8 via the parasitic resistance 15 inside the P type region 5.

Next, the operation of the semiconductor protection device configured as described above will be described. (A) When a positive surge is applied to the input terminal 16 with respect to the V _ss terminal. Diode 24
Breakdown and the diode 25 is forward biased. The breakdown current of the diode 24 turns on the PNP transistors 22, 12, and 14. Then, holes, which are currents of the PNP type transistor 12, are injected into the second P type isolation region 10, and the potential of the second P type isolation region 10 rises, so that the PNP type transistor 13 is turned on. The surge current flows from the input terminal 16 to the diodes 24 and 25, the PNP type transistor 22, the PNP type transistors 12 and 13, or the PN.
It flows to the V _ss terminal through the P-type transistor 14. Here, in this embodiment, the current concentration at the end portion of the P-type region 5 is relaxed by the action described below, and the semiconductor protection device is prevented from being destroyed. Assuming that the base ground current amplification factor of the PNP type transistor ₁₂ is α ₁₂ and the base ground current amplification factor of the PNP type transistor 13 is α ₁₃ , the combined base ground current amplification factor of the circuit in which the PNP type transistors 12 and 13 are connected in series. α ′ is α ′ = α ₁₂ · α ₁₃ <min (α ₁₂ , α ₁₃ ), because | α ₁₂ | <1 and | α ₁₃ | <1. Therefore, α'is smaller than the current amplification factor of the PNP type transistor alone, so that PNP type transistors 12 and 1
The magnitude of the surge current flowing through 3 does not become excessive. Therefore, the concentration of current on the end portion of the P type region 5 in the vicinity of the first P ⁺ type region 8 is relaxed as compared with the conventional example. Since the second P-type isolation region 10 is junction-separated from the P-type substrate 1 by the N-type buried region 11, the PNP-type transistor 12 passes through the second P-type isolation region 10 to the P-type substrate 1. There is no current path to reach. So, like
No current concentration occurs at the end of the P-type region 5. The diode 24 due to the presence of the second P-type isolation region 10.
Surge currents flowing through the first and second P ⁺ -type regions 8 from the end of the P-type region 5 near the first P ⁺ -type region 8 to the first P-type region 5 facing the end.
It cannot flow on the shortest path to the mold isolation region 4. Therefore, the parasitic resistance (not shown) of the series circuit of the diodes 24 and 25 becomes larger than the parasitic resistance in the conventional example. Therefore, the magnitude of the surge current flowing through the diodes 24 and 25 is smaller than that of the conventional example.
Since there is the second P-type isolation region 10,
The current of the PNP type transistor 14 is the first P ⁺ type region 8
It is implanted from the P-type region 5 other than the vicinity to the N-type region 3. Here, since the transistor current flows through the parasitic resistance 15, a voltage drop occurs in the parasitic resistance 15. Therefore PN
The emitter-base bias of the P-type transistor 14 is reduced, and the current concentration on the PNP-type transistor 14 is reduced. Since the PNP transistor 22 has a vertical structure, the surge current is injected into the N-type region 3 from the wide area of the bottom surface of the P-type region 5 as in the conventional case. Therefore, the surge current density flowing through the PNP transistor 22 is low.

(B) When a negative surge is applied to the input terminal 16 with respect to the V _ss terminal. Diode 24 is forward biased and diode 25 breaks down. Diode 2
Due to the breakdown current of 5, the PNP type transistors 22, 1
The reverse transistors of 2, 13, and 14 respectively are turned on. The surge current _flows from the V _ss terminal to the reverse transistor of the PNP type transistor 22, the reverse transistor of the PNP type transistors 12 and 13, or the PNP type transistor 14.
Flows to the input terminal 16 through the reverse transistor of. Here, in this embodiment, the semiconductor protection device is prevented from being broken by the following actions. As in the case of (a), PN
The current amplification factor of the circuit in which the reverse transistor of the P-type transistor 12 and the reverse transistor of 13 are connected in series is P
Since it is smaller than the current amplification factor of the reverse transistor alone of the NP type transistor 12 or 13, the magnitude of the surge current flowing through the reverse transistor of the PNP type transistor 12 and the reverse transistor of the PNP type transistor 13 does not become excessive. Therefore, the concentration of current on the end portion of the P type region 5 in the vicinity of the first P ⁺ type region 8 is relaxed as compared with the conventional example.
Similar to (a), there is no current path from the P-type substrate 1 to the P-type region 5 via the reverse transistor of the PNP-type transistor 12. Therefore, current concentration does not occur at the end of the P-type region 5. Similar to (a), the value of the surge current flowing through the diodes 24 and 25 is small. Since the second P-type isolation region 10 is provided, the base length of the reverse transistor of the PNP-type transistor 14 becomes long, the current amplification factor decreases, and the parasitic resistance 15 is connected to the collector. The surge current that flows through the reverse transistor is limited, and current concentration is less likely to occur. Similar to (a), the PNP transistor 22
The reverse transistor has a vertical structure, so the surge current density is low.

As described above, in the present embodiment, the diodes 24 and 25, the PNP type transistors 12 and 13, and P.
NP type transistor 14 and PNP type transistor 22
The density of the surge current flowing through is low, and the surge current does not concentrate on a specific transistor or diode. Therefore, the semiconductor protection device is less likely to be damaged by the surge. In addition, the second P-type isolation region 1
Since the 0 and N type buried regions 11 surround only a part of the P type region 5, the impedance of the semiconductor protection device does not become excessive. That is, the ratio of the surge current flowing through the series circuit of the PNP type transistors 12 and 13 is small, but most of the surge current flows through the diodes 24 and 25, the PNP type transistor 14, or the PNP type transistor 22. Therefore, the surge current is not injected into the internal circuit through the input protection resistor 20 and the internal circuit is not destroyed.

If the surface concentration of the P-type region 5 is high enough to make ohmic contact, the first and second regions are formed.
This semiconductor protection device operates even if the P ⁺ type regions 8 and 9 are not formed. Further, when the trench type insulator region is formed instead of the second P type isolation region and the N type buried region 11 is not formed, the PNP type transistor 1 is used.
2 and 13 are not formed. Therefore, the first P ⁺ type region 8
It is even more difficult for the current to concentrate on the end portion of the P-type region 5 in the vicinity. Therefore, the semiconductor protection device is less likely to be damaged by the surge. In this embodiment, the case where the main protection device is formed on the P-type substrate has been described. However, when the main protection device is formed on the N-type substrate, the P-type and the N-type are replaced in the above description, The V _ss terminal may be the V _dd terminal. Further, in the present embodiment, the case where the protective device is connected to the input terminal has been described. However, even when the protective device is connected to the output terminal, the same protective effect as described above is produced.

[0016]

As described above, according to the invention described in each claim, the following effects are obtained.

According to the first aspect of the present invention, one end side of the first conductivity type region serving as the input protection resistor, which is connected to either the input terminal or the output terminal, and the first isolation region of the first conductivity type. Since the second conductivity type region in between is provided with either the second first conductivity type isolation region or the trench type insulator region which is bonded and separated from the first conductivity type substrate by the second conductivity type buried region, First conductivity type region and second
The current flowing through both parasitic diodes formed by the junction between the conductivity type regions and the junction between the first first conductivity type isolation region and the second conductivity type region is at one end side of the first conductivity type region and this one end side. The shortest path to the opposing first isolation region of the first conductivity type cannot flow, and the surge current concentration on one end side of the first conductivity type region is alleviated. Further, in a parasitic transistor having the first conductivity type region as an emitter, the second conductivity type region as a base, and the first first conductivity type isolation region as a collector, a parasitic transistor is provided between the emitter and one end side of the first conductivity type region. Parasitic resistance occurs in series,
This parasitic resistance lowers the bias between the emitter and the base and suppresses the current value. Therefore, the concentration of the surge current on the one end side of the first conductivity type region is alleviated also through this path. Further, when the second first-conductivity-type isolation region is provided, a parasitic transistor having the first-conductivity-type region as an emitter, the second-conductivity-type region as a base, and the second first-conductivity-type isolation region as a collector And a parasitic base transistor having the second first conductivity type isolation region as an emitter, the second conductivity type region as a base, and the first first conductivity type isolation region as a collector, a combined base ground current amplification factor Becomes smaller than the base ground current amplification factor of the single parasitic transistor, so that the surge current concentration on the one end side of the first conductivity type region is alleviated also in this path. In this way, the surge current concentration on one end side of the first conductivity type region is relaxed, the surge current density flowing through each parasitic diode or each parasitic transistor is reduced, and the surge current to a specific parasitic diode or parasitic transistor is reduced. It is possible to prevent the semiconductor protective device from being damaged by the surge due to the lack of concentration.

According to a second aspect of the present invention, a first first-conductivity-type high-concentration region is formed on one end side of the first-conductivity-type region, and the first first-conductivity-type high-concentration region is input. A second high-concentration region of the first conductivity type is formed on the other end side of the first-conductivity type region while being connected to either a terminal or an output terminal to protect the second high-concentration region of the first conductivity type. Since it is connected to at least one of the diode and the protected internal circuit, the ohmic contact of the first conductivity type region portion serving as the input protection resistance can be surely made, and the semiconductor protection device can be operated more properly.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing an embodiment of a semiconductor protection device according to the present invention.

FIG. 2 is a plan view of the above embodiment.

FIG. 3 is a vertical sectional view of a conventional semiconductor protection device.

FIG. 4 is a plan view of the above conventional example.

[Explanation of symbols]

1 P-type substrate 3 N-type region 4 First P-type isolation region 5 P-type region 8, 9 First and second P ⁺ -type regions 10 Second P-type isolation region 11 N-type buried region 16 Input terminal

Claims (2)

[Claims] 1. A main surface of the second-conductivity-type region is formed by forming a second-conductivity-type region on the main-surface of the first-conductivity-type substrate while being separated from the surroundings by a first first-conductivity-type isolation region. A first conductivity type region serving as an input protection resistor is formed on one side, one end side of the first conductivity type region is connected to either an input terminal or an output terminal, and the other end side is at least a protection diode or a protected internal circuit. A semiconductor protection device connected to any one of the first conductivity type isolation region and the first conductivity type isolation region connected to either a low potential terminal or a power supply terminal, wherein one end side of the first conductivity type region and the first first A second first conductive type junction is separated from the first conductive type substrate by a second conductive type buried region in the second conductive type region between the conductive type isolation regions.
A semiconductor protection device comprising a conductive type isolation region or a trench type insulator region. 2. A first first-conductivity-type high-concentration region is formed on one end side of the first-conductivity-type region, and the first first-conductivity-type high-concentration region is provided as either the input terminal or the output terminal. And a second first-conductivity-type high-concentration region is formed on the other end side of the first-conductivity-type region, and the second first-conductivity-type high-concentration region is connected to the protection diode or the protected internal circuit. The semiconductor protection device according to claim 1, wherein the semiconductor protection device is connected to at least one of the above.