JPH07334562A - Circuit diagram generation system - Google Patents

Abstract

PURPOSE:To provide a circuit diagram generation system capable of efficiently recognizing bundle of signals and generating a circuit diagram easy to see. CONSTITUTION:A signal name discrimination part 121 discriminates the logical connection information accepted from an input device 11 based on characters comprising the name of the signal and stores it in a logical connection discrimination storage part 131. A single/bundle signal extraction part 122 extracts the single signal connection information or bundle signal connection information from the logical connection discrimination storage part 131. An arrangement wiring part 123 arranges the symbol on the circuit diagram based on the logical connection information accepted from the input device 11 and executes wiring between the symbols with bundle lines and single line based on the information received from the part 122. Then, the diagram is outputted to an output device 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for generating a circuit diagram, and more particularly to a circuit diagram generating system for generating a circuit diagram from logical connection information and circuit symbol information generated by a human or a computer system.

[0002]

2. Description of the Related Art Conventionally, as this type of circuit diagram generation system,
For example, as shown in Japanese Patent Laid-Open No. 3-11469 (referred to as "conventional example"), a circuit diagram in which a bundle symbol previously generated by a computer system or created by manual input is used (hereinafter referred to as "old circuit diagram"")) And is used again by the computer system to generate the schematic.

FIG. 11 is a block diagram showing an example of the configuration of the circuit diagram generation system of the conventional example. In the figure, a logical connection storage unit 1101 stores logical connection information of a circuit diagram to be generated.

The old circuit diagram information storage unit 1102 stores old circuit diagram information relating to the old circuit diagram of the circuit diagram to be generated. The temporary bundle symbol extraction unit 1103 extracts a symbol group as a temporary bundle symbol from the old circuit diagram information in the old circuit diagram information storage unit 1102.
The bundled signal name determination unit 1105 determines whether or not the connection signal can be a bundled signal name.

The bundled symbol determination unit 1104 determines whether or not the temporary bundled symbol can be a bundled symbol. The bundled signal name rule storage unit 1106 stores a rule (bundle signal name rule) for determining whether or not the connection signal name can be grouped as a bundled signal name. The placement / wiring unit 1107 places the symbols on the circuit diagram and performs wiring.

FIG. 12 is a flowchart showing the processing of the bundled signal name determination unit 1105.

Next, the processing operation in the conventional circuit diagram generation system will be described.

First, the temporary bundle symbol extraction unit 1103 causes the sheet from the old circuit diagram information in the old circuit diagram information storage unit 1102, a group of symbols having the same X coordinate and Y coordinate (a bundle symbol on the old circuit diagram). When the logical connection information for the symbol group exists in the logical connection storage unit 1101, the symbol group is extracted as a temporary bundle symbol.

Next, the bundled signal name determination unit 1105 extracts the connection signal relating to each pin of the temporary bundled symbol extracted by the temporary bundled symbol extraction unit 1103, and stores the bundled signal name rule in the bundled signal name rule storage unit 1106. Based on the above, it is determined whether or not they can be used as a bundle signal name.

Next, the bundle symbol determination unit 1104 determines whether or not the temporary bundle symbol can be a bundle symbol based on the determination by the bundle signal name determination unit 1105.

Finally, the layout and wiring unit 1107 uses the logical connection information in the logical connection storage unit 1101 to determine the bundle symbol determination unit 11
The bundle symbol group determined by the determination in 04 and the other symbols are distinguished and arranged on the circuit diagram, and the bundle lines and the single lines (normal lines other than the bundle lines) are distinguished and wired.

[0012]

However, the circuit diagram generating method proposed in the above-mentioned conventional example utilizes the old circuit diagram information generated by the computer system or manually input to generate the bundle symbol. Since the judgment is made, it is not effective when the old circuit diagram does not exist. If the old circuit diagram information cannot be used, the connection signal name must be checked for each symbol group having the same symbol type (shape, function, and pin position and type) to determine the bundle symbol. Therefore, there is a problem that the processing time increases as the number of symbols of the same symbol type increases.

Further, since the character string of the signal name is analyzed for each connection signal related to each pin of the symbol group having the same symbol type and it is determined whether or not the bundled signal name can be obtained, the number of connection signals is determined. There is a problem that the processing time increases as the number increases.

Further, even when each signal name of a certain signal group can be converted into the same bundled signal name based on the bundled signal name rule,
When the types of symbols of the symbol groups connected to the signal group are not the same, the symbol group cannot be set as one bundled symbol, and the signal group cannot be wired with one bundled signal as a bundled signal. There is a problem that the generated wiring on the drawing becomes difficult to see.

Therefore, it is an object of the present invention to solve the above problems and provide a system for generating a circuit diagram which enables efficient recognition of a bundle signal and generation of a circuit diagram which is easy to see.

[0016]

In order to achieve the above object, the present invention provides a system for generating a circuit diagram from logical connection information and circuit symbol information, in which the logical connection information of the circuit diagram to be generated constitutes a signal name. Signal name sorting means for sorting by the characters, logical connection sorting storage means for storing the logical connection information sorted by the signal name sorting means, and a single signal or a bundle from the information stored in the logical connection sorting storage means. A single / bundle signal extracting means for extracting a signal;
Arrangement and wiring means for arranging the symbols on the circuit diagram based on the information from the bundle signal extraction means, and arranging them by bundle lines and single lines
There is provided a circuit diagram generation system including:

Further, preferred embodiments of the logical connection classification storage means, the signal name classification means, and the single / bundle signal extraction means in the present invention are as set forth in the second and subsequent claims.

[0018]

According to the present invention, in the present invention, the signal name discriminating means discriminates the logical connection information received from the input device by the characters constituting the signal name and stores it in the logical connection discriminating storage means. The signal extraction means determines whether or not the signal name can be grouped as a bundled signal from the logical connection classification storage means to extract single signal connection information or bundled signal connection information, and the placement and wiring means receives from the input device. The symbols are arranged on the circuit diagram based on the logical connection information, the symbols are wired by a bundled line and a single line based on the information received from the single / bundle signal extraction means, and the drawing is output to the output device. Since the logical connection information of the circuit diagram is sorted and stored in advance by the characters that make up the signal name and the connection information of the bundle signal or the single signal is extracted from that information, the processing time of circuit generation can be shortened. Further, according to the present invention, since the bundle signal is recognized by the signal name, the signal groups that connect the symbol groups that cannot be set as the bundle symbols because the types of the symbols are not the same are also bundled as a bundle signal. It is possible to wire with a single wire, and therefore the generated wiring on the drawing is simple and easy to see.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

[0020]

[Embodiment 1] FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, the circuit diagram generation system according to the present exemplary embodiment includes an input device 11, a signal name classification unit 121, and a single / single unit.
It is composed of a bundle signal extraction unit 122, a layout wiring unit 123, a logical connection information classification storage unit 131, and an output device 14.

The signal name classification unit 121 classifies the logical connection information received from the input device 11 according to the characters forming the signal name and stores it in the logical connection classification storage unit 131. The single / bunch signal extraction unit 122 determines whether the signal name can be grouped as a bundle signal from the logical connection classification storage unit 131, and extracts the single signal connection information or the bundle signal connection information. The placement and wiring unit 123 places the symbols on the circuit diagram based on the logical connection information received from the input device 11, and wires the symbols by a bundled line and a single line based on the information received from the single / bundle signal extraction unit 122, The drawing is output to the output device 14.

FIG. 2 is a diagram showing a data storage structure in the logical connection information classification storage unit 131.

The connection table 23 is a table for storing connection information for each signal, and each entry is composed of a symbol name of a circuit element to which the signal is connected and its terminal name.

The character index table 22 is a table for classifying the connection information for each signal by the characters forming the signal name, and each entry has a character index 221.
And a character index table address part 222 for storing the address of another character index table, and a connection table address part 22 for storing the address of the connection table.
Composed of 3 and.

In the logical connection information sorting storage unit 131,
The character index table 22 is different from the character index table 2 by the character index table address section 222.
Pointed to 2 to form a chain.

The character index table directly pointed to by the table entry 21 provided in the logical connection information sorting storage unit 131 is the level 1 character index table, and the character index table address of any entry in the level n character index table. The character index table pointed to by the section is called a level (n + 1) character index table.

More specifically, referring to, for example, the signal name BAR1 in FIG. 2, the table entry 21 stores the characters'B ',' C ',' P ',' Y ', and'Z'. The address of the character index table 22 of the level 1 is stored, and in the character index table 22 of the level 1, the character index table address part of the entry in which the first character'B 'of the signal name BAR1 is stored in the character index 221. The address of the level 2 character index table (which stores characters'A ',' D ', and' 8 ') is stored in 222, and the second character of the signal name BAR1 in the level 2 character index table is stored. The character index table address portion 222 of the entry storing A'in the character index 221 stores the level 3 character index table (stores'A ',' B ',' R ', and'V'). The dress is stored. Also, the address of the connection table 23 is stored in the connection table address part 223 of the entry that stores the termination character '1' of the signal name BAR1 in the character index 221, and the character index table address part 222 of the entry has a chain. Is stored, that is, a predetermined code (for example, NUL or the like) indicating that it is empty.

Next, the operation of this embodiment will be described with reference to FIGS. 1, 2, 3, and 4. FIG. 3 is a flowchart showing the operation of the signal name classification unit 121 in this embodiment. FIG. 4 shows a single / bundle signal extraction unit according to the present embodiment.
It is a flow chart showing operation of 122.

The operation of the signal name classification unit 121 will be described with reference to FIG. The circuit logical connection information input from the input device 11 is supplied to the signal name classification unit 121.

The signal name classification unit 121 sequentially scans the character string of the signal name of the received logical connection information and the chain of the character index table 22 in the logical connection information classification storage unit 131.

First, the address of the table entry 21 of the logical connection information sorting storage unit 131 is set in the variable P (step
301), the control variable N for managing the number of characters of the signal name is initialized to 1 (step 302).

Next, it is determined whether or not the content of the address pointed to by the variable P is empty (step 303).
That is, when the variable N is 1, the table entry
When the address of the character index table is not stored in 22, an empty character index table in which the content of the entry is cleared is newly created, and the address pointed to by the variable P, that is, the table entry in this case.
It is stored in 22 (step 304). By this, the variable P
The address content pointed to by will point to the character index table (ie, not empty), step 305.
Subsequent processing is performed.

Further, when the processing of the characters of the signal name progresses and the variable N for managing the number of characters is larger than 1 (however, the length of the signal name or less), the variable P is determined in the judgment of step 303.
In step 309, the address of the character index table address part is stored, and it is determined whether or not the content of the address pointed to by the variable P is empty. In this case, that the address content pointed to by P is empty means that a predetermined code indicating that the character index table of the next level does not exist (that is, is empty) is stored in the character index table address part. Say.

Then, the variable T is set to the address of the character index table (step 305). In step 305, the character index table pointed to by the address content pointed to by the variable P is referred to by the address stored as the content of the address (= value of the variable P) of the table entry 22 when the variable N is 1, for example. It means a character index table and corresponds to a so-called indirect addressing operation. As the address pointer P, a predetermined register or the like in the data processing device 12 is used.

It is checked whether the entry corresponding to the nth character of the signal name is in the level n character index table (step 307). Specifically, the character extracted by the control variable N for managing the number of characters of the signal name is set to the variable C.
(Step 306) and scans the character index table for an entry whose character index matches the character stored in variable C (step 30).
7).

If there is no match, a new entry is created in the scanned character index table for storing the scanned character (step 308).

Next, the address of the character index table address portion of the entry storing the character to be scanned is set in the variable P (step 309), and the number of characters in the signal name is managed so as to scan the character next to the signal name. Control variable N for
The value of is incremented (increased) by 1 (step 31)
0).

The value of the control variable N is compared with the length of the signal name (step 311) until the last character of the signal name is reached.
The above operation is repeated for the character index table of the next character (that is, the (n + 1) th character) of the signal name and the level (n + 1) (steps 303 to 311).

When the last character of the signal name is reached, a connection table is created from the logical connection information corresponding to the signal name, and the address of the connection table is set to the connection table of the corresponding entry in the character index table at the end of the chain. It is stored in the address part (step 312).

By the above operation, the connection table corresponding to the logical connection information of the connection signal having the signal name length L is the connection table of the entry corresponding to the last character of the signal name in the level L character index table. It will be pointed to by the address part.

The operation of the single / bundle signal extraction unit 122 will be described with reference to FIG.

The single / bundle signal extraction unit 122 traces the chain of the character index table 22 from the table entry 21 of the logical connection information sorting storage unit 131 by the vertical search, and from the entry whose character index in the character index table is a numeral. All the connection tables that can be traced are listed, and they are supplied to the placement and wiring unit 123 as bundle signal connection information (step 404).

More specifically, first, the character index table pointed to by the table entry 21 of the logical connection information sorting storage unit 131 is set in the variable T (step 401). Next, it is determined whether the value of the variable T is a code indicating empty (step 40
2) If not empty, it is determined whether or not there is an entry whose character index is a number in the character index table referenced by the variable T (step 403).

When there is an entry whose character index is a number in the character index table, all connection tables directly traced from each entry and connection tables indirectly traced from the character index table address part of each entry are listed and arranged. It is supplied to the wiring section 123 (step 404).

Then, in the character index table referred to by the variable T, all entries whose character index is a numeral are deleted (step 405). That is, after outputting the bundle signal connection information to the placement and wiring unit 123, for example, as shown in FIG.
In the data storage structure of the logical connection information sorting storage unit 131, the terminal characters “1” of the signal names BAR1 and BAR2,
Level 4 character index table for storing '2'
For 22, clear the character index and each connection table address part.

In the determination processing of step 403, if the character index table does not include an entry whose character index is a number, the character index table address portion of the first entry in the character index table referred to by the variable T is empty. It is determined whether or not the character index table indicated by the address portion of the character index table is empty (step 406). If not, the character of the first entry in the character index table referred to by the variable T is determined. The address of the character index table pointed to by the index table address section is set in the variable T (step 407). This is equivalent to an operation of tracing to the character index table at the end of the chain because the character index table including the entry storing the number as the terminal character of the signal name is searched for in the character index.

If the determination process of step 406 is empty, it corresponds to the case where there is no entry whose character index is a number in the character index table at the end of the chain of the character index table. The information of the connection table pointed to by the connection table address part of the first entry in the table is supplied to the placement and routing part 123 as single-signal connection information (step 40).
8). Then, the first entry of the character index table referred to by the variable T is deleted (step 409).
More specifically, the contents of the first entry, that is, the character index, the character index table address part, and the connection table address part are cleared.

The placement and routing unit 123 places the symbols on the circuit diagram using a known placement method based on the logical connection information received from the input device 11, and then uses the connection information received from the single / bundle signal extraction unit 122. Based on this, a wiring route between the symbols is obtained by using a known wiring method.

When the information received from the single / bunch signal extraction unit 122 is the bundle signal connection information, the drawn portion of the symbol in the obtained wiring path from the terminal is a single line, and the other portions are a bundled wiring diagram. To occur. When the information received from the single / bundle signal extraction unit 122 is single signal connection information, a wiring pattern is generated with all wiring paths as single lines. The generated drawing is output to the output device 14.

Next, this embodiment will be described based on a concrete circuit example.

For example, it is assumed that the logical connection information of the circuit diagram shown in FIG. 5 is given from the input device in the format shown in FIG. The logical connection information indicates, for each signal name in the circuit diagram, the correspondence between the symbol name and terminal name of the circuit element to which it is connected. The logical connection information in FIG. 6 is, for example, the signal name BAR1 in FIG. Indicates that connection is made between the terminal P02 having the symbol name S01, the terminal P01 having the symbol name S09, and the terminal P01 having the symbol name S07.

First, the signal name classification unit 121 receives this logical connection information and stores it in the logical connection information classification storage unit 131 as shown in FIG.
Generate a data storage structure as shown in.

Since the signal name BAR1 and the signal name BAR2 have the first three characters "BAR" in common and the subsequent characters are numbers, the entries in the same character index table have the address of the connection table representing each logical connection. Remembered.

Next, the placement and wiring unit 123 places the symbol on the circuit diagram based on the logical connection information received from the input device.

Next, the single / bundle signal extraction unit 122 examines the inside of the logical connection information classification storage unit 131, and checks the signal name BAR1 and the signal name B.
Two corresponding connection tables of AR2 are listed, and as bundle signal connection information, [S01, P02], [S09, P01],
[S07, P01], [S02, P02], [S09, P02]
Information ([symbol name, terminal name], ...) Is supplied to the placement and wiring unit 123.

Based on this information, the placement / wiring unit 123 obtains a wiring route between the terminals of the symbol, and the drawing portion from the terminal of the symbol in the obtained wiring route is a single line, and the other portions are a bundled wiring pattern. To occur.

Furthermore, when the single / bundle signal extraction unit 122 checks the inside of the logical connection information classification storage unit 131, this time the signal name BAZ
The connection table is extracted, and the information [S03, P02] and [S07, P02] is supplied to the placement and wiring unit 123 as single signal connection information.

Based on this information, the placement / routing unit 123 obtains the wiring paths for the terminals of the symbol, and in this case, the wiring patterns are generated with all the wiring paths as single lines. An example of the placement and routing result is shown in FIG. As shown in FIG. 8, the signal name B of the original circuit
AR1 and BAR2 (see FIG. 5) are combined into one as a bundled signal of the signal name BAR, and symbol names S01, S02 and S09.
Wired between the terminals.

[0059]

Second Embodiment Next, a second embodiment of the present invention will be described.

Referring to FIG. 9, in the second embodiment of the present invention, the storage device 93 has a delimiter storage unit 32 in addition to the configuration of the storage device 13 in the first embodiment shown in FIG. Different in points. FIG. 10 is a flowchart showing the operation of the single / bundle signal extraction unit 122 in the second embodiment.

The operation of this embodiment will be described with reference to FIGS. 9 and 10. In this embodiment, the delimiter of the signal name is input from the input device in addition to the logical connection information of the circuit and stored in the delimiter storage unit 132. The operations of the signal name classification unit 121 and the placement / routing unit 123 are the same as those in the first embodiment, and the description thereof will be omitted.

The single / bundle signal extraction unit 122 traces the chain of the character index table 22 from the table entry 21 of the logical connection information classification storage unit 131 by the vertical search, and the character index in the character index table is stored as the delimiter character storage unit 32. All connection tables that can be traced from the entry that is the delimiter stored in are listed and supplied to the placement and routing unit 123 as bundle signal connection information (step 100
Four).

If the character index table at the end of the chain of the character index table does not have an entry whose character index is a delimiter, it is pointed to by the connection table address part of the first entry in the character index table at the end. The information of the connection table is supplied to the placement and wiring unit 123 as single signal connection information (step 1008).

In the first embodiment, the connection signal group having a common character string until just before the appearance of a number in the character string of the signal name is grouped as a bundled signal. A group of connection signals having a common character string up to immediately before a delimiter appears in the character string is collected as a bundled signal.

As a result, for example, "SIG <0>",
“SIG <1>”, ..., “SIG <E>”, “SIG <
A signal group whose signal name suffix is not a number, such as F> ”, can be grouped as a bundled signal by giving a delimiter“ <”.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-mentioned embodiments, but includes various embodiments according to the principle of the present invention. For example, FIG. 2 shows a list structure linked by a pointer as a suitable example of the data storage structure in the logical connection information sorting storage unit, but the present invention is limited only to this form of data storage structure. is not.

[0067]

As described above, according to the present invention,
The logical connection information of the circuit diagram to be generated is sorted and stored in advance by the characters that make up the signal name, and the connection information of the bundled signal or the single signal is extracted from that information, so the circuit generation processing time can be shortened. It has the effect of being able to.

Further, in the present invention, since the bundle signal is recognized by the signal name, the signal groups for connecting the symbol groups which cannot be set as the bundle symbol because the kinds of the symbols are not the same are collectively bundled as a bundle signal. Wiring can be performed with a line and a single line, and the generated wiring is simple and easy to see.

Further, according to the data storage structure of the logical connection information sorting storage means of the present invention, the scanning of the characters of the signal name can be speeded up and the storage area can be efficiently used. Similarly, the signal name classification means in the present invention speeds up character scanning and contributes to shortening the processing time for generating a circuit diagram. Further, the single / bunch signal extracting means in the present invention recognizes a bundle signal by a signal name, and collects a signal group that connects symbol groups that cannot be set as a bundle symbol because the types of symbols are not the same as a bundle signal. In addition to enabling the bundled signal to be extracted as a bundled signal, the bundled signal can be extracted at high speed, and the bundled signal can be extracted based on a predetermined delimiter other than numbers, increasing the selectivity of signal names in the circuit diagram. Make the circuit diagram easy to see.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a data storage structure in a logical connection information sorting storage unit 131 according to the first embodiment of this invention.

FIG. 3 is a signal name classification unit 12 according to the first embodiment of the present invention.
3 is a flowchart showing the operation of 1.

FIG. 4 is a flowchart showing an operation of a single / bundle signal extraction unit 122 according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of a circuit.

6 is a diagram showing logical connection information of the circuit of FIG.

7 is a diagram showing a data storage structure formed in a logical connection information classification storage unit corresponding to the logical connection information shown in FIG.

FIG. 8 is a diagram showing an example of a placement and routing result of the circuit of FIG. 5 according to the first embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 10 is a flowchart showing an operation of the single / bundle signal extraction unit 122 according to the first embodiment of the present invention.

FIG. 11 is a block diagram showing an example of a conventional circuit diagram generation method.

FIG. 12 is a flowchart showing the operation of a conventional circuit diagram generation system bundle signal determination unit 1105.

[Explanation of symbols]

 11 Input device 12 Data processing device 13 Storage device 14 Output device 121 Signal name classification unit 122 Single / bundle signal extraction unit 123 Arrangement / wiring unit 131 Logical connection information classification storage unit 132 Delimiter character storage unit 21 Table entry 22 characters Index table 221 characters Index 222 Character index table Address section 23 Connection table 231 Symbol name 232 Terminal name 71 Table entry 72 Character index table 73 Connection table 1101 Logical connection information storage section 1102 Old circuit diagram information storage section 1103 Temporary bundle symbol determination section 1104 Bundle symbol determination section 1105 Bundled signal name determination unit 1106 Bundled signal name rule storage unit 1107 Placement and wiring unit

Claims (7)

[Claims] 1. In a system for generating a circuit diagram from logical connection information and circuit symbol information, signal name discriminating means for discriminating the logical connection information of a circuit diagram to be generated by characters constituting a signal name, and the signal name discrimination. Logical connection classification storage means for storing the logical connection information classified by the means, single / bundle signal extraction means for extracting a single signal or a bundle signal from the information stored in the logical connection classification storage means, A circuit diagram generating system, comprising: placement and routing means for laying out symbols on a circuit diagram based on information from the bundle signal extracting means and wiring the bundle lines and single lines. 2. The logical connection classification storage means comprises a character index table connected in a chain form, wherein the nth character of the signal name in the circuit is the nth character from the beginning.
Stored in an entry of a character index table of a chain of levels, each entry of the character index table includes a character index for storing a character and a first address part for storing an address of a character index table of a next level;
A second address part for storing the address of the connection table, and the signal of the signal name is connected in the circuit to the second address part of the entry of the character index table corresponding to the terminal character of the signal name. The circuit diagram generation system according to claim 1, wherein the circuit diagram generation system is configured to store an address of a connection table storing a symbol name and a terminal name of the circuit element. 3. The signal name classification means stores the logical connection classification memory for each of the first to nth characters of the input signal name consisting of n characters (n> 0 is an integer). When the means scans the character index table of the level corresponding to each character and detects an entry storing the same character as the character to be scanned in the character index table of the corresponding level, For the next character of the signal name, the character index table stored in the first address portion of the entry is scanned, and an entry including the same character as the scan target character is not detected in the character index table. In this case, an entry corresponding to the character of the signal name is provided in the character index table, and after scanning to the terminal character of the signal name, A connection table is created from the logical connection information corresponding to the signal name, and the address of the connection table is stored in the second address part of the entry of the character index table in which the termination character is stored. The circuit diagram generation system according to claim 1. 4. The single / bundle signal extraction means vertically scans a chain of character index tables from the head pointer in the logical connection classification storage means, and a character index is obtained by scanning each entry in the character index table. Is searched for an entry in which the character stored in is belonging to a predetermined symbol and the character index matches the symbol in the connection table in which the address is stored in the second address part of the entry, or through the chain from the entry. The connection tables that arrive are accumulated, and these are output as the bundled signal connection information to the arrangement and wiring means, and the entry whose character index is the symbol in the character index table is deleted. Item 1. A circuit diagram generation system according to item 1. 5. The single / bundle signal extraction means, if an entry in which a character stored in a character index belongs to a predetermined symbol is not detected in the character index table, in the character index table of the termination character. 2. The circuit diagram generating system according to claim 1, wherein the connection table in which the address is stored in the second address portion of the first entry of is output to the placement and wiring means as single signal connection information. 6. A storage means including a logical connection classification storage means for storing the logical connection information classified by the signal name classification means, further comprising a delimiter storage means. The circuit diagram generation system according to any one of 1. 7. The predetermined symbol is a numeral or a predetermined delimiter, and the predetermined symbol is a numeral or a predetermined delimiter.
The circuit diagram generation system according to any one of 1.