JPH07326931A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To form a demodulation circuit for easily improving reception limit performance at the time of low C/N reception at a low cost. CONSTITUTION:First IF signals frequency-converted in a down converter are supplied to an amplifier circuit 3 provided with a control terminal C1. The IF signals are supplied to the separation means 10 of a next stage, second IF signals are obtained from the first IF signals and simultaneously, I signals and Q signals are separated. The I signals and the Q signals are respectively supplied through amplitude limiting circuits 40a and 40b to A/D conversion circuits 20a and 20b. By the diodes 41a, 42a, 41b and 42b of the amplitude limiting circuits 40a and 40b, the amplitude of the signals is limited by the forward voltage of the diode. The limit value of the amplitude is set larger than the input voltage range of the A/D conversion circuits 20a and 20b so as not to influence a normal operation, the input voltage of instantaneous fluctuation is limited and an average control voltage is supplied from the signal processing circuit 30 of the next stage to the control terminal C1 of the amplifier circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication demodulation circuit, and more particularly to a satellite broadcast or CATV demodulation circuit.

[0002]

2. Description of the Related Art Conventionally, digital communication has been mainly used in satellite broadcasting or cable television.
Various types of code decoding technology, modulation / demodulation technology, synchronization technology, etc. are being studied. Examples of the modulation method include ASK, PSK, FSK, etc. Usually, from the viewpoint of multi-valued, large capacity, error characteristics, etc., a quadrature phase modulation method (hereinafter referred to as QPS)
(K) is often used. Receiving performance has been studied from the viewpoint of error characteristics, particularly carrier-to-noise ratio (hereinafter referred to as C / N ratio), and various demodulation circuits have been developed to improve receiving performance at low C / N.

FIG. 2 shows a conventional quadrature phase modulated wave (hereinafter referred to as QP
A block diagram of a demodulation circuit (referred to as SK) is shown. In the figure, reference numerals a and b are made to correspond to the portions forming the two-system circuits by using the same components.

In FIG. 2, the demodulation circuit has an input terminal 1. The QPSK modulated wave is supplied to a down converter circuit (not shown) via the input terminal 1 and converted into a first intermediate frequency signal (hereinafter referred to as a first IF). The frequency-converted first IF signal is supplied to the bandpass filter circuit 2 (hereinafter referred to as a BPF circuit) via the input terminal 1, and is further supplied from the BPF circuit 2 to the amplification circuit 3 at the next stage.

The amplifier circuit 3 has a control terminal C1 for gain control, and the first IF amplified to the branch circuit 11 at the next stage.
Providing a signal. Further, the branch circuit 11 supplies the first IF signals of equal amplitude and equal phase to the mixer circuits 12a and 12b at the next stage, respectively.

One mixer 12b is provided with a local oscillator circuit 17
From the VCO 17 is supplied to the other mixer 12a via the branch circuit 16 and the 90 ° phase shift circuit 18.
The local oscillation circuit 17 described above is a variable voltage oscillation circuit (hereinafter,
VCO) and has a control terminal C2.

The branch circuit 16 is also the branch circuit 11 described above.
Similarly, the input signal is divided into signals of equal amplitude and equal phase, and the signals are output.

The mixer circuits 12a and 12b mix the IF signal and a signal having a local oscillation frequency, and obtain a sum signal and a difference signal from both signals. Each mixer 12a, 12
The output signal of b is separated into an in-phase signal (hereinafter, I signal) and a quadrature signal (hereinafter, Q signal) based on the phase difference between the signals supplied from the VCO 17. The output signals of the mixer circuits 12a and 12b are supplied to low-pass circuits (hereinafter referred to as LPFs) 13a and 13b, respectively, and unnecessary frequency components (sum signals) are removed.
Here, the second IF signal is obtained. The signals converted from the first IF signal to the second IF signal are respectively supplied to the A / D conversion circuits 20a and 20b via the amplifier circuits 14a, 15a, 14b, 15b connected in two stages.

The branch circuits 11 and 17, the mixer circuit 12a,
12b, LPF circuits 13a and 13b, amplifier circuit 14a,
15a, 14b, 15b and the phase shift circuit 18 constitute a separating means 10 for separating an in-phase component (hereinafter, I signal) and a quadrature component (hereinafter, Q signal).

The A / D conversion circuits 20a and 20b are
The input signal is converted into digital data according to the amplitude value, and the converted signal is supplied to the signal processing circuit 30 in the next stage.

In the signal processing circuit 30, the phase error is detected by comparing the quadrature components of the I and Q signals with a phase detection circuit or the like. A voltage for VCO control is generated from this phase error using a loop filter, and this voltage is transferred from the AFC terminal to the control terminal C of the VCO.
Supply to 2. The frequency of the VCO 17 changes according to the change of the control voltage of the control terminal C2, and after the control voltage is fixed, it is fixed at a predetermined frequency. Further, the signal processing circuit 30 detects the amplitude value of the output signal and supplies the control voltage to the control terminal C1 of the amplifier circuit 3 based on this signal. Amplifier circuit 3, separating means 10 and A / D conversion circuit 20
a, 20b and the signal processing circuit 30, the AGC (Auto Ga
in Control) constitutes a loop.

Further, the QPSK data is demodulated from the PLL circuit in the signal processing circuit 30, and the demodulated data is output from the output terminal 4. The signal processing circuit 30 is composed of an integrated IC and has an I signal input terminal (I-I).
N), an input terminal for Q signal (Q-IN), an output terminal for AFC control (AFC), an output terminal for AGC control voltage (A
A plurality of input / output terminals such as GC) and demodulated data output terminal (OUT).

Next, the operation of FIG. 2 will be described. The first IF signal frequency-converted by the down converter is the BPF circuit 2
Bandwidth is limited by. This signal is supplied to the amplifier circuit 3,
Is amplified. A control voltage is supplied from the signal processing circuit 30 (AGC) to the control terminal C1 of the amplifier circuit 3 based on the amplitude information from the A / D conversion circuits 20a and 20b. Then, the gain is controlled according to the control voltage, and the amplified signal is supplied to the signal processing circuit 30 again via the A / D conversion circuits 20a and 20b based on the controlled gain. Here, the amplitude level is further detected, and a control voltage for controlling the gain of the amplifier circuit 3 is generated based on the detected signal. This control voltage is supplied to the control terminal C1 of the amplifier circuit 3. By repeating this, the AGC operation is performed so that the amplitude value of the output signal of the amplifier circuit 3 is always kept constant. That is, the amplitude of the voltage output from the amplifier circuit 3 is controlled by the control voltage, regardless of the magnitude of the signal input to the amplifier circuit 3.
Is kept constant.

Further, like the AGC, in the signal processing circuit 30, after the signal is input, the VCO1 is used in the PLL circuit.
7 generates a control voltage to be supplied to the control terminal C2 of 7,
For both the PLL loop and AGC loop,
Reach steady state. After reaching the steady state, the I signal and the Q signal synchronized with the phase of the carrier wave are obtained, and a predetermined modulation signal is demodulated in the signal processing circuit 30 from these signals.

In general, the stability of the PLL loop is determined by the loop filter in the signal processing circuit 30 and the constant of the VCO, similarly to the response characteristic of the AGC loop described above. In such a circuit, as a measure for improving the reception performance at low C / N, the filter characteristic of the demodulation circuit is made narrow in the narrow band or in the cutoff region. That is, the noise of the unnecessary frequency component is removed by the narrow band filter circuit 2 which passes only the frequency component necessary for the demodulated data. In particular, when transmitting in another mode or another channel, the required band becomes narrower, so using the narrow band filter circuit 2 is advantageous for suppressing noise. Further, when there is another modulation signal or the like in the adjacent frequency or when the degree of separation of the sum difference signal is required, it is advantageous to use the filter circuits 2 and 13 having a steep cutoff characteristic in order to suppress noise. Is.

However, if the band is too narrow,
The frequency component of the demodulated data is also cut off like noise, and the error rate of the reproduced data becomes large. Further, in the case of narrowing the band or making the characteristics of the cutoff region steep, it is necessary to use a component with a high Q value, which is not only expensive, but also the drawback that the circuit becomes large when a multistage filter circuit is configured. there were.

Therefore, a closed loop circuit (AGC, AF
C, PLL circuit (not shown)), in particular, a method of setting constants such as loop gain and loop filter of the PLL circuit to appropriate values.

However, when observing the characteristics of the demodulation circuit which has been improved with an oscilloscope, the waveform of the input part of the A / D conversion circuit 20 at the time of low C / N transmission is high C / N due to the influence of noise. It is understood that the waveform has an amplitude value nearly double that of the above, and the effect is not sufficient to improve the marginal reception performance at low C / N. That is, when the amplitude value is detected by signal processing using the signal supplied from the A / D conversion circuit when the C / N is low, erroneous signals increase due to noise components, and the control to the amplification circuit 3 is properly performed. There was a problem that I wasn't told.

[0019]

As described above, as the input signal to the demodulation circuit becomes smaller, the gain of the amplification circuit automatically increases, so that the noise output increases, and as the signal approaches the noise level, that is, the low C There was a problem that the reception performance deteriorates when / N.

Therefore, the present invention has been made in view of the above problems.
The purpose is to easily and inexpensively improve the reception limit performance during low C / N reception.

[0021]

A demodulation circuit according to the present invention according to claim 1 is provided with a control terminal, is supplied with a phase-modulated carrier having in-phase and quadrature components orthogonal to each other, and supplies this signal to the control terminal. Amplification means for amplifying in accordance with a predetermined control voltage, separation means for separating the quadrature component and the in-phase component of the phase modulated wave from the signal from the variable gain amplifier circuit, and the signal from the separation means is supplied. Analog / digital conversion means for converting the separated signals into digital signals corresponding to the respective amplitude values, and the analog / digital conversion means.
Signal processing means for supplying to the control terminal a control voltage for automatically controlling the gain of the amplifying means based on a signal from the digital converting means, and the separating means and the analog / digital converting means. An amplitude limiting circuit is provided between them, for instantaneous fluctuation of the output signal from the separating means,
It is characterized in that the response of the control voltage supplied from the signal processing means to the amplification means is made slow.

[0022]

In the present invention, the provision of the amplitude limiting circuit makes it possible to suppress noise with large amplitude, particularly impulse noise. Further, the excessive input of the signal level is eliminated, and the overload of the amplifier circuit and the like can be prevented.

[0023]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the demodulation circuit of the present invention. The same components as those in FIG. 2 are designated by the same reference numerals for description. As in FIG. 2, the same circuits of two systems of I signal and Q signal are represented by the reference numerals a and b.

The circuit structure is the same as that of FIG. 2 except that amplitude limiting circuits 40a and 40b are provided between the amplifier circuits 14a and 15a, 14b and 15b, respectively. The amplitude limiting circuits 40a and 40b each include a pair of diodes 41a.
And 42a, 41b and 42b. Of these amplitude limiting circuits 40a and 40b, the cathode of the diode 41a that constitutes one of the amplitude limiting circuits 40a is connected to the signal line between the amplifier circuit 14a and the amplifier circuit 15a, and the anode is connected to the reference potential. The other diode 42
The cathode of a is connected to the reference potential, and the anode is connected to the signal line between the amplifier circuit 14a and the amplifier circuit 15a, respectively. The forward voltage of these diodes sets the amplitude limit values of different polarities.
Further, the other amplitude limiting circuit 40b is similarly configured, and is composed of the diode 41b and the diode 42b.
The signal amplitude is limited.

Next, the operation of FIG. 1 will be described. Since the same operation is performed in both the I signal and Q signal systems, only the Q signal system (corresponding to the symbol a) will be used for the sake of simplicity for the sake of simplicity.

The forward voltage of the diodes 41a and 42a is VF. For example, if VF is 0.7V, the signal line
When a voltage of 0.7 V or more is applied, one of the diodes 42a becomes conductive, and the voltage value of the signal is fixed to the diode saturation voltage value of 0.7 V. When a voltage of -0.7V or less is applied to the signal line, this time the other diode 41a is turned on.
Is conducted, and the voltage value of the signal is fixed to -0.7V by the diode. Therefore, the voltage within ± 0.7 V is supplied to the A / D conversion circuit 20a as it is, but when the voltage exceeds it, the voltage remains fixed at the voltage value of ± 0.7 V.

Therefore, when the amplitude of the Q signal supplied from the amplifier circuit 14a exceeds 0.7 V, the amplitude is limited here. Further, since the amplitude limiting circuit 40b operates similarly for the I signal, the amplitude of both the I and Q signals will not exceed ± 0.7V. By doing so, the amplitude limiting circuit operates and the signal having a constant amplitude value is input to the A / D conversion circuit 20a in response to instantaneous fluctuation or excessive input. Therefore, when generating the control signal after detecting this signal,
An erroneous control voltage is not applied to the amplifier circuit in response to an instantaneous voltage or noise component, and only a normal signal can be favorably amplified and a stable AGC loop can be constructed.

That is, the following values of the amplitude limiting circuits 40a and 40b slow the tracking characteristic of the AGC loop due to the instantaneous variation (input voltage variation component of 0.7 V or more), and the control voltage to the amplification circuit 3 is averaged. Can be added.

Normally, a signal having an amplitude of ± 0.5 V from the positive polarity side peak to the negative polarity side peak is output from the amplifier circuits 14a and 14b as a normal signal output signal, and the amplitude limiting circuit 40a. And 40b have no effect.

With this structure, low C /
Stable AGC loop operation is guaranteed even during N hours.
The loop can be prevented from following the noise component, and an appropriate control voltage can always be supplied to the amplifier circuit 3. As a result of experiments, the demodulation circuit according to the present embodiment shows that the C / N ratio
An improvement effect of 1 to 2 dB was obtained.

[0031]

As described above, according to the present invention, the following effects can be obtained.

At low C / N, the amplitude limiting circuit can remove the amplitude which is instantaneously changed by the noise component, so that the AGC loop can be controlled on average and the stability is increased.

Further, it becomes possible to improve the reception limit performance without narrowing the band of the filter during multimode and multichannel transmission.

Further, it serves as a protection circuit for the input voltage range of the A / D conversion circuit, and with respect to the minimum input voltage at low C / N,
Since the output voltage is not set to a voltage value outside the pull-in range and the output voltage operates within a fixed range, the pull-in time of the AGC loop can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a demodulation circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional demodulation circuit.

[Explanation of symbols]

 3 ... Gain variable amplification circuit (amplification means) 10 ... Separation means 30 ... Signal processing circuit 40a, 40b ... Amplitude limiting circuit

Claims (1)

[Claims] 1. A phase-modulated carrier having a control terminal and having in-phase and quadrature components orthogonal to each other is supplied, and amplification means for amplifying this signal with a gain according to a predetermined control voltage is supplied from the amplification means. Separating means for separating the quadrature component and the in-phase component from the phase-modulated carrier wave, and an analog / digital converting means for supplying the signal from the separating means and converting the separated signals into digital signals corresponding to the respective amplitude values. Signal processing means for supplying a control voltage for automatically controlling the gain of the amplifying means to the control terminal based on amplitude information from the analog / digital converting means, the separating means and the analog / digital converter. An amplitude limiting circuit is provided between the digital converting means, and the signal processing circuit supplies the instantaneous variation of the output signal from the separating means to the amplifying means. A demodulation circuit characterized by slowing the response of the control voltage.