JPH07322200A - Data output device - Google Patents

Abstract

PURPOSE:To miniaturize a device, to reduce cost and to shorten the delay time for outputting correction data. CONSTITUTION:By a judgment device 16, the image data later than the data of a present frame by prescribed time is made to be outputted from a data transfer circuit 12, corresponding to the defect of the data reproduced and outputted by the disks such as the optical magnetic disk and hard disk, etc., that a drive 11 incorporates and the image data is made to be supplied to an adder 21 via a buffer memory 13. The image data delayed by a prescribed number of line by the FIFO memories 31 to 33 of a storage circuit 15 is selected by a selector 23 and the data is outputted to the adder 21. In the adder 21, the average value of the both inputs is made to be calculated. A selector 22 selects either one of the output of the buffer memory 13, the output of the adder 21 or the output of the selector 23 and outputs it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for reproducing image data recorded on a recording medium such as a disc, and correcting and outputting a defect in the reproduced data when the reproduced data is present. Data output device.

[0002]

2. Description of the Related Art FIG. 8 shows an example of the configuration of a conventional data output device. The drive 1 has a built-in magneto-optical disk, for example, and is adapted to record or reproduce digital image data therein. In the reproduction mode, the drive 1 reproduces and outputs the image data recorded on the magneto-optical disk. This image data is directly supplied to the adder 4, and after being delayed by 1 frame each by the delay circuit 2 and the delay circuit 3 (after being delayed by 2 frames in total), is supplied to the adder 4. To be done.
The adder 4 calculates the average value of the input image data,
The calculation result is output to the selector 5.

The selector 5 is also supplied with image data output by the delay circuit 2 and delayed by one frame. The selector 5 selects and outputs the image data output by the delay circuit 2 when the data input from the drive 1 has no defect. If there is a defect in the image data input from the drive 1, the adder 4
Select the output of and output. As a result, instead of the image data having a defect, the average value of the image data one frame before and the image data one frame later is output as the correction data.

In this way, even if the image data reproduced from the magneto-optical disk has a defect such as a dropout, the defect can be made inconspicuous and the deterioration of the image quality can be prevented.

Such correction is not limited to the case where there is a defect in the reproduced data, but for example, the processing time for decoding the image data reproduced from the magneto-optical disk becomes longer for some reason, and the reproduced video rate is increased. It is also done when it is not possible to make it in time.

[0006]

In the conventional data output device, it is necessary to store the image data for two frames in the delay circuit 2 and the delay circuit 3 as described above.
Since it is necessary to use a frame memory or the like as the delay circuits 2 and 3, there is a problem that not only the device becomes large but also the cost becomes high. Further, not all the data is supplied immediately to execute the calculation for correction, so a relatively long delay time is required before image data is output, as compared with a system that does not perform correction calculation. There were challenges.

The present invention has been made in view of such a situation, and it is possible to reduce the size and cost of the apparatus and to shorten the delay time. .

[0008]

A data output device of the present invention comprises a storage means (for example, the storage circuit 15 in FIG. 1) for storing output data, and a substitute data selection means (for example, storage circuit 15 in FIG. 1) for selecting substitute data from input data. Data transfer circuit 1 of FIG.
2), a deciding means (for example, the deciding device 16 in FIG. 1) for deciding the correction method corresponding to the defect of the input data, and at least one of the storing means and the alternative data selecting means according to the correction method decided by the deciding means And a correction unit (for example, the correction circuit 14 in FIG. 1) that corrects the data output from the device.

In this storage means, the output data can be delayed by different times to generate a plurality of delayed data. In this case, the storage means is composed of a plurality of cascade-connected FIFO memories (for example, the FIFO memory of FIG. 1).
It can be configured by the memories 31 to 33). This FIFO memory is, for example, a first FIFO memory (for example, FI of FIG. 1) that delays and outputs data by one line.
FO memory 31) and a second F that delays and outputs the data output from the first FIFO memory by 262 lines.
An IFO memory (for example, the FIFO memory 32 of FIG. 1),
It can be configured by a third FIFO memory (for example, the FIFO memory 33 in FIG. 1) that delays the data output from the second FIFO memory by 262 lines and outputs the delayed data.

Further, the correcting means includes delay data selecting means (for example, the selector 23 in FIG. 1) for selecting a predetermined one from a plurality of delay data having different delay times.
Arithmetic means for computing correction data from the alternative data selected by the alternative data selecting means and the delay data selected by the delay data selecting means (for example, adder 21 in FIG. 1).
And the alternative data selected by the alternative data selection means,
It can be configured by the output data selection unit (for example, the selector 22 in FIG. 1) that selects and outputs either the delay data selected by the delay data selection unit or the correction data calculated by the calculation unit.

The calculating means may calculate the average value of the alternative data selected by the alternative data selecting means and the delay data selected by the delay data selecting means.

[0012]

In the data output device having the above structure, the once output data is stored in the storage circuit 15. Then, the correction data is calculated in the correction circuit 14 from the alternative data selected by the data transfer circuit 12 and the delay data delayed by the storage circuit 15 for a predetermined time. Therefore, not only can the device be downsized and the cost can be reduced, but also the delay time required for outputting the image data can be shortened.

[0013]

1 is a block diagram showing the configuration of an embodiment of a data output device of the present invention. The drive 11 has a built-in disk (not shown) such as a magneto-optical disk and a hard disk, and is configured to record or reproduce image data therein. Data transfer circuit 12
In the reproduction mode, the drive 11 is controlled to reproduce the data recorded at a predetermined position on the disc and receive the transfer. Data transfer circuit 12
Is configured to decode the image data supplied from the drive 11 and supply it to the correction circuit 14 via the buffer memory 13.

The correction circuit 14 selects one of the three inputs, outputs the selector 23, calculates the average value of the data supplied from the buffer memory 13 and the data output by the selector 23, and outputs the adder. 21 and a selector 22 for selecting and outputting any one of the output of the adder 21, the data supplied from the buffer memory 13 and the output of the selector 23.

The output of the selector 22 is supplied to a circuit (not shown) and also to the storage circuit 15 for storage. The memory circuit 15 is composed of FIFO memories 31 to 33 that are connected in cascade.

The FIFO memory 31 delays the input image data by one line (1H) and supplies it to the FIFO memory 32. The FIFO memory 32 delays the input image data by 262 lines (262H) and outputs it to the FIFO memory 33. FIFO memory 3
3 receives the input image data as 262 lines (262
The output is delayed by H).

The selector 23 of the correction circuit 14 is a FIFO.
Delay image data delayed by one line output from the memory 31, total 263H output from the FIFO memory 32
Either the delayed image data delayed by that amount or the delayed image data delayed by a total of 525H (one frame) output from the FIFO memory 33 is selected.

The judgment device 16 judges whether or not there is a defect in the image data reproduced and output by the drive 11, and in accordance with the judgment result, the data transfer circuit 12, the selectors 22 and 23.
Is controlled to cause the correction circuit 14 to execute correction according to a predetermined method.

Next, referring to the flowchart of FIG.
The operation will be described. When a reproduction command is input from an input unit (not shown), the determiner 16 receives the data transfer circuit 1
The drive 11 is controlled via 2 to cause the drive 11 to reproduce the image data recorded on the disc. When the drive 11 receives the input of this command, the drive 11 reproduces the image data recorded on the disc, and the data transfer circuit 1
Output to 2. The data transfer circuit 12 detects the presence or absence of a defect in the input image data and outputs the detection signal to the determiner 16. The determiner 16 determines the correction method according to the input detection signal as shown in the flowchart of FIG.

That is, first, in step S1, it is determined whether or not the data currently being reproduced is normal.
If the reproduced data is normal, the process proceeds to step S2, and the process of selecting the reproduced data is executed. That is,
The determiner 16 controls the selector 22 to select the data supplied from the buffer memory 13 as it is. This causes the buffer memory 1 to pass through the data transfer circuit 12.
The data supplied to and stored in the selector 3 is directly used in the selector 2
2 is selected and output. That is, in this case, since there is no particular defect in the reproduced data, the correction process is not performed and the reproduced data is selected and output as it is.

When it is determined in step S1 that the reproduced data is not normal, the process proceeds to step S3, and it is determined whether or not the data on the upper and lower lines of the same field is normal. That is, when the image data recorded on the disc is, for example, NTSC image data, the data of each frame is composed of the data of the odd field (first field) and the data of the even field (second field). It is configured.

If the data being reproduced is the data of the second field, as shown in FIG. 3, for example, if there is a defect in the predetermined pixel data of the second field,
Since it is determined in step S1, the pixel data A of the upper line (second field) of the pixel data,
It is determined whether or not the pixel data B on the lower line (second field) is normal.

If both the pixel data A and B are normal, the process proceeds to step S4 and the in-field spatial average correction process is executed. That is, the determiner 16 controls the data transfer circuit 12 and, via the buffer memory 13, the adder 2
1 is supplied with pixel data B which is one line after the pixel data in which the defect is found.

On the other hand, the image data output from the selector 22 is delayed by one line by the FIFO memory 31 of the storage circuit 15 and supplied to the selector 23.
The determiner 16 controls the selector 23, and the pixel data delayed by this one line, that is, the pixel data A that is one line before the defective pixel data in FIG.
Is selected and supplied to the adder 21.

The adder 21 adds A to the pixel data B supplied from the buffer memory 13 and the pixel data supplied from the selector 23, and a value of 1/2 of the sum, that is,
Calculate and output the average value. The determiner 16 is the selector 2
2 is controlled to select and output the average value data output by the adder 21. As a result, as shown in FIG. 3, the defective pixel data is interpolated by the average value ((A + B) / 2) of the pixel data A one line before and the pixel data B one line later. It was done.

If it is determined in step S3 that the upper and lower line data of the same field is not normal, that is, if it is determined that at least one of the pixel data A or B in FIG. 3 is not normal, step S5.
Then, it is determined whether or not the data on the upper and lower lines of the previous field is normal. That is, as shown in FIG.
The first before the currently reproduced second field data
It is determined whether the pixel data A of the upper line of the field and the pixel data B of the lower line of the field are normal.
When it is determined that the pixel data A and B are normal, the process proceeds to step S6, and the intra-frame spatial average correction process is executed.

That is, the judging device 16 is constituted by the data transfer circuit 12
The drive 11 to control the current pixel data 26
The pixel data A (of the first field) two lines before is reproduced and output. This pixel data A is stored in the buffer memory 13
Is supplied to the adder 21 via.

On the other hand, the determiner 16 controls the selector 23 to select the pixel data B which is 263 lines before and which is output from the FIFO memory 32, and supplies it to the adder 21. The adder 21 calculates the average value ((A + B) / 2) of the pixel data A supplied from the buffer memory 13 and the pixel data B supplied from the selector 23, and outputs it to the selector 22. The determiner 16 causes the selector 22 to select the output of the adder 21. As a result, as shown in FIG. 4, instead of the defective pixel data in the second field, the pixel data A one line above in the first field
And the data ((A + B) / 2) interpolated by the pixel data B on the lower side of one line are output.

If it is determined in step S5 that the data on the upper and lower lines of the previous field is not normal,
That is, when it is determined that at least one of the pixel data A and the pixel data B in FIG. 4 is not normal,
In step S7, it is determined whether the data on the same line in the subsequent frame is normal. That is, as shown in FIG. 5, it is determined whether or not the pixel data A ″ of the frame one frame after the pixel data A of the current frame is normal. This pixel data A ″ is not normal. If it is determined, the process proceeds to step S8, and the previous frame correction process is executed.

That is, the judging device 16 controls the selector 23 to select the pixel data A'preceding by 525 lines (one frame) output from the FIFO memory 33. The determiner 16 further controls the selector 22, and the selector 23
Selects and outputs pixel data A ′ to be selected and output.
As a result, as shown in FIG. 5, the pixel data A ′ of the previous frame is output instead of the defective pixel data A of the current frame.

In step S7, it has not been determined that the data A'on the same line in the previous frame is normal, but it has been found that at least the data A "on the same line in the subsequent frame is not normal. Therefore, the data A ″ of the subsequent frame is not used for interpolation, but the data A ′ of the previous frame is used for interpolation.

If the data A'in the previous frame is normal,
Appropriate correction is performed, and when the data A ′ of the previous frame is not normal, proper correction is not necessarily performed. However, since the data A ′ of the previous frame has been corrected by the correction circuit 14 or the correct data has been selected and output as it is as described above, the defective data may be used as it is. There is nothing.

If it is determined in step S7 that the data on the same line in the subsequent frame is normal, that is,
5, when it is determined that the pixel data A ″ is normal, the process proceeds to step S9, and it is determined whether or not the data on the same line in the previous frame is normal.
It is determined whether or not the pixel data A ′ in is normal. When it is determined that the pixel data A ′ is not normal, the process proceeds to step S10, and the post-frame correction process is executed.

That is, the judging device 16 is constituted by the data transfer circuit 12
The pixel data after 525 lines from the drive 11 is selected and output from the drive 11. Then, the selector 22 is controlled to select and output the data after 525 lines output by the data transfer circuit 12 via the buffer memory 13.

That is, in FIG. 6, in place of the defective pixel data A of the current frame, the same pixel data A ″ of the frame one frame later (this data corresponds to step S
(Determined as normal data in 7) is output as interpolation data.

If it is determined in step S9 that the data on the same line in the previous frame is normal, that is,
When it is determined that the pixel data A ′ in FIG. 5 is normal, it is determined in step S7 that the pixel data A ″ after one frame in FIG. 5 is also normal, and in this case, Go to step S11,
Time average correction processing is executed.

That is, as shown in FIG. 7, the pixel data A (pixel data A ′ in FIG. 5) one frame before the defective pixel data and the pixel data B (frame) in the frame one frame later (see FIG. The average value ((A + B) / 2) with the pixel data A ″ in 5 is calculated and output.

That is, the judging device 16 is constituted by the data transfer circuit 12
The pixel data B after one frame from the drive 11 is selected and output. This pixel data B is supplied to the adder 21 via the buffer memory 13. On the other hand, the selector 23 is controlled to select the pixel data A output by 525 lines (one frame) output from the FIFO memory 33 and supply the pixel data A to the adder 21. Adder 21
Calculates the average value of both inputs and outputs it to the selector 22. The determiner 16 controls the selector 22 to add the adder 21.
Select and output the pixel data output by.

As described above, since the data after one frame is supplied from the data transfer circuit 12 each time, the conventional delay circuit 2 in FIG. 8 is not required, and the device is downsized accordingly. Therefore, the cost can be reduced. In addition, the delay time can be shortened as compared with the conventional case.

In the above embodiments, the data transfer circuit 12 is made to supply the data via the drive 11, but the drive 11 can also be a predetermined transmission path. The buffer memory 13 can also be replaced with a transmission line.

[0041]

As described above, according to the data output device of the present invention, the output data is stored in the storage means, and is corrected from the data stored in the storage means and the alternative data selected by the alternative data selecting means. Since the data is generated, the capacity of the storage means is half that of the conventional case.
It becomes possible to As a result, not only can the device be made smaller and the cost can be reduced, but also the delay time for outputting the correction data can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data output device of the present invention.

FIG. 2 is a flowchart illustrating the operation of the embodiment of FIG.

FIG. 3 is a diagram illustrating an in-field spatial average correction process.

FIG. 4 is a diagram illustrating an intra-frame spatial average correction process.

FIG. 5 is a diagram illustrating a previous frame data correction process.

FIG. 6 is a diagram illustrating a post-frame data correction process.

FIG. 7 is a diagram illustrating a time average correction process.

FIG. 8 is a block diagram showing a configuration of an example of a conventional data output device.

[Explanation of symbols]

 1 Drive 2, 3 Delay Circuit 4 Adder 5 Selector 11 Drive 12 Data Transfer Circuit 13 Buffer Memory 14 Correction Circuit 15 Storage Circuit 16 Judgmenter 21 Adder 22, 23 Selector 31 to 33 FIFO Memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Shiotani 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (6)

[Claims] 1. A storage means for storing the output data, a substitute data selecting means for selecting substitute data from the input data, a determining means for determining a correction method corresponding to a defect in the input data, and the determining means. A data output device, comprising: a correction unit that corrects data output from at least one of the storage unit and the alternative data selection unit according to the correction method determined by. 2. The data output device according to claim 1, wherein the storage unit delays the output data by different times to generate a plurality of delayed data. 3. The data output device according to claim 2, wherein the storage means has a plurality of FIFO memories connected in cascade. 4. The first FIFO memory outputs the data delayed by one line, and the data output from the first FIFO memory.
A second FIFO memory which delays by two lines and outputs the data, and a data output from the second FIFO memory 26
4. The data output device according to claim 3, further comprising a third FIFO memory which delays by two lines and outputs. 5. The delay data selecting means for selecting a predetermined one from a plurality of the delay data having different delay times, the alternative data selected by the alternative data selecting means, and the delay. Computing means for computing the correction data from the delay data selected by the data selecting means, and the alternative data selected by the alternative data selecting means,
Delay data selected by the delay data selection means,
The data output device according to claim 2, 3 or 4, further comprising output data selection means for selecting and outputting any one of the correction data calculated by the calculation means. 6. The arithmetic unit according to claim 5, wherein the arithmetic unit calculates an average value of the alternative data selected by the alternative data selecting unit and the delay data selected by the delay data selecting unit. Data output device.