JPH07321637A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To control power supply with the output of a CMOS inverter by providing two kinds of power supplies before and after level conversion to a power source of the CMOS inverter to reduce the number of stages. CONSTITUTION:Drains of P-channel MOS transistors(TRs) PTA, PTB are connected in parallel to the source of an N-channel MOS TR NT3 in P-channel MOS TR PT3 and the N-channel MOS TR NT3 being components of a CMOS inverter. The source of the TR PTA connects to a high power source VDDA before level conversion and the source of the TR PTB is connected to a high power source VDDB for level conversion. An output terminal of an inverter INB receiving the signal of an output node DOT is connected to a gate of the TR PTB and to an input terminal of the inverter INA. The output terminal of the inverter INA is connected to the gate of the TR PTA. The power source is VDDB for both the inverters INA, INB and the base potential of the TRs, PTA, PTB uses the power source VDDB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS type level conversion circuit for converting a small input signal into a large output signal.

[0002]

2. Description of the Related Art FIG. 5 is a CMO including a level conversion circuit for interfacing from a small signal system to a large signal system.
It is a circuit diagram which shows an S output circuit. Here, the input / output amplitude of the signal is 0 to 3 V for a small signal system, and 0 to 5 V for a large signal system to be converted. The figure is divided into a level conversion circuit, a prebuffer, and a main buffer. In the level conversion circuit LVC5, the gates and sources of the P-channel MOS transistors PT1 and PT2 whose source voltage is a 5V power source (VDDB) are reversely connected to each other, and the N-channel is provided between each connection point and the ground voltage (VSS). MOS transistor NT1
, NT2 drain and source are connected. The gate of the transistor NT1 is connected to the signal input node IN, and the gate of the transistor NT2 is connected to the output terminal of the inverter IV1 of the 3V power source to which the signal of the node IN is input. Output node 53 of level conversion circuit LVC5
Is connected to the input terminal of the pre-buffer PIV of the 5V power supply. The output terminal of the pre-buffer PIV is connected to the gate of one P-channel MOS transistor MPT of the main buffer. The output node 54 of the LVC6 having the same configuration as the level conversion circuit LVC5 is connected to the input terminal of the pre-buffer NIV of the 5V power source. The output terminal of the pre-buffer NIV is connected to the gate of the other N-channel MOS transistor MNT of the main buffer. The source of the transistor MPT of the main buffer is connected to the 5V power supply VDDB, the source of the transistor MNT is connected to the ground voltage VSS, and the drain connection points of both the transistors MPT and MNT are connected to the signal output terminal OUT. 5V
The system pre-buffer and main buffer have a gate input of 5V (VGS = VGS) when the gate-source voltage is VGS and the gate-drain voltage is VDS in order to bring out sufficient characteristics.
DS = 5V) is required.

The operation of the level conversion circuit LVC5 is as follows. When the input signal changes from 0V to 3V, the transistor NT1 is turned on and the level of the node 52 is lowered to the ground level, so that the transistor PT2 is turned on and the transistor NT2 receiving the inverted signal of the input is turned off and the output node 53 becomes 5V. Conversely, the input signal is 3V
When it changes to ~ 0V, the transistor NT2 turns on,
The output node 53 falls to the ground level and the transistor PT
When 1 is turned on and transistor NT1 is turned off, the circuit is stabilized and the output node 53 becomes 0V. FIG. 6 shows an output waveform diagram in a part of the operation of the above circuit.

According to the above circuit configuration, the signal converted from the 0-3V system to the 0-5V system by the level conversion circuit is used as the input signal of the pre-buffer. According to the above configuration, four stages of gates are provided from the input to the output.

FIG. 7 is a circuit diagram of a tri-state type output circuit including level conversion from a small signal system to a large signal system. A logic circuit for creating a high impedance state is added to the configuration of FIG. It has a data pin DT and control pins TN and EN as input pins. The pins DT and TN are connected to the two input terminals of the NAND gate 71, and the output thereof is one input of the NOR gate 72. N
The pin EN is connected to the other input of the OR gate 72. N
The output of the OR gate 72 is connected to the gate of the transistor NT1 of the level conversion circuit LVC5 and also to the gate of the transistor NT2 via the inverter IV1.

The output of the NAND gate 71 is further connected to the first input terminal of a 3-input NAND gate 73. NAND
The second input end of the gate 73 is connected to the pin TN, and the third input end is connected to the output of the inverter 74 which inverts the signal of the pin EN. The output of the NAND gate 73 is connected to the gate of the transistor NT1 of the level conversion circuit LVC similar to the above, and also the transistor N1 via the inverter IV1.
Connected to the gate of T2.

In the circuit configuration of FIG. 6 described above, normal data output only needs to be under the condition of pin TN = "H" and EN = "L", and the high impedance state is TN = "L" or EN = "H". Is the condition, and at this time, the output is in the high impedance state regardless of the input.

Here, it is assumed that the input / output amplitude of a signal is 0 to 3V for a small signal system and 0 to 5V for a large signal system. TN =
Input DT is 0V to 3V in the state of "H", EN = "L"
Changes to 0V to 3V through the gate 2 stages up to the input of each level conversion circuit, and thereafter, the output changes from 0V to 5V through the gate 4 stages in the same configuration as in FIG. The same applies when the input DT changes from 3V to 0V, that is, 6 gates are required from the input to the output. When the high impedance state is set, the output of the NOR gate 72 is set to 0 as an input to the level conversion circuit.
V, the output of the NAND gate 73 becomes 3V. After that, as in the case of FIG. 5, a high impedance state is achieved through four stages of gates.

On the other hand, consider the case of an output circuit that does not perform level conversion, such as a 3V system output for a 3V system input. Such an output circuit has only two gates from the input to the output. Further, the tri-state buffer that does not perform level conversion has only four gates from the input to the output. Therefore, the circuit configuration including level conversion requires a considerably larger number of gate stages than the circuit configuration without level conversion, and the delay time increases accordingly.

[0010]

As described above, conventionally, the circuit configuration including the level conversion requires a larger number of gate stages than the circuit configuration not including the level conversion, and the delay time increases accordingly. For circuit configurations including level conversion, delay characteristics similar to those of output circuits not including level conversion are desired.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a level conversion circuit in which the delay time is reduced by reducing the number of gate stages.

[0012]

According to another aspect of the present invention, there is provided a level conversion circuit which is connected in parallel to at least two transistors having different conductivity types, which form a CMOS inverter, and a source on the power supply side of the transistors. 1
Of the first power supply path and the second power supply path for level conversion and the first and second power supply paths according to the switching of the output signal of the CMOS inverter. It is characterized in that it is provided with first and second MOS transistors provided in respective power supply paths.

[0013]

According to the present invention, the first power supply and the second power supply for level conversion are connected to the power supply source side of one CMOS type inverter, and the first and second output signals of the CMOS type inverter are utilized. Transfer control of the power supply path of the. This reduces the number of gate stages from the level conversion input to the output.

[0014]

1 is a circuit diagram showing the structure of a level conversion circuit according to an embodiment of the present invention. The common gates of the P-channel MOS transistor PT3 and the N-channel MOS transistor NT3 forming the CMOS type inverter are connected to the signal input node DIN, and the transistors PT3, N are connected.
The common drain of T3 is connected to the signal output node DOT. The source of the transistor PT3 is a P channel M
The drains of the OS transistors PTA and PTB are connected in parallel. The source of the transistor PTA is connected to the low power supply VDDA before level conversion, and the source of the transistor PTB is connected to the high power supply VDDB to be level converted. The source of the transistor NT3 is connected to the ground voltage Vss.

The inverter IVB for inputting the signal of the output node DOT has its output end connected to the gate of the transistor PTB and is connected to the input end of the inverter IVA. The output terminal of the inverter IVA is a transistor PT
It is connected to the gate of A. Inverter IVA, IV
The power source for both B is VDDB, and the transistors PTA and PTB are used.
The power source for both substrate potentials is VDDB.

In the circuit configured as described above, the input / output amplitude of a signal is set to 0 to 3 V for a small signal system and 0 to 5 V for a large signal system for conversion. This reduces the low power supply VDDA to 3
The operation will be described assuming that the high power supply VDDB is 5V.

When the level of the input DIN changes from 3V to 0V, the transistor PT3 is turned on and the transistor N is turned on.
T3 turns off. At this time, since the transistor PTB is in the off state and the transistor PTA is in the on state, 3V is obtained at the output node DOT. 3V of the output node OUT is input to the inverter IVB to turn on the N-channel MOS transistor inside IVB. IV
Since the power source of the P-channel MOS transistor in B is also 5V, it turns on with a weak driving force.
The output of B approaches 0V.

The output of the inverter IVB is the transistor P.
Turn on TB and turn on inverter IVA to 5V
Is output and the transistor PTA is turned off. As a result, the source voltage of the transistor PT3 changes from 3V to 5V.
Will change to. Therefore, the output node DOT approaches 5V, and the output of the inverter IVB receiving this output signal is surely set to 0V. As a result, the input node D
The output node DOT becomes 5V with respect to 0V of IN.

On the contrary, the level of the input DIN is 0V to 3V.
, The gate-source voltage (VGS) of the transistor PT3 is 2V, the driving force is reduced, the transistor NT3 is turned on, and the output node DOT becomes 0V. The output of the inverter IVB receiving this 0V is 5
V, the inverter IVA outputs 0V. This allows
The transistor PTB is turned off, the transistor PTA is turned on, the source voltage of the transistor PT3 is changed from 5V to 3V, and VGS of the transistor PT3 is changed to 0V, so that the transistor PT3 is completely turned off. Eventually, the output node DOT becomes 0V with respect to the input node DIN of 3V.

According to the above configuration, the output signal is inverted with respect to the input signal, but it is possible to use only one gate as compared with the conventional level conversion circuit which requires two gates. In addition, when "H" level is output,
In the above, the output is in two stages from 3V output to 5V.

FIG. 2 shows a first application example of the present invention, which corresponds to C in FIG.
It is a circuit diagram in which the present invention is applied to a MOS output circuit. The level conversion circuit (LVC1, LVC2; the same configuration) of the present invention and the main buffer (MPT, MNT). The pre-buffer is not necessary due to the logical configuration. The input / output amplitude of a signal is 0 to 3V for a small signal system and 0 to 5V for a large converted signal system. Therefore, the low power supply VDDA is 3V and the high power supply VDDB is 5V. Transistor MP
T and MNT exhibit a sufficient driving force under the condition of VGS = VDS = 5V (VDS is the drain-source voltage), and VGS = V
It turns off under the condition of DS = 0V. Input I in FIG. 2 in FIG. 3
The output waveform diagram when N changes to 0V-3V is shown. The circuit operation will be described with reference to these.

When the input IN changes from 0V to 3V, the gate of the transistor MPT and the gate of the transistor MNT rapidly change from 5V to 0V. As a result, the transistor MPT is turned on, the transistor MNT is turned off, and 5 V is output to the output OUT (FIG. 3).

When the input IN changes from 3V to 0V, the gates of the transistors MPT and MNT rapidly rise from 0V to 3V. Therefore, VGS of transistor MPT is 5
Since the driving force is lowered due to the change from V to 2V, VGS of the transistor MNT is changed from 0V to 3V and the driving force is obtained, so that the output node OUT starts to drop from 5V to 0V.
During this time, the gates of the transistors MPT and MNT (that is, the outputs DOT1 and 2 of the level conversion circuit) are quickly set to 3V.
Changes from 5V to 5V, and the VGS of the transistor MPT is 2
It changes from V to 0V and turns off. Also, the transistor M
The VGS of NT changes from 3V to 5V, a sufficient driving force is obtained, and the output node OUT becomes 0V. With such a configuration, the number of gate stages is only two, and the speedup between input and output can be achieved as compared with the conventional four gate stages.

FIG. 4 is a second application example of the present invention and is a circuit diagram in which the present invention is applied to a tri-state type output circuit including a level conversion circuit. A logic circuit that creates a high impedance state is configured as follows. Data pins DT, control pins TN, EN as input pins
Have. The output terminals of the inverter 11 that outputs the inverted signals of the pins DT, TN, and the pin EN are each a 3-input NAN.
It is connected to each input terminal of the D gate 12, and its output is connected to the input node DIN1 of the level conversion circuit LVC1.

Further, the output terminals of the inverter 13 for outputting the inverted signals of the pins DT, EN and the pin TN are respectively connected to the respective input terminals of the 3-input NOR gate 14, and the output thereof is level-converted as in the above-mentioned circuit LVC1. It is connected to the input end of the circuit LVC2.

Output node DO of the level conversion circuit LVC1
T1 is connected to the input terminal of the pre-buffer PIV, and the output of the pre-buffer PIV is connected to the gate of the P-channel MOS transistor MPT which constitutes the main buffer. The output node DOT2 of the level conversion circuit LVC2 is connected to the input terminal of the prebuffer NIV, and
The output of IV is an N channel MO that constitutes the main buffer.
It is connected to the gate of the S transistor MNT. The common drain of the transistors MPT and MNT is the output OUT
Becomes

Also in this case, a signal system having a small signal input / output amplitude is 0 to 3 V, and a large signal system to be converted has a signal range of 0 to 5 V.
As a result, the low power supply VDDA is 3V and the high power supply VDDB is
The operation will be described with 5V.

Normal operation is performed under the condition that the pin TN is at "H" level and EN is at "L" level. When the input pin DT changes from 0V to 3V, NAND gate 12 and NOR gate
Both 14 outputs change from 3V to 0V. This is converted into 5V by the level conversion circuits LVC1 and 2, and the transistor MPT is turned on through the prebuffers PIV and NIV.
MNT turns off. Therefore, the output OUT becomes 5V.
Conversely, if the pin DT changes from 3V to 0V, the NAND
The outputs of the gate 12 and the NOR gate 14 both change from 0V to 3V. This is converted to 0V by the level conversion circuits LVC1 and 2, and the transistor MPT is turned off and the MNT is turned on through the prebuffers PIV and NIV. Therefore, the output OUT becomes 0V.

On the other hand, when the pin TN is at "L" level or the pin EN is at "H" level, it is a condition of a high impedance state. The NAND gate 12 becomes 3V and the output of the NOR gate 14 becomes 0V without depending on the signal to the input pin DT, and the level conversion circuit LVC1 outputs 0V,
Converted to 5V by LVC2. The respective outputs are respectively inverted by passing through the pre-buffers PIV and NIV, the transistors MPT and MNT of the main buffer are both turned off, and the high impedance state is set.

According to the circuit having the above configuration, the number of gate stages from input to output is four. Compared to the configuration that requires 6 stages of the conventional circuit, the number of gates is reduced by 2 stages, so that it is easy to realize high speed. In the above-described embodiment, the level conversion is set to 0 to 3 V for a signal system having a small input / output amplitude, and set to 0 to 5 V for a large signal system to be converted, but it is applicable to various level conversions. For example, the upper limit voltage of the small signal system is 2.5 to 3.6 V, the upper limit voltage of the large signal system to be converted is 4.5 to 5.5 V, or the upper limit voltage of the small signal system is 1.5 to 2.5 V, the upper limit voltage of the large signal system to be converted is 4.5 to 5.5 V, or the upper limit voltage of the small signal system is 1.5 to 2.5 V, the upper limit voltage of the large signal system to be converted Is 2.5 to 3.6 V or the like.

[0031]

As described above, according to the present invention,
Two types of power supplies before and after level conversion are provided on the power source side of the CMOS type inverter, and the power supply is controlled by the output of the CMOS type inverter. Therefore, the number of gate stages is reduced and the operation speed is increased. It is possible to provide a level conversion circuit that can achieve the above.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a configuration according to a first application example of the present invention.

FIG. 3 is an output waveform diagram showing a circuit operation of a part of FIG.

FIG. 4 is a circuit diagram of a configuration according to a second application example of the present invention.

FIG. 5 is a circuit diagram showing a CMOS output circuit including a conventional level conversion circuit.

FIG. 6 is an output waveform diagram showing a circuit operation of a part of FIG.

FIG. 7 is a circuit diagram showing a conventional tri-state type output circuit including level conversion.

[Explanation of symbols]

PT3, PTA ... P-channel MOS transistor, NT
3, PTB ... N-channel MOS transistor, IVA,
IVB ... Inverter.

Claims (2)

[Claims] 1. A at least two transistors of different conductivity types forming a CMOS inverter, a supply path of a first power supply connected in parallel to a power supply side source of the transistors, and a level conversion first transistor. Two
And a first power supply path provided to each of the power supply paths so that transfer control of each of the first and second power supply paths is performed in accordance with switching of the output signal of the CMOS inverter. And a second MOS transistor. 2. A first inverter for inputting an output signal of the CMOS type inverter and controlling the gate of the second MOS transistor at the output, and an output signal of the first inverter for inputting the output signal at the output. A second inverter for controlling the gate of the first MOS transistor,
The power supply for the first and second inverters and the first MO
The level conversion circuit according to claim 1, wherein the second power supply is applied as a substrate potential of the S transistor.