JPH07319772A - Address conversion controller - Google Patents

Abstract

PURPOSE:To improve the precision of discrimination by comparing a pair of a read-out actual address and a logical address used for access with a pair of an actual address for partial purge and a logical address, which is made correspond to the actual address, to discriminate whether it is the true partial purge object or not. CONSTITUTION:A logical address 101 of a read-out entry and upper bits of the logical address of an address conversion request set to a TLB address register 5 are compared with each other by a comparison circuit 6, and an actual address 102 of the read-out entry and the actual address held in a purge address register 2 are compared with each other by a comparison circuit 7. The logical address of the address conversion request held in the TLB address register 5 and the logical address held in a logical address register 3 are compared with each other by a comparison circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation control device in a virtual memory type information processing device having an address translation buffer for translating a logical address to a real address at high speed. The present invention relates to an address translation control device suitable for a partial purge process of an address translation buffer (which means partial erasing of stored information or partial resetting of the initial state).

[0002]

2. Description of the Related Art Conventionally, in a virtual memory type information processing apparatus, as shown in FIG. 2, in the course of executing a program, the position of each instruction and the data required by each instruction is first determined by a virtual address 21 (virtual It indicates an address on the storage device 20: generally called a logical address).

Therefore, in order to retrieve the necessary instructions and data, it is necessary to convert this logical address 21 into a real address 23 on the real storage device 22 (indicating an address on the real storage device 22). This is called address translation, and the hardware mechanism for this translation is called the dynamic address translation mechanism 24.

When performing this DAT, the virtual storage device 20
An address conversion table 25 (Ad that associates the upper logical address 21 with the real address 23 on the real storage device 22).
dress Translation Table).

However, if the dynamic address translation is performed using the address translation table 25 every time there is an address translation request, the processing cannot be performed at high speed. Therefore, a “pair” of the real address 23 and the corresponding logical address 21 obtained by the dynamic address translation using the address translation table 25 in the past is held in a buffer, and when the address translation request is made, the buffer is stored. Is accessed, the real address 23 is directly obtained from the corresponding logical address to perform the address conversion.

This buffer is the so-called address conversion buffer 26. By using this address translation buffer 26, the logical address 21 of the address translation request
If is registered in the address translation buffer 26, the real address 23 can be directly obtained without performing the dynamic address translation, so that the address translation can be performed at high speed.

In the virtual memory system, the address space that can be specified by the logical address 21 is generally wider than the address space that can be specified by the real address 23.
When the real address 23 assigned to a certain logical address is no longer used, the address conversion table 25 may be rewritten so as to be assigned to another logical address 21.

With the rewriting of the address conversion table 25, the address conversion table 25 before being rewritten
Information in an entry (here, meaning of an area for storing data or storing data, etc.) that holds a “pair” of a logical address 21 and a real address 23 associated with each other, that is, It is necessary to cancel the "pair" of the past logical address 21 and real address 23.

This is a partial purge of the address translation buffer 26 (erasing the information in the entry). This partial purge is performed by searching the address translation buffer 26 one by one, but during the processing, address translation cannot be performed, and there is a problem that the efficiency of use of the address translation buffer 26 decreases. .

As a solution to this, for example, Japanese Patent Laid-Open No. Sho 60
As disclosed in JP-A-142451, a memory array for partial purge is provided in addition to the address translation buffer, and the address translation is performed unless the real address read from the address translation buffer matches the real address to be canceled. A technique is known in which the conversion buffer is used and the partial purge is independently performed by the memory array.

According to this technique, the address conversion can be performed even during the partial purge, and by comparing the real address read from the address translation buffer with the real address to be canceled, the partial purge target is obtained. It is also possible to prevent the entry of is accidentally used.

[0012]

However, in the technique disclosed in Japanese Patent Laid-Open No. 60-142451, the real address read from the address translation buffer is canceled as the condition for determining the target of partial purge. Only the match with the real address should be considered.

Therefore, by rewriting the address conversion table, the "pair" of the real address to be canceled and the logical address newly associated with the real address becomes
When the real address to be canceled is designated as a partial purge target when registered in the address translation buffer by the dynamic address translation, the “pair” is specified.
There is a problem that an entry including is also determined to be a partial purge target and is partially purged, that is, erased.

Therefore, there is a drawback in that unnecessary dynamic address translation is repeated and the address translation processing performance is deteriorated by erasing an entry that is originally not required to be partially purged.

An object of the present invention is to provide an address translation control device which improves the accuracy of determination of a partial purge target entry in address translation during partial purge.

[0016]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, an address conversion table for associating a logical address on the virtual storage device with a real address on the real storage device, the real address previously converted using the address conversion table, and the logic corresponding to the real address. In an address translation control device provided with an address translation buffer having a plurality of entries holding addresses as "pairs", when performing partial purging of the address translation buffer, the address translation buffer is set to the logical translation before the partial purge. A “pair” of the real address obtained by accessing the address and the logical address used for the access, and a “pair” of the real address given for performing the partial purge and the logical address corresponding to the real address. Based on the comparison result of the comparison means and the comparison means, In which the holding within a few entries "pair" with the logical address corresponding to the real address and a determining means for determining whether the partial purge target.

[0018]

According to the means, when an address translation request is made during the partial purge, the address translation buffer is accessed by the request, the real address corresponding to the logical address of the request is read, and the read real address is read. And the logical address used for the access
And a "pair" of a real address given for performing the partial purge and a logical address newly associated with the real address, and based on the comparison result, is the true partial purge target? I will judge whether or not
Even if an address conversion request is issued during the partial purge, the determination accuracy of the partial purge target entry can be improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a partial block diagram showing a partial configuration of an embodiment of the address translation control device according to the present invention.

In FIG. 1, 1 is a logical address 101.
And the real address 10 corresponding to the logical address 101
An address translation buffer that holds a plurality of entries including 2 and 2 is a purge address register that holds a real address to be canceled.

3 is a logical address register for holding a rewritten logical address of an address conversion table (not shown) corresponding to the real address to be canceled, 4
Is a selector for selecting a logical address for accessing the address translation buffer 1 and 5 is an address translation buffer address register (hereinafter, TLB address register 5 for holding a logical address for accessing the address translation buffer 1).
That is).

Reference numeral 6 is a comparison circuit for comparing the logical address 101 of the entry read from the address translation buffer 1 with a part of the logical address held in the TLB address register 5.

Reference numeral 7 is a comparison circuit for comparing the real address 102 of the entry read from the address translation buffer 1 with the real address to be canceled held in the purge address register 2, and 8 is a logic held in the TLB address register 5. A comparison circuit for comparing the address with the logical address held in the logical address register 3, 9 is a not gate, 10 is a NAND gate, 11 is an AND gate, 12
Is a dynamic address translation circuit.

Reference numeral 13 is a translation address register for holding the real address obtained by the dynamic address translation circuit 12,
Reference numeral 14 is a comparison circuit for comparing the real address held in the purge address register 2 with the real address held in the translated address register 13, and 15 is a real address for accessing a real storage device (not shown). A selector for selecting 16 is a memory address register for holding a real address for accessing a real storage device (not shown).

Reference numeral 110 is a signal line for giving a logical address of an address translation request, and 120 is a TL to be partially purged.
It is a signal line for giving a B address.

The operation of the address translation control device of this embodiment will be described below with reference to FIG.

First, the operation of address conversion when the partial purge is not performed will be described.

First, when an address translation request occurs, the logical address of the address translation request is given by the signal line 110 and set in the TLB address register 5 via the selector 4.

Then, the address translation buffer 1 is accessed by the middle bit of the logical address set in the TLB address register 5, and the corresponding entry is read.

Logical address 101 of the read entry
And the upper bits of the logical address set in the TLB address register 5 are compared by the comparison circuit 6.

Here, the logical address 101 of the entry includes a valid flag indicating whether the entry is “valid” or “invalid”, and the TLBC output from the comparison circuit 6 is included.
The valid flag of the OIN signal 150 is “1”,
Moreover, when the other part of the logical address 101 of the entry other than the valid flag and the upper bits of the logical address set in the TLB address register 5 match, the value becomes "1".

On the other hand, when the partial purge is not performed, the PPMOD signal 153, which is a signal indicating that the partial purge is being performed, is "0". Therefore, the value of the TLBCOIN signal 150 is "valid" by the NAND gate 10. The COINV signal 154 indicating that is "1".

Therefore, in the address conversion in the case where the partial purge is not performed, it is judged whether or not the logical address of the address conversion request exists in the address conversion buffer 1 by the TLBCOIN signal 150 output from the comparison circuit 6.
Will be decided only by.

If the TLBCOIN signal 150 is "1".
If so, the TLBHIT signal 155 indicating that the logical address of the address translation request exists in the address translation buffer 1 by the AND gate 11 becomes “1”, and the real address 102 read from the address translation buffer 1
To which the lower bit of the logical address set in the TLB address register 5 is added as the real address,
The data is set in the memory address register 16 via the selector 15 and an actual storage device (not shown) is accessed.

If the TLBCOIN signal 150 is "0".
Then, the TLBHIT signal 155 is "0", that is, the logical address of the address translation request does not exist in the address translation buffer 1, and dynamic address translation using an address translation table (not shown) is performed. Will be done and the real address will be sought.

The real address obtained by the dynamic address translation is stored in the translation address register 13.

Then, the real address stored in the translated address register 13 is set in the memory address register 16 through the selector 15, and the real memory device (not shown) is accessed.

The real address obtained by the dynamic address translation and the logical address corresponding to the real address are sent to the address translation buffer 1 and registered in the address translation buffer 1 as a new entry.

Next, the operation when an address translation request is made during the partial purge will be described.

A preset real address to be canceled is set in the purge address register 2 and the PPMOD signal 153 indicating that the partial purge is in progress is set to "1" to start the partial purge.

Here, when an address translation request occurs,
The logical address of the address conversion request is given to the signal line 110 and set in the TLB address register 5 via the selector 4.

Then, the address translation buffer 1 is accessed by the middle bit of the logical address set in the TLB address register 5, and the corresponding entry is read.

Logical address 10 of the read entry
1 and the upper bit of the logical address of the address translation request set in the TLB address register 5
Compared with.

The comparison circuit 7 compares the real address 102 of the read entry with the real address held in the purge address register 2.

The RACOIN signal 151 which is the output of the comparison circuit 7 becomes "1" when the real address 102 of the read entry and the real address held in the purge address register 2 match.

The comparison circuit 8 compares the logical address of the address conversion request held in the TLB address register 5 with the logical address held in the logical address register 3.

The logical address held in the logical address register 3 is a logical address newly associated with the real address to be canceled by rewriting the address conversion table (not shown). If the logical address held in 3 and the logical address of the address translation request match, even if the real address held in the purge address register 2 and the real address 102 read from the address translation buffer 1 match, The entry read from the address translation buffer 1 is excluded from the partial purge target.

The logical address held in the logical address register 3 is the one before the address translation when the real address is obtained by the dynamic address translation and the real address matches the real address held in the purge address register 2. It is obtained by obtaining the logical address 101.

That is, the setting of the logical address in the logical address register 3 is performed by the following operation.

First, when the dynamic address translation is activated,
The dynamic address translation circuit 12 receives the values of the upper and middle bits of the logical address set in the TLB address register 5, and uses the address translation table (not shown) for the real address corresponding to the logical address. Ask for.

The calculated real address is stored in the conversion address register 13 and compared with the real address held in the purge address register 2 by the comparison circuit 14.

In the comparison circuit 14, the PPMOD signal 153, which is a signal indicating that the partial purge is being performed, is "1".
If the real address held in the translation address register 13 and the real address held in the purge address register 2 match, the comparison circuit 1 concerned
The TACOIN signal 160, which is the output of No. 4, is set to "1".

When the TACOIN signal 160 is "1", the logical address that activated the dynamic address translation is set in the logical address register 3, and the valid flag of the logical address register 3 is set to "1".

As can be seen from the above description, until the entry indicated by the logical address newly associated with the real address to be canceled is accessed by rewriting the address translation table (not shown), The logical address register 3 has a valid logical address 101
Is never retained.

Therefore, the logical address set in the logical address register 3 is also "valid" or "invalid" like the logical address 101 of the entry of the address translation buffer 1. Has a valid flag indicating.

The comparison circuit 8 has the logical flag set in the logical address register 3 with a valid flag of "1" and the logical address of the address translation request held in the TLB address register 5 and the logical address register 3. If the held logical address matches,
The LACOIN signal 152 output from the comparison circuit 8 is set to "1".

The NAND gate 10 outputs the RACOIN signal 151, which is the output of the comparison circuit 7, the inverted signal 156 of the LACOIN signal 152, which is the output of the comparison circuit 8, and P.
A COINV signal 154 is generated from the PMOD signal 153.

The generated COINV signal 154 is
When the value of the TLBCOIN signal 150 indicates "valid" and the entry read from the address translation buffer 1 during the partial purge is the target of the partial purge, the COINV signal 154 is set to "0" and the TLBCOI is set.
The value of the N signal 150 is set to “invalid”.

That is, in the address conversion during the partial purge, whether the logical address of the address conversion request exists in the address conversion buffer 1 is basically determined by the TLBCOIN signal 150 which is the output of the comparison circuit 6. However, the logical address of the address translation request exists in the address translation buffer 1 (that is, TLBCO
Even if the IN signal 150 is "1"), if it is a partial purge target, it is forcibly not present (that is, the COINV signal 154 is "0").

The entry read from the address translation buffer 1 is determined to be a partial purge target in the following two cases.

(1) When a valid logical address is not yet held in the logical address register 3, when the real address 102 read from the address translation buffer 1 and the real address held in the purge address register 2 match. , It is determined to be a partial purge target.

(2) When the logical address register 3 holds a valid logical address, the logical address and the logical address of the address conversion request held in the TLB address register 5 are different and the address conversion buffer When the real address 102 read from 1 and the real address held in the purge address register 2 match, it is determined to be a partial purge target.

In both cases (1) and (2), the value of the LACOIN signal 152 output from the comparison circuit 8 is "0", and the RACOIN signal 15 output from the comparison circuit 7 is 15.
Since the value of 1 becomes "1", the COINV signal 154 which is the output of the NAND gate 10 becomes "0", and the comparison circuit 6
Even if the TLBCOIN signal 150, which is the output of, is "1", the TLBHIT signal 155 is forcibly determined to be "0", that is, it is determined that the address translation request logical address does not exist in the address translation buffer 1. Dynamic address translation is performed using an address translation table (not shown), and the real address is obtained.

Further, by rewriting the address translation table (not shown), the entry including the "pair" of the logical address newly associated with the real address to be canceled and the real address is the address translation buffer 1 Since the logical address is registered in the logical address register 3 as well as being registered in the logical address register 3, it is excluded from the partial purge target under the condition (2).

As can be seen from the above description, according to this embodiment, when an address translation request is made during the partial purge, a "pair" with the real address 102 corresponding to the logical address 101 of the request is made. , A “pair” of the real address to be canceled and the logical address newly associated with the real address by rewriting the address conversion table (not shown) is compared, and based on the comparison result, the true Since it is determined whether or not it is a partial purge target, it is possible to improve the determination accuracy of the partial purge target entry even when an address translation request is issued during the partial purge.

[0067]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When performing a partial purge of the address translation buffer, a "pair" of the real address obtained by accessing the address translation buffer with the logical address before the partial purge and the logical address used for the access , A comparison means for comparing a real address given for performing a partial purge and a “pair” of logical addresses corresponding to the real address, and holding in the plurality of entries based on the comparison result of the comparison means. Since the determination means determines whether or not the “pair” of the real address and the corresponding logical address is the partial purge target, the determination accuracy of the partial purge target entry in the address conversion request during the partial purge. Can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of an address translation control device according to the present invention.

FIG. 2 is an explanatory diagram for explaining a dynamic address translation mechanism.

[Explanation of symbols]

1 ... Address conversion buffer, 2 ... Purge address register, 3 ... Logical address register, 4 ... Selector, 5
... TLB address register, 6 ... Comparison circuit, 7 ... Comparison circuit, 8 ... Comparison circuit, 9 ... Not gate, 10 ... NAND gate, 11 ... AND gate, 12 ... Dynamic address translation circuit, 13 ... Translation address register, 14 ... Comparison circuit, 1
5 ... Selector, 16 ... Memory address register, 101
... logical address, 102 ... real address.

Front Page Continuation (72) Inventor Kaino Hirodori 1st Horiyamashita, Hadano City, Kanagawa Pref., General Computer Division, Hiritsu Manufacturing Co., Ltd. (72) Inventor Dai Igarashi 1st, Horiyamashita, Hadano City, Kanagawa Hitachi Computer Ta Engineering Co., Ltd.

Claims (1)

[Claims] 1. An address translation table that associates a logical address on a virtual storage device with a real address on a real storage device, the real address translated in the past using the address translation table, and a logic corresponding to the real address. In an address translation control device provided with an address translation buffer having a plurality of entries for holding addresses as "pairs", when performing the partial purge of the address translation buffer, the address translation buffer is set to the logical translation before the partial purge. A “pair” of the real address obtained by accessing the address and the logical address used for the access,
Based on a comparison result of the real address given for performing the partial purge and a “pair” of logical addresses corresponding to the real address, and a comparison result of the comparison means, the data is held in the plurality of entries. An address translation control device comprising: a determination unit that determines whether or not a "pair" of the existing real address and the corresponding logical address is the partial purge target.