JPH07319687A - Data flow controller and memory unit - Google Patents

Abstract

PURPOSE:To prevent the illegal copy of output data by defining replacement data which are normal instructions corresponding to the combination of separated addresses such as branching instructions or the like. CONSTITUTION:A cassette 9 where a software is stored is constituted of a ROM 4 and this data flow controller 10. Then, the output data of a specified address are related not only with address data inputted latest but also the address data inputted before, the combination of the plural address data is defined as key data and the data corresponding to the key data are stored in the data flow controller 10. In the meantime, dummy data (for instance, 'BREAK' data for breaking down a system) are put in the normal ROM 4. Thus, whether or not they are the dummy data, is not recognized at all and what is the key data is not recognized by anyone except the development person who knows all the processing procedure of the software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow control device for switching and outputting data and a memory device including the data flow control device, and more particularly to a control system or game machine processed by a CPU and software. In particular, the present invention relates to a data flow control device used as a defense means for preventing illegal copying of software, and a memory device incorporating the control means.

[0002]

2. Description of the Related Art In a conventional control system, for example, as shown in FIG. 33, a CRT 2, a CPU (central processing unit) 3, a ROM 4, a terminal 5, and an SRAM 6 are connected to a data bus 1.
Etc. are connected. Here, the software is generally stored in the ROM 4, and the selection processing is performed according to the instruction of the software activation from the terminal 5, and the result is displayed on the CRT 2. Further, the SRAM 6 and the like are used when temporary data storage is required during the processing. Alternatively, a part of the software from the ROM 4 may be downloaded to the SRAM 6 and then processed by the CPU 3.

As shown in FIG. 34, the software stored in the ROM 4 is such that each data D is stored at a specific address A indicating its storage address one by one, and is supplied from the CPU 3. The software is executed by the CPU 3 using the data D output by the address A. In order to utilize many software development vendors in such a control system or a game system using such a control system, the ROM of FIG.
The part is configured to be detachable in a cassette type, and by replacing the cassette 9, the RO provided in the cassette 9 is replaced.
Control according to the stored contents of M4 is performed, or a game according to the stored contents can be enjoyed.

[0004]

When the portion of the ROM 4 for storing the software is of the cassette type as described above, the content of the ROM 4 is such that the data D is transferred to the data line 8 only by giving the address A from the address line 7. It will output. Due to such a simple structure, illegal copying can be easily performed by sequentially giving all the addresses A one by one and reading all the data D. For this reason, a long-standing problem is caused in that the rightful owner of the software developed by investing a large amount of human resources and funds is lost for a long time.

Therefore, it is an object of the present invention to provide a data flow control device and a memory device including the data flow control device, which makes such illegal copying impossible.

[0006]

The data flow control device of the present invention comprises (1) 1) First input terminal to which first input data is sequentially input (1 2) Second input terminal to which second input data is sequentially input (1 3) Output terminal that outputs output data sequentially (1 4) Memory means for storing one or a plurality of replacement data defined corresponding to one or a plurality of arrays of the plurality of first input data (1 5) When the latest first input data is input from the first input terminal, a plurality of first input data including the latest first input data and traced back in the order of input from the latest first input data The second data input from the second input terminal depending on whether the input data corresponds to any one of the above arrays.
Output data in which at least a part or all of the bits of the input data are replaced with replacement data defined corresponding to the array, the same as the second input data input from the second input terminal. Second output data of logic, first
Of the third output data generated by the logical operation based on the output data of and the fourth output data generated by the operation based on both the first output data and the second output data Data switching means for outputting different data selected from the above from the output terminal as the output data.

Here, the above (1 The memory means of 4) is
(2 1) One or a plurality of memory areas are provided, and each of the replacement data is stored in each of the memory areas. The data switching means of 5) is (3) 1) One or a plurality of searched data to be searched for whether or not they match the search data composed of a plurality of first input data sequentially input from the first input terminal are stored, and the search is performed. In the case where a match between the search data and the searched data is detected in, for reading the replacement data from the memory area of the memory means in which the replacement data corresponding to the searched data for which the match is detected is stored. Data reference means for outputting access signal (3 2) Depending on whether or not the access signal is output, at least a part or all of the bits of the second input data input from the second input terminal are replaced with the replacement data read from the memory means. The first output data, the second output data composed of the second input data input from the second input terminal, the third output data generated by a logical operation based on the first output data, And different data selected from the data group consisting of the fourth output data generated by the logical operation based on both the first output data and the second output data,
Data output means for outputting the output data from the output terminal may be provided.

The above (2 The memory means of 1) is the same as that of
Although it does not have to have a specific configuration defined above in 1), for example, in (2) above. It is preferable that the memory means 1) stores replacement data defined by a combination of the enhancement transistor and the depletion transistor. In addition, (3 The data reference means of 1) is also described in It does not have to be narrower than that defined in 1), but the above (3
It is preferable that the data reference means of 1) stores the searched data defined by the combination of the enhancement transistor and the depletion transistor.

Further, in the data flow control device of the present invention,
And above (1 The data switching means of 5) is (4) 1) The latest first input data from the first input terminal
When is input, the latest first input data is included
A plurality of data traced in the order of input from the latest first input data
The first input data is the first input data forming the above array.
The first input data that does not form the above array between data
Including any one of the above arrays when the insertion of
The second input from the second input terminal depending on whether
At least some or all of the input data
Replaced with the replacement data defined for that array
The first output data, which is input from the second input terminal
Second output data having the same logic as the second input data,
First generated by a logical operation based on the first output data
3 output data, and 1st output data and 2nd output
Fourth generated by logical operation based on both data
Mutually selected from the data group consisting of the output data of
Different data from the output terminal as the above output data
It may be output.

Here, the above (1 The memory means of 4) is
(5 1) One or a plurality of memory areas are provided, and each of these memory areas indicates, as necessary, the replacement data, the feedback data used for searching the array, and whether or not it is the final stage of the array. The output control data is stored, and the above (4 The data switching means of 1) is (6) 1) Above (5 A register for storing the feedback data read from the memory means of 1) (6) 2) One or a plurality of objects to be searched for whether or not they match search data formed of a pair of first input data input from the first input terminal and feedback data stored in the register. When the searched data is stored and a match between the searched data and the searched data is detected in the search, the above (5 (1) Data reference means for outputting an access signal for reading data stored in the memory sub-area from the memory area corresponding to the searched data for which a match is detected in the memory means of 1). 3) Above (5 According to the output control data in the data read from the memory means of 1), at least some or all of the bits of the second input data input from the second input terminal are read from the memory area. First output data replaced by replacement data in the data, second output data having the same logic as the second input data input from the second input terminal, logical operation based on the first output data Different from each other selected from the data group consisting of the third output data generated by and the fourth output data generated by the logical operation based on both the first output data and the second output data. Data output means for outputting data from the output terminal as the output data may be provided.

Above (5 The memory means of 1) is the same as that of
Similar to the case of the memory means of 1), the above (5 Although it is not necessary that the configuration is more limited than that defined in 1), for example, the above (5 The memory means of 1) preferably stores data defined by a combination of the enhancement transistor and the depletion transistor.

In addition, the above (6 The same applies to the data reference means of 2), and the above (6) It is preferable that the data reference means of 2) stores the searched data defined by the combination of the enhancement transistor and the depletion transistor. Further, in the data flow control device of the present invention, the above (1 The data switching means of 5) is (7) 1) When the latest first input data is input from the first input terminal, a plurality of first input data including the latest first input data and traced back in the order of input from the latest first input data Whether the input data includes any one of the arrays when the insertion of the first input data within a predetermined number that does not form the array is permitted between the first input data that forms the array. Depending on whether or not, at least a part or all of the bits of the second input data input from the second input terminal are replaced with replacement data defined corresponding to the array, first output data, Second output data having the same logic as the second input data input from the second input terminal, third output data generated by a logical operation based on the first output data, and a first output Data and second output data Different data from each other are selected from among the fourth data group composed of the output data of which is generated by a logical operation based on both the, or may be outputted from the output terminal as the output data.

Here, the above (1 The memory means of 4) is
(8 1) One or a plurality of memory areas are provided, and in each of these memory areas, the replacement data, feedback data used for searching the array, distance data representing the predetermined number, and the array It stores output control data indicating whether or not it is the final stage,
Above (7 The data switching means of 1) is (9) 1) Above (8 A register for storing the feedback data read from the memory means of 1) (9) 2) Above (8 The distance data read from the memory means of 1) is stored, and after the storage, before the next input of the first input data constituting the above array from the first input terminal, A counter that terminates the search of the array being searched when the first input data that does not form the array exceeds the predetermined number determined and is input from the first input terminal. 3) One or a plurality of objects to be searched for matching with search data formed of a pair of first input data input from the first input terminal and feedback data stored in the register. When the searched data is stored and a match between the searched data and the searched data is detected in the search, the above (8 (1) Data reference means for outputting an access signal for reading the data stored in the memory area from the memory area corresponding to the searched data for which a match is detected (9) 4) Above (8 According to the output control data in the data read from the memory means of 1), at least some or all of the bits of the second input data input from the second input terminal are read from the memory area. The first output data replaced by the replacement data in the data, the second output data having the same logic as the second input data input from the second input terminal, and the logical operation based on the first output data Different data selected from the data group consisting of the generated third output data and the fourth output data generated by the logical operation based on both the first output data and the second output data. May be provided with a data output means for outputting the output data from the output terminal.

Above (8 The memory means of 1) is the same as that of
1), (5 Similar to each memory means of 1), the above (8
Although it is not necessary to be limited to the above defined in 1), for example, in (8) above. The memory means of 1) preferably stores data defined by a combination of the enhancement transistor and the depletion transistor.

In addition, the above (9 The same applies to the data reference means of (3), and the above (9 It is preferable that the data referencing means 3) stores the searched data defined by the combination of the enhancement transistor and the depletion transistor. Further, in the data flow control device of the present invention, typically, the address data input from the first input terminal to a storage device (for example, a ROM or the like) that stores a large amount of data is the first input data. Data input as input data and output from the storage device (ROM or the like) is input as the second input data from the second input terminal. Further, the memory means in the data flow control device of the present invention comprises the replacement data corresponding to the first array of the plurality of first input data, and the plurality of first input data constituting the first array. And replacement data corresponding to a second array consisting of one or a plurality of first input data arranged subsequently to the plurality of first input data are stored. It is also a preferable aspect that the memory means stores a plurality of replacement data corresponding to each of a plurality of arrays including the same first input data in the final stage.

The data flow control device of the present invention can be effectively used by adopting an array of address data in the following situations, for example. (A) The first data is address data representing an address on a memory in which an instruction to be executed by the CPU is stored, and a branch instruction or an instruction executed before the branch instruction is used as the array. The stored address,
A plurality of addresses including an address at which an instruction executed after the branch instruction is stored, and an address at which the branch instruction is branched to an address away from the address at which the branch instruction is stored. An array composed of a plurality of address data representing addresses is adopted.

(B) The first data is address data representing an address on a memory where an instruction to be executed by the CPU is stored, and as the above array, it is a subroutine call instruction or before the subroutine call instruction. An array of a plurality of address data representing a plurality of addresses including an address where an instruction to be executed is stored and an address where an instruction to be executed after the subroutine call instruction is stored is adopted.

(C) The first data is address data representing an address on a memory in which an instruction to be executed by the CPU is stored, and as the above array, a return instruction from the subroutine or before the return instruction. An array of a plurality of address data representing a plurality of addresses including an address where an instruction executed is stored and an address where an instruction executed after the return instruction is stored is adopted.

(D) The first data is address data representing an address on a memory in which an instruction executed by the CPU is stored, and the first data corresponds to the event when a predetermined event occurs. An array of a plurality of address data representing a plurality of addresses including an address at which a call instruction for invoking a predetermined routine is stored and an address at which an instruction executed after the call instruction is stored To do.

(E) The first data is address data representing an address on a memory in which an instruction executed by the CPU and data accessed from the CPU are stored, and the data on the memory as the array. Of a plurality of addresses including a data access instruction that accesses the data access instruction or an instruction that is executed before the data access instruction and an address that stores the data accessed by the data access instruction. An array of address data is adopted.

The data flow control device of the present invention can be configured as follows, for example, as one embodiment thereof. That is, the data flow control device of the present invention as one embodiment thereof includes: (10_1) a first input terminal to which first input data is sequentially input; (10_2) a second input data to which second input data is sequentially input; Input terminal (10_3) of which output data are sequentially output. (10_4) replacement data defined corresponding to one or more respective arrays of the plurality of first input data, and Memory means for storing feedback data defined corresponding to first input data included in at least one array (10_5) register for storing feedback data read from the memory means (10_6), The second input data input from the second input terminal and the replacement data read from the memory means are input, and the second input data is input according to a predetermined control signal. Alternatively, a selector which outputs the data in which at least a part or all of the bits of the second input data are replaced with the replacement data to the output terminal as the output signal (10_7) Any one of the arrays From the pair of the first data included in and the feedback data defined corresponding to the first data that is arranged immediately before the first data and that constitutes the above-mentioned array that includes the first data. The searched data to be searched is stored in each searched data memory area corresponding to each of the first data included in any one of the above arrays, and the first data input from the first input terminal is stored. Data stored in the above register,
Search data composed of a pair of return data read from the memory means is compared with each of the searched data, and the searched data corresponding to the searched data is stored in the searched data memory area. Coincidence detecting means for outputting a coincidence signal to the signal line provided therein (10_8) In response to the coincidence signal being outputted to the signal line, the searched data memory corresponding to the signal line to which the coincidence signal is outputted. The feedback data defined corresponding to the first data forming the searched data stored in the area is read from the memory means and stored in the register, and the first input data forming the search data is Depending on whether or not it is the first input data arrayed at the end of any one of the arrays, the replacement data defined corresponding to that array The selector outputs the data in which at least some or all of the bits of the second data read from the memory means and input from the second input means are replaced with the replacement data.
Alternatively, the data flow control device is provided with a control means for causing the selector to output the second data input from the second input means.

Further, the above-described data flow control device of the present invention can be configured as another embodiment, for example, as follows. That is, the data flow control device of the present invention as an embodiment thereof includes (11_1) a first input terminal to which the first input data is sequentially input, and (11_2) a second input data to which the second input data is sequentially input. Input terminal (11_3) Output terminal from which output data is sequentially output. (11_4) Replacement data defined corresponding to one or each array of a plurality of first input data, and one of the arrays The feedback data defined corresponding to the first input data included in the one array and the first data defined corresponding to the first input data are output from the first input terminal. After being input, the first data arranged immediately after the first data constituting the array including the first data is input from the first input terminal, and then the first data is input. Input from the input terminal Memory means (11_5) for storing distance data indicating the number of other first input data which is allowed to be stored (11_5) register for storing feedback data read from the memory means (11_6) from the memory means By storing the read distance data and comparing the distance data with the number of first input data input from the first input terminal after the storage, the distance data is read from the first input terminal. , Searching the array when the number of other first input data input while two adjacent first input data adjacent to each other in the array exceeds the number determined by the distance data Counter to end (11 7) The second input data input from the second input terminal and the replacement data read from the memory means are input, and the second input data, or the second input data, is input in accordance with a predetermined control signal. A selector (11) for outputting the data obtained by replacing at least a part or all of the bits of the second input data with the replacement data as the output signal to the output terminal. 8) Corresponding to the first data included in any one of the above arrays and the first data that is arranged immediately before the first data and that constitutes the array including the first data Stored in the searched data memory area corresponding to each of the first data included in any one of the above arrays, the searched data in pairs with the return data defined as Search data consisting of a pair of the first data input from the first input terminal and the feedback data stored in the register and read from the memory means are compared with each of the searched data. Match detection means for outputting a match signal to a signal line provided corresponding to the searched data memory area storing the searched data matching the searched data (11) 9) Corresponding to the first data forming the searched data stored in the searched data memory area corresponding to the signal line to which the match signal is output, in response to the output of the match signal to the signal line The feedback data and the distance data defined as above are read from the memory means and stored in the register and the counter, respectively, and at least one of the first input data and the array forming the feedback data is read. First arrayed at the end of the array
Of the second data input from the second input means by reading the replacement data defined corresponding to the array from the memory means according to whether the input data is input data Data comprising a control unit for causing the selector to output the data in which the bit of is replaced with the replacement data, or for causing the selector to output the second data input from the second input unit. It is a flow control device.

The memory device of the present invention is (12) 1) Input terminal for inputting input data (12) 2) Output terminal that outputs output data sequentially (12 3) First memory means for storing a plurality of storage data respectively defined corresponding to a plurality of input data (12) 4) Second memory means for storing one or more replacement data defined corresponding to one or more respective arrays of the plurality of input data 5) When the latest input data is input from the input terminal, a plurality of first input data including the latest input data and traced back in the input order from the latest input data is any one of the above arrays. At least a part or all of the bits of the storage data defined corresponding to the latest input data are replaced with the replacement data defined corresponding to the array, depending on whether or not First
Output data, a second output data having the same logic as the storage data defined corresponding to the latest input data, and a third generated by a logical operation based on the first output data.
Output data and different data selected from a data group consisting of fourth output data generated by a logical operation based on both the first output data and the second output data, The memory device is provided with a read control means for outputting to the output terminal as.

Here, in the memory device of the present invention, the above (12) The read control means of 5) is (13) 1) When the latest input data is input from the input terminal, a plurality of first input data including the latest input data and traced back in the input order from the latest input data are the input data forming the array. At least storage data defined corresponding to the latest input data is included depending on whether any one of the arrays is included when the insertion of the input data that does not form the array is allowed between them. First output data in which some or all of the bits are replaced with replacement data defined corresponding to the array,
Second output data having the same logic as the storage data defined corresponding to the latest input data, third output data generated by a logical operation based on the first output data, and first output data Even if the different data selected from the data group consisting of the fourth output data generated by the logical operation based on both the second output data are output to the output terminal as the output data. Good.

Further, in the memory device of the present invention, the above (12) The read control means of 5) is (14) 1) When the latest input data is input from the input terminal, a plurality of first input data including the latest input data and traced back in the input order from the latest input data are the input data forming the array. It is defined corresponding to the latest input data according to whether or not any one of the above arrays is included when the insertion of the input data within each predetermined number that does not form the above array is allowed between them. At least a part or all of the bits of the stored data are replaced with replacement data defined corresponding to the array.
Output data, second output data having the same logic as the storage data defined corresponding to the latest input data, third output data generated by a logical operation based on the first output data, and first Which outputs different data selected from the data group consisting of the fourth output data generated by the logical operation based on both the output data and the second output data to the output terminal as the output data. May be

Address data is typically input to the memory device of the present invention as the input data.
In the memory device of the present invention, it is preferable that the “different data” output from the output terminal is data as exemplified below. (A) Output data output from the output terminal is CPU
The data different from each other, which are output from the output terminal, have the same instruction code and different operands. For example, (a 1) The different data are data representing instructions for storing different values in the same register. (A 2) The different data is an instruction to store a predetermined value in different memory addresses. (A 3) The different data are branch instructions to different addresses. (B) The output data output from the output terminal is the CPU
And at least one of the different data output from the output terminal is data representing a return instruction from the subroutine. (C) The output data output from the output terminal is the CPU
The data different from each other output from the output terminal includes data representing an instruction to be executed in step 1. (D) The output data output from the output terminal is the CPU
The data different from each other, which is output from the output terminal, includes data referred to by a predetermined instruction executed by
The data having different values referred to by the predetermined instruction.

[0027]

In the program, there is always a situation in which instructions (data) stored at addresses other than adjacent addresses, such as jump instructions and branch instructions to subroutines, are read out from the ROM or the like. Moreover, only the developer of the program knows at what address and at what address the branch occurs.

The present invention has been completed paying attention to this point. That is, when the "first input data" to the "input data" are used as address data, replacement data that is a regular instruction is defined corresponding to a combination of addresses such as a branch instruction that are distant from each other. When a plurality of address data are input in the order defined by the program, for example, replacement data is output, and the CPU can execute the replacement data as a regular instruction.

On the other hand, by ignoring, for example, a jump instruction or the like, address data which is sequentially incremented is given to R
Attempting to read the contents of the OM will result in the reading of different or erroneous data that is not replaced by the replacement data. Therefore, it is possible to prevent illegal copying of output data due to input of simple address data that does not follow the data processing flow of software.

In recent years, CPUs that perform so-called prefetch operations have been introduced to speed up the processing. This prefetch operation is data (instruction) in the CPU.
It is to read ahead the data of the next address mechanically without waiting for the end of the execution of
For example, in the case of a branch instruction, the preread data is discarded and the data at the branch destination address is read again.

In the present invention, even if there is first input data (input data) that does not form the array between first input data (or input data) that forms the certain array, the existence of the array exists. Can be recognized, it is possible to extract an array and output regular data without malfunction even in the case of an operation that ignores the processing procedure of a program such as a prefetch operation.

Further, the above (6_1) to (6_) of the present invention.
A data flow control device having the data switching means of 3),
A data flow control device having the data switching means of (9_1) to (9_4), and (10_1) to (10_).
8) A data flow control device equipped with the above, or (1) above.
In a data flow control device including 1_1) to (11_9) or a memory device incorporating any of those data flow control devices, the feedback data is read from the memory means and the feedback data is used for the next search. Since it is configured to be used, an "array" according to the present invention can be defined quite freely from an array consisting of a small number of first input data to an array consisting of a large number of first input data, which is extremely free. A high-quality system is constructed.

When data is defined by a combination of an enhancement transistor and a depletion transistor as the memory means and the data reference means referred to in the data flow control device of the present invention, an LSI equipped with the data flow control device or memory device of the present invention is mounted. When disassembling and observing with a microscope or the like, neither the enhancement transistor nor the depletion transistor can be distinguished in appearance, and therefore the analysis of the data defined there becomes more difficult, and the prevention of illegal copying can be further ensured. .

Further, as the "array" according to the present invention, when each first input data is a, b, c, d, ...
For example, the sequences'a, b, c'and the sequences'a, b, c, d'may define a plurality of partially overlapping sequences, or, for example, the sequences'a, b, x'and the sequence'c. , D, x'and arrays'e, f, x'define a plurality of arrays in which the data x at the final stage of each array is common, the arrays become complicated, and data analysis and illegal copy The difficulty will increase.

The "different data" referred to in the present invention means that one of them is "normal" data that can continue normal operation, and the other is "abnormal" data that causes a system down, for example. Alternatively, all of the “different data” may be “normal” data that causes normal operation in different situations in the program flow.

[0036]

1 is a block diagram showing the overall configuration of a control system adopting an embodiment of the present invention. The same numbers are used for those that are the same as the conventional ones.
In the figure, it should be noted that the cassette 9 in which the software is stored is composed of the ROM 4 and the data flow control device 10. Therefore, the address line 7 and the data line 8 which are output to the outside of the cassette 9 can be provided as being the same as the conventional ones, and the conventional control system or game system excluding the cassette 9 can be used as it is. .

Now, the first embodiment of the data flow control device 10 shown in FIG. 1 will be described in detail. First, as shown in FIG. 2, data D is stored in each address A in the ROM 4, and the address data is input to the ROM 4 from the address line 7 through the data flow control device 10. It Similarly, the output data from the ROM 4 is output to the data line 8 via the data flow control device 10. Of course, all or part of the address line 7 or part of the data line 8 may be directly connected to the ROM 4.

From the normal operation of the software, the input order of the address data is J-2 → J-1 → J.
→ Assume J + 2. At this time, a combination of a plurality of address data (J-2,
J-1, J, J + 2) corresponding to the regular data D (J +
2) is defined. On the other hand, in ROM4, data'B which causes system down corresponding to address data J + 2
REAK 'is defined.

The address processing procedure and the output data by this software when this control system is operating are as shown in FIG. That is, for the address data J-2, J-1 and J, the ROM
Data D (J-2), D (J-)
1) and D (J) are output, and the next process is address J
+2, and the data stored in ROM4 is BRE
Although the system is brought down by AK, output of this data is stopped by the data flow control device 10, and instead, data D (J + 2) is output to the data line 8,
Normal operation continues. However, in case of illegal data copy, this actual software processing procedure,
In other words, without understanding the flow of addresses, the addresses are sequentially input and the data output corresponding to each input address is read. In this case, the output data for each address is as shown in FIG. 3B because the data replacement by the combination of address data (J-2, J-1, J, J + 2) does not occur.
Only BREAK can be obtained as data for +2, and even if an attempt is made to operate the software with such data, the system goes down at some point and becomes inoperable.

As described above, here, the discontinuity of the addresses existing when the actual software operates and the relationship of the addresses that the data from a plurality of addresses are required for a series of processing are 2 Focus on the point. From this point, the output data of a specific address is associated not only with the latest input address data but also with the previously input address data, and the combination of these multiple address data is used as key data to correspond to that key data. Data to be stored is stored in the data flow control device 10, while dummy data ('BREAK' data for bringing down the system in the above example) is stored in the normal ROM 4. By doing this, unless the developer who knows all the processing procedures of the software, it is completely unknown whether it is dummy data or not, and what is the key data.

Further, in this embodiment, four combinations of addresses J-2, J-1, J and own address J + 2 are defined as the key data of D (J + 2), and these four address data are the same. The regular D (J + 2) output is obtained only when input in order.
By varying the number of address data defined as this key data or increasing the number of data to be replaced by increasing the number of each key data,
Illegal copying can be made even more difficult.

Next, the data flow control device 10 of the present invention.
An example will be described more specifically with reference to FIGS. 4 and 5. In this example, for simplification, a 2-bit address is input from the address line 7, the output data is also 2-bit, and is output from the data lines 8a and 8b.
The 2-bit data from is input from the output data lines 42a and 43a. In addition, key data (search data that matches the defined array) is also a 2-bit address of 2
2 sets of address data (0,0) →
For the key data composed of the combination of (1,1), (0,1) is output as output data, and for the key data composed of the combination of two address data (1,0) → (0,0) Output data (1,0) is output. In the case of a combination other than these two sets, the output data output from the ROM 4 to the output data lines 42a and 43a is output as it is. An address line (not shown) branched from the address line 7 is directly connected to the ROM 4.

The data flow control device 10 is provided with a selector 46, whose output is the data lines 8a, 8a.
It is connected to b. One of the two sets of inputs to the selector 46 is one of the output data lines 42a, 4a from the ROM 4.
3a, the other set is connected to the data output lines 42b and 43b. Inside the selector 46, there are two n-channel transistors Tn and p-channel transistors Tp.
When there is a set and the selector control signal line 51 is “0” (when there is no key data input), the output line 42 from the ROM 4
a and 43a are connected to the data lines 8a and 8b, and the ROM 4
When the selector control signal line 51 is "1" (when key data is input), the output data of
The data output lines 42b and 43b are connected to the data lines 8a and 8b, and the data in the data flow control device 10 is output.

In this example, the selector 46 is used for simplicity.
However, this may be one that performs a certain arithmetic processing. Further, for example, the output line 43a from the ROM 4 is directly connected to the data line 8b without passing through the selector 46, or the like.
4 may be only a part of the bits of the data output from No. 4.

Here, the data output lines 42b and 43b are connected to the output of a general dynamic type sense amplifier 52. In general, the dynamic sense amplifier 51 firstly receives the bit line 1 corresponding to the input of the inverter 151.
52 is precharged in advance by the precharge transistor 153, and the memory cells M11 and M1 are precharged.
The change in the potential of the bit line 152 due to 2, M21 and M22 is detected. In the illustrated embodiment, each memory cell M11, M12, M21, M22 has a data "1" depending on whether the transistor connected in series to the control transistor 154 is the depletion transistor Td or the enhancement transistor Te. And "0" are represented. This operation will be described in more detail. When an address data group (two address data = 4 bits in this embodiment) as key data is input, the control word line 155 is input.
One of them becomes the "1" level, and the memory cell M1
1, word line W connected to M12, M21, M22
The potential of the selected one of 1 and W2 becomes the "0" level. Now, if the word line W1 becomes "0" level, the memory cells M11 and M12 are selected, and these memory cells M11 and M12 are an enhancement transistor Te and a depletion transistor Td, respectively.
The memory cell M11 is non-conductive, and the memory cell M12 is conductive to the ground line. Of the two bit lines 152 in the figure, only the bit line 152 on the right side is set to the ground, and as a result, the dimic amplifier 52 outputs the inverted signal thereof, so that "0" is output from the data output line 42b. "1" is output from the output line 43b.

At this time, one of the control word lines 155 is
One (here, the upper control word line of the two control word lines 155 in the figure) becomes "1" level, so that the selector control transistor 156 connected thereto is turned on, and the precharge is performed in advance. The selected selector control signal detection line 157 becomes "0" level, this level is detected by the dynamic sense amplifier 52, the selector control signal line 51 becomes "1", and the selector 46 moves to the data output lines 42b and 43b side. The data (0, 1) from the memory cells M11 and M12 that are switched are changed to the data line 8
It will be output to a and 8b.

The data output section (right half in the figure) of the data flow control device 10 has been described above. Next, the key data reference section (left half in the figure) for controlling this data output section.
Will be described. First, address data input from the address line 7 is input to the shift register 47. The address line 7 has an ATD (Adjustment Detector) 4 for detecting a change in the address data.
8 is connected to drive the shift register 47 by this signal, and the control circuit 49 is used to generate the entire control signal to be placed on the control signal line 50.

First, when the address data is input from the address line 7, the change of the address data due to the input of the new address data is detected by the ATD 48, and the output signal thereof changes each time the address data changes. New address data is input to the shift register 47. In this embodiment, the shift register 47 is composed of two registers D1 and D2 each having 2 bits, and stores two sets of 2-bit address data in the order of input. That is, it is possible to always store two sets of address data in time series.

Further, the address data stored in the shift register 47 has the inverter group 141 for each bit.
And the inverter group 141 generates a normal signal and an inverted signal of each bit, and the coincidence detection circuit 14
Entered in 2. In the present embodiment, the match detection circuit 142 employs a dynamic NAND decoder as an example. One enhancement transistor Te and one depletion transistor Td are provided for each bit.
4 bits, that is, 4 groups are serially connected, one end of which is connected to the dynamic sense amplifier 52 similar to that described above, and the other end of which is connected to the control transistor 14.
3 is connected.

Similar to the above description, the dynamic sense amplifier 52 is to precharge the input side of the inverter 151 in advance and detect the potential change thereof. Therefore, this potential becomes "0" level,
In order for the output of the inverter 151 to reach the “1” level, all of the enhancement transistor Te and the suppression transistor Td that are serially connected and that constitute the dynamic NAND decoder are turned on,
In addition, the control transistor 143 also needs to be turned on. Only when this condition is satisfied, the output of the dynamic sense amplifier 52 becomes "1", one of the control word lines 155 becomes "1" as described above, the memory section of the data flow control device 10 is selected, and the selector 46 is selected. It is output.

The condition in which all the transistors of the NAND type decoder are turned on will be described using a pair of transistors of the depletion transistor Td and the enhancement transistor Te at the upper left end in the figure. First, the normal data line 144 and the inverted data line 145 of 1-bit address data are connected to the gates of these transistors. Since the depletion transistor Td is turned on even when the gate voltage thereof is “0” level, both of the transistors connected in series are turned on because the voltage of the “1” level is applied to the gate of one enhancement transistor Te. Is applied, that is, when one bit of the address is "0". In this way, the NAN at the upper left of the drawing
In the D-type decoder, two sets of address data are (0,0)
→ When (1, 1), all are turned on, and (0,
It can be seen that 1) is output. Also, with respect to the other NAND type decoder thereunder, when (1, 0) → (0, 0) is input as address data, the output of the dynamic type sense amplifier 52 becomes “1”,
That is, (1, 0) is output from the memory section. Of course, at this time, the control signal line 50 goes to "1" level and the control transistor 143 is turned on.

FIG. 5 shows a timing chart of this operation. When address data is applied from the address line 7 to the data flow control device 10 and the ROM 4 (see FIG. 1), the ROM is sent via the data lines 42a and 43a.
4 output data is input. At the same time, ATD48
Generates a pulse by detecting the address change. A control signal as shown in FIG. 5 is generated based on this pulse, and the address data is input to the shift register 47. However, if it does not match the key data written in the NAND decoder, the selector control signal becomes It remains "0", and the output data from the ROM 4 is the data line 8 as it is.
It is output to a and 8b.

On the other hand, when the key data and the input address data set match, the selector control signal becomes "1" level, and the internal data is output from the memory section of the data flow control device 10. Here, it becomes possible to define the key data and the output data corresponding thereto depending on which transistor of the NAND type decoder is the enhancement transistor Te and which part of the memory section is the enhancement transistor Te.

Of course, it goes without saying that the circuit system shown in this embodiment is merely an example, and other known circuit systems may be used. In the above embodiment, the ROM 4
Although the data flow control device 10 is configured separately from the above, the data flow device 10 may be incorporated in a memory device such as a ROM.

Next, the data flow control device 10 of the present invention.
The second embodiment will be described. Here, as shown in FIG. 6, each data A shown in FIG. 6 is stored in the ROM 4, and as shown in FIG. 7, from the normal operation of the software, the address data Input order is A (n) → A (n + 1) → ... → A (j) → A
It is assumed that (j + 1) → A (j + 2) → A (k) → A (m). Here, of these address data, an array of address data {A
(N), A (j), A (k)} and an array {A (n), A obtained by adding address data A (m) to this array.
(J), A (k), A (m)} are focused on, and these two arrays {A (n), A (j), A
(K)}, {A (n), A (j), A (k), A
(M)} corresponding to the regular data D
(K) and D (m) are defined as addresses A (k) and A (m) in the data flow control device 10. On the other hand, ROM4
In the addresses A (k) and A (m), data "BREAK1" and "BREAK2" that cause a system down
Are defined respectively.

FIG. 7A shows an address processing procedure and output data thereof when the control system is operating by such software. That is, except for the address data A (k) and A (m), the data stored in the ROM 4 is output.
When (k) and A (m) are input, 'BREAK1'and'BREAK2'that bring down the system are in ROM.
Instead of being output from 4, the normal data D (k) and D (m) are output from the data flow control device 10, and normal operation is continued. However, when performing illegal data copying, regardless of this actual software processing procedure, in other words, the flow of a legitimate address, for example, the addresses are input sequentially and output corresponding to each input address. You will read the data. The data output corresponding to each address in this case is as shown in FIG. 7B, and the addresses A (k), A
'BREAK1', 'BR as data for (m)
Only EAK2 'can be obtained, and trying to run the software with such data at some point causes the system to go down and become inoperable.

As described above, here, the discontinuity of the addresses existing when the actual software operates and the relationship of the addresses that the data from a plurality of addresses are required for a series of processing are 2 Focus on the point. From this point, the output data of a specific address is not only the latest or the address data input at that time,
The data corresponding to the key data is stored in the data flow control device 10 in association with the address data input before that, and the combination of the plurality of address data is stored as the key data. Put dummy data (data of'BREAK1 'and'BREAK2' that bring down the system in the above example). By doing this, unless you are a developer who knows all the software processing steps, you have no idea whether it is dummy data or what the key data is.

Further, in this embodiment, as the key data of the data D (k), the address data A (n), A (j) and the three address data of its own address A (k) and the data D (m) are stored. Address data A (n), A (j), A (k) and own address A as key data
The order in the four address data of (m) is defined, and the regular data D (k) and D (m) are respectively converted to the address data A (k by the generation order of these three to four address data. ), A (m) is output corresponding to the input. Of course, the arrangement is not limited to the arrangement of three or four address data shown in this example, and an arbitrary number of addresses accessed for performing a series of processing,
Select one in any location, put dummy data in ROM4,
It is possible to input regular data and its key data into the data flow control device 10. This makes illegal copying even more difficult by changing the number of address data defined as this key data, or by increasing the number of regular data to be replaced by increasing the number of each key data. Can be done.

Next, the data flow control device 10 of the present invention.
The circuit configuration of the second embodiment will be described with reference to the block diagram of FIG. 8 and the timing chart of FIG. First, address data is input to the match detection unit 241 via the address line 7 shown in FIG. At the same time, the data stored in the feedback register 242 is input to the match detection unit 241, and the word line 243w of the match block 243 that matches both the data stored in the feedback register 342 and the address data becomes active. As a result, the memory block 245 right next to it is selected.

Each memory block 245 comprises a feedback register control flag 245a, feedback data 245b, output data 245c and a selector control flag 245d. The matching block 243 is composed of an address data matching unit 243a and a feedback data matching unit 243b. First, address data A via address line 7
(N) is input to the match detection unit 241. At this time, A (n) is contained in the address data matching section 243a of the fourth matching block 243 of the matching detection section 241. The feedback data matching unit 243b of the fourth matching block 243 is set to the don't care state (a state in which any data is considered to match). As a result, a match occurs in the fourth match block 243, the word line 243w thereof becomes active, and the fourth memory block 245 right next to the figure is selected.
The stored data is output respectively. Since the selector control flag 245d of this stored data is “0”, the selector 246 outputs the output signal from the ROM 4 input via the data input line 247 to the data line 248. Further, the feedback register control signal generated by delaying the '1' signal of the feedback register control flag 245a by the delay circuit 249 causes the feedback data 45b to be '1'.
The data is input to the feedback register 42. This state is time T1 in the timing chart of FIG. The ATD output and control signal in FIG.
Is a signal generated based on the change in the address data detected by the control circuit 249, which controls the entire data flow control device 10.

Further, a plurality of address signals are input to the data flow control device 10 via the address line 7, and at the same time R
The address signal is also input to the OM4. Data corresponding to each address is output from the ROM 4, but there is no match in the match detection unit 241 of the data flow control device 10 unless the address signal A (j) is input, and the selector 46 always reads from the ROM 4 Will be output to the data line 8.

Also, the feedback register control signal is always "0".
Therefore, the value of the feedback register 242 maintains the state of "1".
When the address signal A (j) is input here, the address data matching unit 243a of the second matching block 243 of the matching detection unit 241 matches. In addition, the feedback data matching unit 243b of this matching block 243 is preset with a value of "1", and this value also matches, and as a result, the word line 243w of this second matching block 243. Rises, and the memory data of the memory block 245 just beside the line is detected. The selector control flag 245d of this memory block 245 is "0".
Therefore, the selector 246 outputs the data from the ROM 4 to the data output line 8. At this time, the feedback register control flag 245a is "1", and the feedback data 24
Since 5b is '2', the feedback register 2
'2' is input and held in 42 (time T2 in FIG. 9).

Similarly, the output from the ROM 4 is the selector 46 until the address data A (k) is input.
Is output to the data output line 8 via. By the way, when the address data A (k) is input, the match detection unit 241
The fifth address data matching section 243a of
Further, at this time, the value of the feedback data matching unit 243b is "2".
Has been set, and this part will also match. Therefore, the data of the memory block 245 corresponding to this coincidence block 243 is detected. Since the selector control flag 245d of this data is "1", the data from the ROM 4 is not output this time, but instead the output data 245 corresponding to the matching block 243 is output.
The value of c, that is, D (k) will be output via the selector 246.

At the same time, since the feedback register control flag 245a is "1", the feedback data 245b is returned.
'3' is input and held in the feedback register 242 (FIG. 9).
Time T3). The same applies when the address A (m) is next input, and the data D (m) stored in the data flow control device 10 is output instead of the output from the ROM 4 (time T4 in FIG. 9). ).

As described above, the output data is not determined only by the address input at that time, but the output is output for a specific address by the address sequence at the time of executing the software input before that. By making a decision, copying in an illegal address operation is prevented. In addition, as shown in this example, even if one or a plurality of unexpected address data, such as the address data A (n), comes, it is possible to always wait for the next key. Because,
Due to the prefetch operation of the CPU for speeding up the processing in recent years, proper key data extraction and normal data extraction can be performed without malfunction even when prefetching data at consecutive addresses that do not consider the software processing procedure. Output is possible.

Next, concrete circuit examples of the main constituent elements in the block diagram of FIG. 8 will be described. First, the match detection unit 2
41, each circuit example of the matching block 243 of FIG.
It shows in (b). 10A and 10B employ a dynamic NAND circuit having a configuration of a programmable decoder and having a plurality of input transistors connected in series for the purpose of compact design.

FIG. 10A shows a plurality of enhancement type transistors 264 connected in series, and the input signal line 2 is connected to the gate of the transistor 264.
Depending on whether the positive logic line 268a of 68 is connected or the negative logic line 268b is connected, it is defined as "1" or "0" respectively. Further, an enhancement type transistor 264 connected to this series has a control transistor 261 connected to one end and a dynamic sense amplifier 260 connected to the other end, which are controlled by a control signal line 262. The operation will be specifically verified by taking the address data matching unit 243a as an example.

First, a “0” signal is applied to the control signal line 262, the control transistor 261 is turned off, and the precharge transistor 260 of the dynamic sense amplifier 260 is turned on.
a turns on, the input node of the inverter 260b is charged, the input node is "1", and the output is "1".
It is 0 '. At this time, an address signal is applied to each of the enhancement type transistors 264 already connected to the series.

Next, when the control signal line 262 changes to a "1" signal, the control transistor 261 turns on and the precharge transistor 260a turns off. At this time, the enhancement type transistor 264 connected in series.
When the input address signal is equal to the data defined therein, which is defined by the connection state of the signal line to the gate of, for example, when the gate is connected to the positive logic line 268a and the input address signal is "1". Will turn on its enhancement type transistor 264. Similarly, when the gate is connected to the negative logic line 268b and the input address signal is "0", the signal inverted by the inverter 269 '
1'is applied to the negative logic line 268b, which also turns on its enhancement transistor 264. That is, when the input address signal and the gate connection state match, the enhancement type transistor 264 is turned on. However, when they do not match, “0” is applied to the gate and the gate remains off.

Therefore, when all the connection states of the enhancement type transistors 264 connected in series and the input address signal match, they are all turned on, and the charge charged in the input node of the inverter 260b of the dynamic sense amplifier 260 is discharged. Done '
It becomes 0 '. This "0" signal is inverted by the inverter 260b and a coincidence signal "1" is output.

Further, the coincidence signal "1" is inputted to the gate of the control transistor 261 of the feedback data coincidence section 243b constituted by the dynamic NAND circuit of the next stage. This turns on the control transistor 261 of the feedback data coincidence section 243b, and in the same manner as above,
When the input feedback data matches the data defined by the connection state of the gates of the enhancement type transistors 264, "1" is output to the word line 243w.

The above is an example of the matching block 243 in which data is defined by the connection state to the gates of the enhancement type transistors connected in series. However, with this method, the contact pattern to the gate can be directly visually inspected, and there is a possibility that the coincidence data will be read in the disassembly examination of the LSI. Therefore, next, a circuit system that makes this visual interpretation almost impossible will be described with reference to FIG.

In FIG. 9B, the basic transistor configuration connected to the series is different from that in FIG. 9A, and a transistor pair 266 consisting of an enhancement type transistor 266a and a depletion type transistor 266b is used. , And each is connected to the positive logic signal line 268a or the negative logic signal line 268b. From the outside, it is impossible to determine whether the transistor is the enhancement type transistor 266a or the depletion type transistor 266b. This is because the difference between the two transistors is only the difference in the threshold voltage due to the difference in the concentration of impurities directly under the gate. This transistor pair 26
Regarding the operation of 6, when the input signal '1' is matched, the transistor connected to the positive logic line 268a is made an enhancement type and the transistor connected to the negative logic line 268b is made a depletion type. In this way, if "1" is input to the input signal line 268,
"1" on the positive logic line 268a and "0" on the negative logic line 268b
Is applied. At this time, the enhancement type transistor 266a is turned on by applying "1" to the gate. However, the depletion type transistor 266b has a gate voltage of "0" because its threshold voltage is negative.
But even "1" turns it on. Therefore, the transistor pair 266 is turned on, which means that they match.

On the contrary, when "0" is input to the input signal line 268, the positive logic line 268a becomes "0" and the enhancement type transistor 266a is turned off. That is, the transistor pair 266 is turned off, which means that they do not match. In this way, the data can be defined depending on which one of the transistor pair 266 is the enhancement type transistor 266a, and it is possible to detect the coincidence / non-coincidence with the input data. In the same figure (b), these pairs are connected in series like the same figure (a), the dynamic type NAND circuit is formed.

Here, by making both transistors of the transistor pair 266 a depletion type, this pair is turned on regardless of the input data, that is, a don't care state is defined. Further, in these examples, the data value is created in advance in the manufacturing process, but this is not always necessary, and the data may be composed of a rewritable SRAM, EPROM, E ² PROM, or the like. FIG. 11 shows an example of the SRAM type, but for simplification, an example in which only the portion corresponding to the enhancement type transistor 264 of the basic elements connected to the series of FIG. The part surrounded by the dotted line in the figure corresponds to that.

Internal nodes Q, Q of the normal SRAM 271
A transistor T3 and a transistor T4 are connected to _, and a transistor T5 is connected between both transistors connected to this series. The positive logic signal on the input signal line 268 is applied to the bit line 272a and the negative logic signal is applied to the bit bar line 278b. First, this SRAM 27
It is assumed that "1" data is held in 1. That is,
It is assumed that Q is "1" and Q_ is "0". If the input signal is "1" and coincides with the data held in the SRAM 271, the transistor T3 is turned on because Q = "1", and the input positive logic signal "1" changes the gate of the transistor T5. And the transistor T5 is turned on. The transistors T5 are connected in series to form a dynamic NAND, and therefore, when all the SRAM data match the input signal, the match output "1" is obtained from the dynamic sense amplifier 260.

The input signal is "0" and the SRAM
Similarly, when the data of 271 is "0", the transistor T4 in which the negative logic signal "1" is turned on at Q_ = 1
Is applied to the gate of the transistor T5 via. Further, when the data of the SRAM 271 and the input signal do not match, for example, when the input signal is “1” and the data of the SRAM 271 is “0” (Q = “0”, Q _ = “1”), the transistor is turned on. The negative logic signal "0" of the input signal is applied to the gate of the transistor T5 via T4 to be turned off. The same applies to the opposite case.

When detecting this match / mismatch, the SR
The word line 273 of the AM 271 maintains the state of "0". S
When writing data to the RAM 271, the word line 73
Then, the normal memory operation is performed, such as setting the state of "1". Next, FIGS. 12A and 12B show specific examples of the memory block 245 of the memory unit 244. Also here, the enhancement type memory transistor 281 is used (FIG. 2A) and the depletion type memory transistor 284a is used (FIG. 2B).
Examples are given.

First, in FIG. 9A, the gates of a plurality of enhancement type memory transistors 281 are connected to the same word line 243w for each memory block 245, and the feedback register control flag 245a, feedback data 245b, output The data 245c and the selector control flag 245d are configured. Each enhancement-type memory transistor 281 has a value of "1" or "0" depending on whether or not the connection portion 282 is connected to the bit line 280.
Is expressed. Here, the black circles of the connection portion 282 represent the connected state, and the white circles represent the disconnected state. Beyond this bit line 280 is the dynamic sense amplifier 26.
0 is formed. First, the control signal line 262 becomes "0", and each bit line 280 is precharged by the precharge transistor 62a. Word line 243 at this time
w is set to '0'. Next, the control signal line 26
When 2 becomes "1" and then the word line 243 becomes "1", each enhancement type memory transistor 28
1 turns on. As a result, the charge is discharged from the bit line in which the connection portion 282 is in the connected state via the enhancement type memory transistor 281, and the dynamic sense amplifier 260 detects this and outputs "1".
Is output. On the contrary, in the case where the connection portion 282 is in the non-connection state, the electric charge of the bit line 280 is held and the output becomes “0”.

In this case as well, the connecting portion 282 is often formed in a pattern in which the shape of the contact or the like remains, and there is a possibility that the data analysis will be performed by the disassembly examination. Therefore, also in this case, a circuit example based on the memory definition in which a shape change such as a threshold voltage change due to a difference in ion implantation amount or implantation impurities does not remain is shown in FIG. The basic memory 283 is composed of two transistors. A select transistor 284 and a memory transistor 285, which are connected in series. The memory transistor 285 is an enhancement type transistor 285.
There are two types, b and depletion type memory transistor 285a, which correspond to data "0" and "1", respectively.

That is, when the word line 243w becomes "1", all the select transistors 284 are turned on. At this time, the memory transistor 285 connected to the signal “0” obtained by inverting the word line 243w by the inverter 286 is divided into an enhancement type and a depletion type, which are turned off or turned on. That is, in the case of the depletion type memory transistor 285a, the precharged charge of the bit line 280 is discharged and the dynamic sense amplifier 260 outputs "1". On the other hand, in the case of the enhancement type memory transistor 285b, the electric charge of the bit line is held and "0" is output. However, in appearance, these transistors are exactly the same, which makes disassembly and investigation extremely difficult.

Of course, it goes without saying that the circuit system shown in the above-mentioned embodiment is only an example, and other known circuit systems may be used. Also, the process is not limited to ROM, but E ² PROM, flash RO
M, SRAM, etc. are not particularly limited. Further, in the above embodiment, the data flow control device 1 is provided separately from the ROM 4.
However, the data flow control device 10 may be incorporated in a memory device such as a ROM.

Next, the data flow control device 10 of the present invention.
A third embodiment will be described. As shown in FIG. 6, each data D shown in FIG. 6 is stored in the ROM 4, and here, as shown in FIG. 13, from the normal operation of the software, the input of the address data is performed. The order is A (n) → A (n + 1) → ... → A (j) → A
It is assumed that (j + 1) → A (j + 2) → A (k) → A (m). Here, of these address data, an array of address data {A
(N), A (j), A (k)} and an array {A (n), A obtained by adding address data A (m) to this array.
(J), A (k), A (m)} are focused on, and the distance between the address data forming these arrays is focused. Here, the “distance” indicates whether or not one particular address data of interest is input, then some address data is input, and then another address data of interest is input. Here, it is assumed that the distance from the input of the address data A (n) to the input of the next address data A (j) is unlimited. That is, the address data (j) may be input immediately after the address data A (n) is input,
The address data A (n) is input, and then the number of other address data is input, and then the address data A (n) is input.
(J) may be input. Further, regarding the address data A (j) and the address data A (k), the distance between them is 3, that is, there is a maximum of two other address data between the address data A (j) and the address data A (k). Is allowed to enter. Further, the address data A (k) and the address data A (m)
For, the distance is 1, that is, the address data A
No other address data should enter between (k) and the address data A (m).

In the order of the above arrangement and when the distance between the respective address data is satisfied, the data flow control device 1
Regular data D (k), D (m) stored inside 0
Are output in response to inputs of address data A (k) and A (m), respectively. On the other hand, in ROM4,
Data'BREAK1''BREAK2 'which causes a system down is defined in each address A (k), A (m).

FIG. 13A shows an address processing procedure and its output data when the control system is operating by such software. That is, except for the address data A (k) and A (m), the data stored in the ROM 4 is output, but the address data A (k),
When A (m) is input, 'BREAK1''BREAK2' for shutting down the system is not output from the ROM 4, but instead the normal data D (k), D (from the data flow controller 10 is output. m) is output,
Normal operation continues. However, when illegal data copying is performed, regardless of this actual software processing procedure, in other words, the flow of a legitimate address, for example, the addresses are sequentially input, and the output data corresponding to each input address is output. Will be read. The data output corresponding to each address in this case is as shown in FIG.
As a result, only'BREAK1''BREAK2 'can be obtained as the data for the addresses A (k) and A (m), and even if an attempt is made to operate the software with such data, the system goes down at some point and becomes inoperable. become.

As described above, here, the discontinuity of the address existing when the actual software operates and the relation of the address that data from a plurality of addresses are required for a series of processing are related. We pay attention to two points.
From this point, the output data of a specific address is associated not only with the address data input most recently or at that time, but also with the address data input before that, and the combination of these multiple address data is used as key data. As data, the data corresponding to the key data is stored in the data flow control device 10, while the normal ROM is used.
Dummy data (data of'BREAK1 'and'BREAK2' that bring down the system in the above example) is put in No. 4. By doing this, unless you are a developer who knows all the processing steps of software, you do not know at all whether it is dummy data or what the key data is.

Further, in this embodiment, three pieces of address data A (n) and A (j) and three address data of own address A (k) and data D (m) are used as key data of data D (k). The order in the four address data of the address data A (n), A (j), A (k) and the own address data A (m) as key data and the distance between the addresses (including unlimited distance) Is defined, and the normal data D (k), D (m) correspond to the input of address data A (k), A (m), respectively, depending on the generation order of these three or four address data and their distances. And output it. Of course the three or four shown on this side
Not only the arrangement of one address data, but also an arbitrary number and an arbitrary place are selected from a plurality of addresses accessed for performing a series of processing, and dummy data is stored in the ROM 4
In addition, it is possible to input the regular data and the key data thereof to the data flow control device 10. Further, here, the address distance may be within a certain setting range, which facilitates the setting. Making illegal copying even more difficult by changing the number of address data defined as this key data or increasing the number of regular data to be replaced by increasing the number of each key data. You can

Next, the third embodiment of the data control device 10 of the present invention will be described.
The circuit configuration of the embodiment will be described with reference to the block diagram of FIG. 14 and the timing chart of FIG. First,
Address data is input to the match detection unit 341 via the address line 7 shown in FIG. At the same time, the feedback register 34
The data stored in No. 2 is input to the coincidence detection unit 341, and the word line 343w of the coincidence block 343 that coincides with both the data stored in the feedback register 342 and the address data is activated. As a result, the memory block 345 just beside it is selected.

Each memory block 345 has a counter set flag 345a and a counter enable flag 345.
b, feedback data 345c, counter data 345d, output data 345e, and selector control flag 345f.
Is made up of. The matching block unit 343 includes an address data matching unit 343a and a feedback data matching unit 343.
Has become

First, the address data A (n) is input to the coincidence detection unit 341 via the address line 7. At this time, the address data A is stored in the address data matching unit 343a of the fourth matching block unit 343 of the matching detection unit 341.
(N) is included. The feedback data matching unit 343b of the fourth matching block unit 343 is set to the don't care state (a state in which any data is considered to match). As a result, a match occurs in the fourth match block unit 343, and the word line 343 of the match occurs.
w becomes active, the fourth memory block 345 located right beside in the figure is selected, and its stored data is output. Since the selector control flag 345f of this stored data is "0", the selector 346 causes the data line 308
The output signal from the ROM 4 input via a is output to the data line 8.

The counter set flag 345a is also set to '
Since it is 1 ', the value' 1 'read from the feedback data 345c is stored in the feedback register 342 at the rising edge of the feedback register control signal (time T1 in FIG. 15). At the same time, “*” of the counter data 345d is input to the counter 352 at the rising timing of the count set signal (this count set signal is a signal obtained by delaying the output of the counter set flag 345a by Δt2). Here, the value “*” of the counter data 345d means that the value may be any value. The value may be anything because the counter enable flag 345b is "0", and therefore the output signal to the feedback register 342 is "1" regardless of the state of the counter 352. Therefore, until the next address data A (j) forming the above-described array is input, the feedback register 342 is input.
It becomes possible to hold the value of
(N) and A (j) are independent of the distance.

This feedback register 342 and counter 352
Will be specifically described with reference to FIG. Feedback register 34
Reference numeral 2 is composed of a plurality of flip-flops 390 and an input data control circuit 391.
Output Q is fed back to the input data control circuit 391. In addition, the input data control circuit 391 has 2
There is a street input.

One of them is the feedback data 345c,
This feedback data 345c is the counter set flag 345.
a is “1” or the output of the counter 352, that is, the OR circuit 3
When the output from 95 is '0', the rising timing of the feedback register control signal (for example, time T1, T2 in FIG. 15,
(T3, T4, etc.) at the feedback register 342. The other is the feedback data from the flip-flop 390, which is the counter set flag 345a.
Is "0" and the output of the counter 352 is "1", the feedback input is performed at the rising timing of the feedback register control signal as in the above, and the data up to that point is held as it is.

This feedback register control signal is output from the control circuit 349 of FIG. 14, which is generated from the ATD output for detecting the change of the address input via the address line 7. Further, the control signal is delayed by Δt1 and inverted (see FIG. 15). As for the counter 352, the counter set flag 345
The counter data 345 is generated at the rising edge of the counter set signal obtained by delaying the signal a (see FIG. 14) by Δt2.
The value of d is input to the counter circuit 392. The control signal counter circuit 392 is connected to the countdown terminal (countdown) every time the address data is input.
Count down by 1 '.

The logical sum of the outputs of the counter circuit 392 is calculated by the OR circuit 393, and the output thereof is the OR circuit 395.
Has been entered in. The output of the flip-flop 394, to which the counter enable flag 345b is inverted by the inverter 394a and input, is input to the OR circuit 395. Also, the value of the counter enable flag 345b is input to the flip-flop 394 at the rising timing of the counter set signal, and when the value of the flip-flop 394 is "0", that is, the counter is disabled, the OR circuit 395 outputs the value. , Feedback register 34
Output '1' to 2. As a result, unless the counter set flag 345a is "1", the flip-flop 39
The Q output of 0 is held as feedback.

Further, the counter enable flag 345b
Is “1” and the counter 352 is enabled (when the output of the flip-flop 394 is “0”), when one of the outputs of the counter circuit 392 is “1”, the output of the OR circuit 395 is “1”. Similarly, the Q output of the flip-flop 390 is feedback-held. The above is the outline of the feedback register 342 and the counter 352. As can be seen from this description, once the counter enable flag '0' is taken in, the counter 3 is not operated until the address data A (j) expected to be input next is input.
Feedback register 3 regardless of the countdown operation of 52
42 continues to hold the same value.

Next, the operation when the address data A (j) is input will be described. Feedback register 3 at this time
Since '1' has already been input and held in 42, a match occurs in the second matching block in FIG. 14 in the same manner as described above, the word line 343w becomes active, and the memory block directly next to it is activated. 345 to “1” of the counter set flag 345a, counter enable flag 3
'1' of 45b, '2' of feedback data 345c and '3' of counter data 345d are output. However,
Also at this time, the selector control flag 345f is "0",
The output data, which is always input from the ROM 4 to the selector 346 via the data line 308a, is output from the data line 8.

Here, since the counter set signal generated from the counter set flag 345a becomes "1", "2" of the feedback data 345c becomes "2" at the rising timing of the feedback register control signal (time T2 in FIG. 15). 342 and the counter data 3
'3' of 45d is input to the counter 352. Also,
Since the counter enable flag 345b is "1", the output of the flip-flop 394 in FIG. 16 is "0", and thus the feedback register 342 is controlled by the signal from the counter circuit 392 this time.

When the next address is input, the counter 352 (FIGS. 14, 15 and 16) is generated at the rising edge of the control signal.
The value of (see) is counted down by one and becomes “2” (between time T2 and T2 + 1 in FIG. 15). Further, the next address data is input, and the feedback register control signal rises at time T2 + 1. At this time, the counter set flag 3
45a is "0" and the output from the counter 352 is "0".
Since it is 1 ', the output of the flip-flop 390 of the feedback register 342 is fed back as it is and holds the previous data (see FIG. 16). From time T2 + 1 to T
At the rising edge of the control signal between 2 + 2, the counter 352
Is counted down to '1'.

Similarly at time T2 + 2, the feedback register control signal rises, but at this time, the value of the counter 352 is'
1'and the counter set flag 345a is '0'
Therefore, the previous data is retained. next,
At the rising edge of the control signal from time T2 + 2 to time T3, the counter 352 counts down to "0", and the output from the counter 352 to the feedback register 342 becomes "0". However, the address data at this time has the expected value. A (k), the counter data 345d'1 'and the counter enable flag 34 at the rising edge of the counter set signal.
5b'1 'is set. At this time, since the selector control flag 345f is "1", the output data 34
5d D (k) is the output data BRBAK from ROM4
Instead of 1, it is output from the data line 8 via the selector 345. Further, '3' of the feedback data 345c is input and held in the feedback register 342 at the rising edge of the feedback register control signal at time T3.

Further, the timing of the rising edge of the control signal between time T3 and time T4, the counter 352 is counted down to "0", and the selector control flag 345f is set to "0".
Since it is 1 ', the output data B from the ROM 4 is also
The data D (m) is replaced by the selector 346 instead of the REAK2.
Is output from the data flow control device 10 via the.

Next, at the rising edge of the feedback register control signal at time T4, since the output from the counter 352 is "0", the value "0" of the feedback data 345c is input and held in the feedback register 342. Further, in the counter 352 and the flip-flop 394 of the counter enable flag 345b, the counter set flag 345a is "0".
Therefore, the state of '0' will be maintained.

The above is the outline of the operation. It is the counter 352 that determines the distance n (integer) between the two input expected address data. However, when the expected address data is input within this n-th position, FIG. Of the feedback data 34, which constitutes the input data control circuit 391 of the feedback register 342 of
The circuit for controlling the 5c input is the output of the counter 352,
Since it is the OR circuit 391b that calculates the logical sum of the counter set flag 345a, if the expected address data is input within this nth, it becomes the same as when it is input exactly at the nth. On the contrary, in the case of being input after the (n + 1) th, the feedback data after the output of the counter 352 becomes “0” and the expected address data is not input, that is, “0” is input to the feedback register 342. It will be.

As described above, the output data is not determined only by the address input at that time, but for a specific address, it is determined by the address sequence and the distance at the time of executing the software input before that. By determining the output, copying in an illegal address operation is prevented. Also, as shown in this example,
For example, even if one or a plurality of unexpected address data comes after the address data A (n),
Since it is configured so that it can always wait for the next key, the prefetch of data by consecutive addresses without considering the processing procedure of software by the prefetch operation of the CPU for speeding up processing in recent years It is possible to extract appropriate key data and output regular data without malfunctioning.

The match block 343 of the match detection unit 341 and the memory unit 34 in the third embodiment shown in FIG.
Although the specific circuit of the memory block 345 of No. 4 is not particularly limited, for example, it can be configured in the same manner as the specific circuit shown in the second embodiment described above (FIG. 10).
(A), (b), FIG. 11, FIG. 12 (a), (b) reference).

Next, a fourth embodiment of the data flow control device of the present invention will be described. First, in ROM4,
As shown in FIG. 17A, each data D shown in the drawing is stored according to each address A, and the data flow control device 1
0 also stores the data shown in FIG. ROM4
Is input with address data from the address line 7 through the data flow control device 10. Similarly, ROM
The output data from 4 is output to the data line 8 via the data flow control device 10. Of course, all or part of the address line 7 or part of the data line 8 is directly RO
It may be connected to M4.

Next, an example of operation during actual software execution will be described. In particular, this embodiment will be described from the point of "address multiplexing", in which a plurality of data are associated with the same address. First, during certain software processing, the address is A (j) → A (j +
2) → A (k) → A (k + 1) is accessed. This access procedure is shown in FIG. 18 (a).
Are attached numbers (1) to (4). At this time, the data corresponding to each address is output from the normal ROM 4.

Here, it is assumed that the data of the address A (j) corresponds to the judgment part of the conditional jump,
The above-mentioned first case is assumed to be a case where no jump has occurred. On the other hand, in the case of FIG. 18B, the second order indicating the order of address access when a conditional jump occurs
A (j) → A (j + 1) → A (m) →
A (m + 1) → A (k) → A (k + 1).

In the first case (FIG. 18 (a)), the addresses A (k) and A (k + 1) correspond to the data (k, 1) and D (k + 1, 1), respectively. , Second
In the case (Fig. 18 (b)), the same address A (k),
A (k + 1) has different data D (k,
2) and D (k + 1, 2) correspond to each other. Therefore, the data D (k, 2), D (k + 1,2) corresponding to the addresses A (k), A (k + 1) in the second case are stored in the data flow control device 10, and The order in the case, that is, A (j) → A (j
+1) → A (m) → A (m + 1) → A (k) → A (k +
When accessed in the order of 1), the address A (k),
Corresponding to A (k + 1), the data of the data flow control device 10 is output instead of the contents of the ROM 4.

Here, among the addresses of the second case, in particular, {A (j), A (m), A (k), A (k +
1)} address appearance order and the distance between the addresses. Here, the “distance” indicates that one address data of interest is input, and then the number of address data is input and then the other address data of interest is input. Here, after the address data A (j) is input, the next address data A
It is assumed that the distance until (m) is input is unlimited.
That is, the address data (m) may be input immediately after the address data A (j) is input, the address data A (j) is input, and then the number of other address data is input and then the address data is input. A (m) may be input. The distance between the address data A (m) and the address data A (k) is 3,
That is, the address data A (m) and the address data A
A maximum of two other address data are allowed to enter between (k). Furthermore, regarding the address data A (k) and the address data A (k + 1),
The distance is 1, that is, other address data should not enter between the address data A (k) and the address data A (k + 1).

When each address data is input in the order of the above arrangement and the distance between each address data is satisfied, the data D (k, 2), D (k + 1) stored in the data flow control device 10 is stored. , 2) are output in response to inputs of address data A (k) and A (k + 1), respectively. On the other hand, in the ROM 4, each address A
Program data D (k, 1) and D (k + 1,1) on the other branch side described above are defined in (k) and A (k + 1), respectively.

As described above, also in the present embodiment, the discontinuity of the addresses existing when the actual software operates and the address discontinuity that data from a plurality of addresses are required for a series of processing We pay attention to two points of relevance. From this point, the output data of a specific address is associated not only with the address data input at the latest or at that time, but also with the address data input before that, and the combination of these multiple address data is used as key data. As a result, data corresponding to the key data is stored in the data flow control device 10, while data of another software flow is put in the normal ROM 4 to multiplex the address. By doing so, unless the developer knows all the processing procedures of the software, he / she cannot know the multiplexed address address and the data content thereof. It is also assumed that the key data corresponding to the multiplexed address is unknown. Further, in this embodiment, as the key data of the data D (k, 2), the three address data of the address data A (j), A (m) and the own address A (k), and the data D
Address data A as (k + 1, 2) key data
(J), A (m), A (k) and its own address data A (k + 1) in the four address data and the distance between each address (including unlimited distance) are defined. Address-multiplexed data D depending on the generation order of these three or four address data and their distances.
(K, 2) and D (k + 1, 2) are the address data A, respectively.
(K) and A (k + 1) are output corresponding to the input. Of course, the arrangement is not limited to the arrangement of the three or four address data shown in this example, and an arbitrary number and an arbitrary place can be selected from a plurality of addresses accessed for performing a series of processing, and address multiplexing can be performed. It is possible to store the data of a certain process in the ROM 4 and the data of another process and its key data in the data flow control device 10. Further, here, the address distance may be within a certain setting range, which facilitates the setting. The number of data multiplexed by increasing the address multiplexing rate, changing the number of address data defined as key data corresponding to each processing data, and increasing the number of key data By increasing the number, illegal copying can be made more difficult.

As described above, the present invention is not limited to the point of view of erroneous data that causes a malfunction such as system down when the data is not read in the normal flow as described in the first to third embodiments. As shown in the fourth embodiment, it can be configured from the viewpoint of address multiplexing. Even when the present invention is configured from the viewpoint of address multiplexing, only the data stored in the ROM 4 or the data flow control device 10 is different, and the specific hardware of the data flow control device 10 is as described above. First
The configuration of the third embodiment (see FIGS. 4, 8 and 14) can be adopted as it is.

Here, in the case where the insertion of the address data which does not form the array between the address data which forms the array is allowed and the concept of the distance is introduced between the address data which forms the array, the circuit is explained. Although the configuration overlaps with the case of the third embodiment (see FIG. 14) described above, an example of the circuit configuration will be described from the viewpoint of address multiplexing with reference to the block diagram of FIG. 19 and the timing chart of FIG. To do.

First, an address signal is input to the coincidence detecting section 341 via the address line 7 shown in FIG. At the same time, the data output signal of the feedback register 342 is input to the coincidence detection unit 341, and the word line 343 of the coincidence block 343 that coincides with both the data output signal and the address signal.
w becomes active. As a result, the memory block 45 right next to it is selected.

Each memory block 345 has a counter set flag 345a and a counter enable flag 345.
b, feedback data 345c, counter data 345d, output data 345e, and selector control flag 345f.
Is made up of. The matching block 343 includes an address data matching unit 343a and a feedback data matching unit 343b.
Is made up of.

First, the address data A (j) is input to the coincidence detection unit 341 via the address line 7. At this time, the address data A is stored in the address data matching unit 343a of the fourth matching block 343 of the matching detection unit 341.
(J) is included. The feedback data matching unit 343b of the fourth matching block 343 is set to the don't care state (a state in which any data is considered to match). As a result, a match occurs in the fourth matching block 343, the word line 343w thereof becomes active, the fourth memory block 345 right next to the drawing is selected, and its stored data is output. Since the selector control flag 345f of this stored data is "0", the selector 46 operates the data line 108a.
The output signal from the ROM 4 input via the is output to the data line 108.

At this time, at the rising edge of the feedback register control signal (time T1 in FIG. 20), the value "1" read from the feedback data 345c is stored in the feedback register 342.
At the same time, the counter set flag 345a is also "1".
Therefore, “*” of the counter data 345d is input to the counter 1342 at the rising timing of the count set signal (this count set signal is a signal obtained by delaying the output of the counter set flag 345a by Δt2). Here, the value of this counter data 345d '
* 'Means that the value can be anything. It does not matter what value the counter enable flag 345b has.
Is “0”, and therefore the output signal to the feedback register 342 becomes “1” regardless of the state of the counter 1342. Therefore, the value of the feedback register 342 can be held until the next address data A (m) forming the above-described array is input, and the key addresses A (j) and A (m) are separated by a distance. Will be irrelevant to.

This feedback register 342 and counter 352
16 is the same as that shown in FIG. 16 and its description is omitted. Next, the operation when the address data A (m) is input will be described. At this time, the feedback register 342 has already been set to '
Since 1'is continuously input and held, a match occurs in the second matching block in FIG. 19 in the same manner as described above, the word line 343w becomes active, and the counter set flag from the memory block 345 right next to it becomes active. 345
a of "1" and counter enable flag 345b of "
1 ', feedback data 345c' 2 'and counter data 345d' 3 'are output. However, even at this time, the selector control flag 345f is "0", and the selector 34 is still unavoidable from the ROM 4 via the data line 308a.
The output data input to 6 is output from the data line 8.

Since the counter set signal generated from the counter set flag 345a becomes "1", the feedback register control signal rises (see FIG. 20).
At time T2), "2" of the feedback data 345c is input to the feedback register 342, and at the same time, "3" of the counter data 345d is input to the counter circuit 392.
Further, since the counter enable flag 345b is "1", the output of the flip-flop 394 in FIG. 16 is "1".
Therefore, the feedback register 342 is controlled by the signal from the counter circuit 392.

When the next address data following the address data A (m) is input, the value of the counter circuit 392 (see FIGS. 19, 20 and 16) is decremented by 1 at the rising edge of the control signal. 2 '(between time T2 and T3 in FIG. 20). At this time, counter set flag 3
45a is "0" and the output from the counter 352 is "0".
Since it is 1 ', the output of the flip-flop 390 of the feedback register 342 is fed back as it is and holds the previous data (see FIG. 16).

Further, at time T3, the next address data is input, which causes the feedback register control signal to rise. At this time as well, the value of the counter 352 is "2" and the counter set flag 345a is "0". Since it exists, the previous data is retained. Immediately after that, at the rising edge of the control signal, the counter 352 counts down to "1", but the address data at this time is the expected value A.
(K), the counter data 345d′1 ′ is newly set in the counter circuit 392 at the rising edge of the counter set signal, and the counter enable flag 345b′1 ′ is inverted and set in the flip-flop 394. At this time, the selector control flag 34
Since 5f is '1', D of the output data 345e
(K, 2) is the output data D (k, 1) from the ROM 4.
Instead of, the data is output from the data line 8 via the selector 346. Also, '3' of the feedback data 345c is input and held in the feedback register 342 at the rising edge of the feedback register control signal at time T4.

Further, the address data A (k + 1) is input, the counter circuit 392 is counted down to "0" at the timing of the rising edge of the control signal between time T4 and time T5, and the counter circuit 392 is placed right beside the Nth matching block 343. Since the contents of the memory block 345 of No. 4 are read and the selector control flag 345f is “1”, the data D instead of the output data D (k + 1,1) from the ROM 4 is also changed.
(K + 1, 2) is output from the data flow control device 10 via the selector 346.

Next, at the rising edge of the feedback register control signal at time T5, since the output from the counter 352 is "0", the value "0" of the feedback data 345c is input and held in the feedback register 342. In addition, the counter circuit 39
Since the counter set flag 345a is "0", the second and flip-flops 394 maintain the state of "0" up to that point.

The above is the outline of the operation. It is the counter 352 that determines the distance n (integer) between the two input expected address data, but the circuit that controls the input of the feedback data 345c that constitutes the input data control circuit 391 of the feedback register 342 in FIG. Since it is the OR circuit 391b that calculates the logical sum of the output of 352 and the counter set flag 345a, even when the expected address data is input at a shorter distance than this distance n, it is input at exactly the distance n. It will be similar to the case. On the other hand, when the n + 1th and subsequent signals are input, the output of the counter 352 is'
The feedback data after being 0 ', where the expected address data is not input, that is,' 0 'is input to the feedback register 342.

Thus, the output data is not determined only by the address input at that time, but for a specific address, it is determined by the address sequence and the distance at the time of executing the software input before that. By determining the output, copying in an illegal address operation is prevented. Further, in this example, as in the third embodiment described above, even if one or a plurality of unexpected address data comes after the address data A (j) or the like, the next key is always used. Since it is configured to be able to wait, it does not malfunction even when prefetching data at consecutive addresses that does not consider the processing procedure of software due to the prefetch operation of the CPU in recent years for speeding up the processing. It is possible to extract various key data and output regular data.

In the following, specific scenes of the program that can be incorporated in the data flow control device or the memory device of the present invention to prevent illegal copying will be introduced with the game program in mind. FIG. 21 is a diagram showing a storage address and a mnemonic of a program including a jump instruction.

'BE stored at address'9000'
Q 9013 'is an instruction indicating that if a certain bit in a certain status register is'0', it jumps to the address' 9013 ', and otherwise executes the next instruction in the address order. The'JMP a000 'stored in the address'9010' is an instruction to unconditionally jump to the address'a000 ', the address' 902.
'BNE 9013' stored in 0'is '90 unless a bit in a status register is '0'.
The instruction jumps to the address 13 ', and if it is'0', it indicates that the next instruction according to the address order is executed.

In this program flow, the address' 9
To 013 ', address'9000' or '9020'
There is a path that jumps from, but there is no path from the address immediately before it. In this case, '..., 9000, 90
By adopting 13, ... 'Or' ..., 9200, 9013, ... 'as an array of address data (key data), a correct instruction (data) is output only when accessed in the array order. can do.

Here, only when the data is accessed according to the address order (or the address order and the distance) registered in advance as the key data, the data stored in the address '9013', for example, the value '0' is stored in the accumulator.
The instruction'LDA # 00 'which means to store 0'
Is output, the game operates normally, and the most interesting play intended by the game creator can be performed. On the other hand, when access is made in violation of the registered key data, the instruction “LDA # 33”, which means storing the value “33” in the accumulator, for example, is output as the data at the address “9013”, As a result, the game operation thereafter becomes abnormal or the fun of the game is reduced. The feature of this example is that the instructions are the same and only the operands are different. Such a copy protection measure is easy to create, while it is difficult to analyze where the error is, what the correct operand value is, etc. Therefore, illegal copying is difficult.

FIG. 22 is a diagram showing storage addresses and mnemonics of a program including a subroutine call instruction and a return instruction from a subroutine. address'
'JSR 92 stored in 9000', '9100'
01 'is a subroutine call instruction for instructing to execute a subroutine starting from address' 9201 ', and'RTS' stored at address '9300' is a return instruction for instructing return from the subroutine. In addition, the'R stored at the address '9200'
TS 'represents an instruction that directs the return of another subroutine.

In this program flow, address' 9
To 201 '(entry point of subroutine),
There is a path from address '9000' or address '9100', but no path from the previous address. That is, there is an address discontinuity on the program flow between addresses '9200' and '9201'. Therefore, '..., 9000, 9201, ...' Or '
, 9100, 9201, ... ′, etc., can be arranged so that a correct instruction (data) is output only when accessed in the order of arrangement.

Further, in this program flow, the address' 9003 'or address'9103' (the point immediately after the subroutine call instruction) is addressed to the address'
There is a path coming from 9300 ', but the address is' 900
There are no paths from 0'to '9100'. That is,
There is an address discontinuity on the program flow between addresses '9000' and '9003' and between addresses '9100' and '9103'. Therefore, '..., 9300, 9003, ...' Or '..., 93
By setting 00, 9103, ... 'And the like as an array of address data, a correct instruction (data) can be output only when accessed in the array order.

Here, only when it is accessed according to the address order (or the address order and the distance) registered in advance as the key data, the data of the address '9210', for example, '00' is stored in the accumulator value. The command'LDA # 00 ', which means, is output and the game continues normally. On the other hand, if an access is made in violation of the registered key data, the address '92
As the data of 10 ', for example, the return instruction'RTS' from the subroutine is output, the subroutine processing ends midway and returns, and the operation of the game thereafter becomes abnormal. Generally, it is not uncommon for multiple return instructions to exist even in one subroutine, so even if the return instruction'RTS 'exists at address'9210' in the illegally copied data, it feels strange. I can't. Therefore, also in this case, it is difficult to analyze the copy data. On the other hand, such a copy protection measure is also easy to create.

FIG. 23 is a diagram showing a storage address and a mnemonic of a program including an instruction for designating a start point of the program when an interrupt or a reset is input. Address'fffe ',' fffc '
Stored in'dw irq_int ',' dw s
In start ', programs executed at interrupt input and reset are irq_int (address' 8100 ') and start (address' 800, respectively).
0 ').

In this program, there is a path from the address'fffc 'in which the address value is stored to the start point' 8000 'at reset, but there is no path from the immediately preceding address. That is, there is an address discontinuity on the program flow between the address '8000' and the address '7fff' immediately before it.

Therefore, 'fffc, 8000, ...'
Is set as an array of address data, so that a correct instruction (data) can be output only when accessed in the array order. The same is true for interrupts. Here, only when the address is accessed in accordance with the address order (or the address order and the distance) registered in advance as the key data, the data of the address '8000' to the address '8100', for example, the memory address '2000' in the memory, The command'STZ 2000 'for zero-clearing the contents of is output. On the other hand, when an access is performed in violation of the registered key data, an instruction "STZ 2010" for clearing the contents of another memory address "2010" in the memory to zero is issued as the data of address "8000" or address "8100". It is output, and the subsequent game operation becomes abnormal.

Generally, the memory space is often initialized immediately after the program is started. Therefore, as shown in this example, if the memory area to be initialized and the initial value are made different, different operations will be performed, one of which is a normal operation, the other of which is an incorrect operation or a game operation which is interesting but not so much. You can also do it. In such a case, it is difficult to analyze where and how the illegally copied data is erroneous. Conversely, such copy protection can be easily created.

FIG. 24 is a diagram showing storage addresses and mnemonics of a program including a data fetch instruction.
'LDA [1 stored at address'9000'
0], Y ′ is an instruction indicating that “10” is added to the value of the direct register, and the data stored at the address formed by adding the value of the Y register is loaded. For example, when the address "9000" is reached, "a000" is stored in the direct register and Y
If 100 'is stored in the register, the added address becomes'a110'. Therefore, in this program flow, addresses' 9000 ',' 900
After the 1 ', the address'a110' appears. That is, the address'a110 'and the address'a1 immediately before it.
There is a discontinuity in the program flow between 0f '. Therefore, by setting '..., 9000, a110', etc. as an array of address data, a correct instruction (data) can be output only when accessed in the array order.

In this case, depending on whether or not the access is performed according to the registered key data, the address'a11
As the data of 0 ', for example, the correct value of' 8 '
0 ', an incorrect value'ff' is output. Unlike the opcode area, there is nothing unnatural about the presence of any value of data in the data area, so in this case,
It is extremely difficult to judge whether the value of the data read from the address'a110 'is incorrect.

FIG. 25 (a) is a diagram showing the storage address and mnemonic of a program including a subroutine call instruction and a branch instruction, and FIGS. 25 (b) and 25 (c) are stored in the data flow controller 10. It is a figure which shows the erroneous data produced. As key data, for example, '9000,9
202 'and' 9000, 9202, 9210, 921
Two sequences of 8'that partially overlap each other are registered. '
LDA 'is a 2-byte instruction, and when an access is performed according to this registered key data, the address'
As the values stored in 9202 'and' 9218 ', FIG.
Correct data # 00, # 00 as shown in 5 (a) is output. On the other hand, if the address '9202' appears opposite to the registered key data, then FIG.
Wrong data #ff and # 88 as shown in FIG. Even if the address '9202' appears according to the registration key data, the address '9202' will be displayed.
When 218 'appears opposite to the registered key data, erroneous data # 88 as shown in FIG. 25C is output for the address'9218'.

As shown in this example, by registering a plurality of arrays (key data) in which array elements partially overlap, some of the plurality of protects composed of those key data are broken. (It was copied correctly)
Even so, there will be another protection after that, which will increase the difficulty of analyzing and copying what is a correct program.

Next, the viewpoint of address multiplexing will be described. FIG. 26 is a diagram showing a program flow in which instructions are multiply arranged between the address '9000' and the address '90ff'. Address' 90f
'JMP 9 stored in 3 bytes from d'to 90ff'
000 'represents an instruction unconditionally branching to the address'9000', and as an array of address data, for example, '..., 9000' ..., 90fd, 9000, ..., 9
0 fd, 9000, ..., 90 fd, 9000, ..., 90
By adopting fd, ..., As shown in FIG. 26, it is possible to multiplex the instructions between the address '9000' and the address '90ff'. In this case, if the address is simply read out in the order of addresses, only the first one of those multiplexed is read out, and even if the read program is executed, it does not operate normally.

In this example, the address '9000' to the address '90fd' are repeatedly used four times. '
LDA 'is a 2-byte instruction. For example, "LDA # 00" and "LDA" are assigned to the first, second, third and fourth addresses'9000' and '9001', respectively.
# 2a ',' LDA # 0f ', and'LDA #ee' are defined. In this case, as the data of the address '9001', a different value depending on the case is input to the accumulator. If the access is not based on the key data, the first data of the address'9000''LDA
Only # 00 'is output. Also in this case, the analysis is extremely difficult.

FIG. 27 shows a case in which the instructions are arranged in multiples in FIG.
A program that is more complex than the program flow shown in 6
It is a figure which shows a flow. As an array of address data,
For example, '..., 9000, ..., 901d, 9020,
..., 903d, 9040, ..., 905d, 9020,
..., 903d, 9000, ..., 901d, 9040,
, 905d, ... ′, etc., the multiplexing shown in FIG. 27 is realized.

FIG. 28 is a diagram showing another example of the program flow. BEQ, BNE, and BCC are all mnemonics indicating branch instructions. As an array of address data (key data), for example, '..., 9000, 9
030, ... ',' ..., 9010, 9030, ... ','
, 9020, 9030, ... ′ And the like, the multiplexing shown in FIG. 28 (a) is realized.

28 (b) to 28 (e) are diagrams showing an example of the inside of the broken line block in FIG. 28 (a). "JSR" is a subroutine call instruction, and "BRA" is an unconditional branch instruction. 28 (b), (c), (d), and (e) show that there are one subroutine call, five subroutine calls, three subroutine calls, and no subroutines to call. That is, in this example, the subroutine to be called differs depending on which registered key data the access follows. It is extremely difficult to analyze what scene is called and what subroutine is called so that the game can be played correctly. Therefore, exact copying is difficult.

FIG. 29 (a) is a diagram showing another example of the program flow. As an array of address data, for example, '..., 9000, 9030, ..., 93f
f, ... ',' ..., 9010, 9030, ..., 93ff,
... ',' ..., 9020, 9030, ..., 93ff,
... ',' ..., 902f, 9030, ..., 93ff, ... '
By adopting, for example, the multiplexing shown in FIG. 29 (a) is realized.

29 (b) to 29 (e) are diagrams showing an example of the inside of the broken line block in FIG. 29 (a). 'STA' is an instruction to store the data stored in the accumulator in memory, 'BNE' is a conditional branch instruction, 'CMP'
Indicates a comparison instruction, 'STZ' indicates an instruction for clearing the memory to zero, and'LDY 'indicates an instruction for loading a value into the Y register.

In this example, a plurality of patterns of data exist in the area after the address '9030', and completely different processing is executed depending on which registered key data is used for the access. It is difficult to analyze what kind of processing should be executed in any case so that the game can be played correctly, and thus copying is difficult. 30 and 31 show examples of program flows including a subroutine call instruction (JSR).

Similarly to the branch instructions shown in FIGS. 28 and 29, when a subroutine call instruction is used, the array of address data is similarly defined. FIG. 32 is a diagram showing storage addresses and mnemonics of a program including a subroutine call instruction and a branch instruction. Here, as the key data (array of address data), for example, '900
0, 9300, ..., 9700, ... ',' 9100, 93
00, ..., 9500, ... ',' 9200, 9300,
..., 9500, ... ',' 92ff, 9300, ..., 94
00, ... 'Is registered.

In this example, the address area '9300'
~ '93ff' is multiplexed, and different data is output depending on where it is called from. The address areas '9500' to '95ff' are also multiplexed, and different data is output depending on where the branch is from. When an address is sequentially incremented and copying is attempted, '93ff, 9300, ..., 940
Since it is accessed according to the registration key data of 0, ..., In the address areas' 9300 'to' 93ff ', the data of the block a in the figure, the address areas'9500' to '
At 95ff ', only the data of the block e in the figure is output.

If there are a plurality of multiplexed regions in this way,
Parsing and copying is almost impossible.

[0154]

As described above, the present invention utilizes the actual processing flow of software to store dummy data at a specific address and to store normal data corresponding to the specific address. It is configured so that only the developer who knows the actual flow of software can store it in correspondence with a combination of a plurality of address data, and only when the combination is given, the regular data is output. Therefore, it is possible to prevent illegal copying.

Further, in the present invention, it is possible to allow the insertion of the data that does not form the array between the data that form the array, and further to define the distance between the data that forms the array. In these cases, the present invention is also suitable for a system in which a hardware operation, such as a prefetch operation, that ignores software processing procedures is performed.

Further, according to the present invention, the actual processing flow of software is used to perform the address multiplexing for giving the same address to each specific processing in different processing flows.
One of the specific processes to which the same address is given is stored as key data, which is the processing procedure of multiple address data that can be known only by the developer who knows the actual flow of software, and the array Can be configured to output the data of the specific processing corresponding to one of them only when given within a predetermined distance or within the predetermined distance, and in this case also, it becomes possible to prevent illegal copying.

When the present invention is adopted, copy protection can be performed without making any changes to the external terminals of the cassette storing the software and the main body system other than the cassette. Its industrial utility value is extremely high. Of course, as mentioned above,
It goes without saying that the data flow control device may be incorporated in a ROM for storing software and used.

Furthermore, the present invention can be used for other security systems, and a similar data flow control device can be used for a game system using a CD-ROM or the like. The range of use is extremely wide.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a control system adopting an embodiment of the present invention.

FIG. 2 is a data storage diagram inside a ROM.

FIG. 3 is a flowchart of data output for address input.

FIG. 4 is a schematic circuit diagram of a first embodiment of the data flow control device of the present invention.

5 is a timing chart of the data flow control device shown in FIG.

FIG. 6 is a data storage diagram inside a ROM.

FIG. 7 is a flowchart of data output for address input.

FIG. 8 is a schematic circuit diagram of a second embodiment of the data flow control device of the present invention.

9 is a timing chart of the data flow control device shown in FIG.

10 is a diagram showing each circuit example of a match block of a match detection unit of the data flow control device shown in FIG.

11 is a diagram showing a circuit example in which a matching block of a matching detection unit of the data flow control device shown in FIG. 8 is configured by using SRAM.

12 is a diagram showing each circuit example of a memory block of a memory unit of the data flow control device shown in FIG.

FIG. 13 is a flowchart of data for address input.

FIG. 14 is a schematic circuit diagram of a third embodiment of the data flow control device of the present invention.

15 is a timing chart of the data flow control device shown in FIG.

16 is a diagram showing a configuration example of a feedback register and a counter of the data flow control device shown in FIG.

FIG. 17 is a data storage diagram inside a ROM and a data flow control device.

FIG. 18 is a flowchart of data output for address input.

FIG. 19 is a schematic circuit diagram of a fourth embodiment of the data flow control device of the present invention.

20 is a timing chart of the data flow control device shown in FIG.

FIG. 21 is a diagram showing a storage address and a mnemonic of a program including a jump instruction.

FIG. 22 is a diagram showing storage addresses and mnemonics of a program including a subroutine call instruction and a return instruction from a subroutine.

FIG. 23 is a diagram showing a storage address and a mnemonic of a program including a call instruction instructing a start point of the program when an interrupt or a reset is input.

FIG. 24 is a diagram showing a storage address and a mnemonic of a program including a data fetch instruction.

FIG. 25 is a diagram showing a storage address and a mnemonic of a program including a subroutine call instruction and a branch instruction.

FIG. 26 is a diagram showing an example of a multiplexed program program.

FIG. 27 is a diagram showing an example of a multiplexed program program.

FIG. 28 is a diagram showing an example of a multiplexed program program.

FIG. 29 is a diagram showing an example of a multiplexed program program.

FIG. 30 is a diagram showing an example of a multiplexed program program.

FIG. 31 is a diagram showing an example of a multiplexed program program.

FIG. 32 is a diagram showing an example of a multiplexed program program.

FIG. 33 is a block diagram of a conventional control system.

FIG. 34 is a data storage diagram inside a conventional ROM.

[Explanation of symbols]

4 ROM 7 Address line 8, 8a, 8b Data line 9 Cassette 10 Data flow control device 42a, 43a Output data line from ROM 42b, 43b Data output line of internal data of data flow control device 46 Selector 47 Shift register 241 Matching detection Part 242 Feedback register 243 Matching block 243a Address data matching part 243b Feedback data matching part 243w Word line 244 Memory part 245 Memory block 246 Selector 307 Address line 308 Data line 341 Matching detection part 342 Feedback register 343 Matching block 343a Address data matching part 343b Feedback data matching unit 343w Word line 344 Memory unit 345 Memory block 346 Selector 349 Control circuit 352 Counter

 ─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 5-178044 (32) Priority date Hei 5 (1993) July 19 (33) Country of priority claim Japan (JP) (31) Priority Claim number Japanese Patent Application No. 6-63347 (32) Priority date March 6 (1994) March 31 (33) Country of priority claim Japan (JP) (31) No. of priority claim Japanese Patent Application No. 6-63348 (32) Priority Hihei 6 (1994) March 31 (33) Priority claiming country Japan (JP)

Claims (29)

[Claims] 1. A first input device for sequentially inputting first input data
Input terminal, a second input terminal to which the second input data is sequentially input, an output terminal to which the output data is sequentially output, and one or more arrays of the plurality of first input data. Memory means for storing one or a plurality of replacement data defined correspondingly; and when the latest first input data is input from the first input terminal, the latest first input data is stored. The plurality of first input data, which includes the latest first input data and is traced back in the order of input, is input from the second input terminal according to whether or not it corresponds to any one of the arrays. First output data obtained by replacing at least a part or all of the bits of the second input data with the replacement data defined corresponding to the array, and the first output data input from the second input terminal. The second of the same logic as the input data of 2 Output data, a third output data generated by a logical operation based on the first output data, and a fourth output data generated by an operation based on both the first output data and the second output data. And a data switching means for outputting different data selected from the data group consisting of the output data of 1) as the output data from the output terminal. 2. The memory means includes one or a plurality of memory areas, and stores the replacement data in each of the memory areas, and the data means sequentially inputs from the first input terminal. One or more search target data to be searched for matching with the search data consisting of the plurality of first input data is stored. In the search, either one of the search data and the search target data is stored. Data for outputting an access signal for reading the replacement data from the memory area of the memory means in which the replacement data corresponding to the searched data for which the match is detected is stored when a match is detected. Reference means, and at least some or all of the bits of the input data input from the second input terminal depending on the presence or absence of the access signal Is replaced with the replacement data read from the memory means, the second output data consisting of the second input data input from the second input terminal, the first output data Data consisting of third output data generated by a logical operation based on the output data of the second output data, and fourth output data generated by a logical operation based on both the first output data and the second output data 2. A data output means for outputting different data selected from the group as the output data from the output terminal.
The described data flow control device. 3. The latest first input data including the latest first input data when the latest first input data is input from the first input terminal, wherein the data switching means includes the latest first input data. A plurality of first input data traced back in the order of input from the array when the insertion of the first input data that does not form the array between the first input data that forms the array is permitted. The replacement data in which at least some or all of the bits of the second input data input from the second input terminal are defined in correspondence with the array depending on whether or not any one of them is included. Replaced with the first output data, the second output data having the same logic as the second input data input from the second input terminal,
Third output data generated by a logical operation based on the first output data, and fourth output data generated by a logical operation based on both the first output data and the second output data 2. The data flow control apparatus according to claim 1, wherein different data selected from the data group consisting of is output from the output terminal as the output data. 4. The memory means is provided with one or a plurality of memory areas, and in each of the memory areas, the replacement data, the return ring data used for searching the array, and the final array data are used as required. Output control data indicating whether or not there is a stage, and the data switching means is input from the register for storing the feedback data read from the memory means and the first input terminal. One or more search target data to be searched for matching with search data consisting of a pair of first input data and feedback data stored in the register are stored, and the search is performed in the search. When a match between the data and any one of the searched data is detected, the memory means is read from the memory area corresponding to the searched data for which a match is detected. Data reference means for outputting an access signal for reading out the data stored in the memory area; and the output control data in the data read out from the memory means, input from the second input terminal. First output data obtained by replacing at least a part or all of the bits of the second input data with the replacement data in the data read from the memory area, input from the second input terminal Second output data having the same logic as the second input data, third output data generated by a logical operation based on the first output data, and the first output data and the second output data Different data selected from the data group consisting of the fourth output data generated by the logical operation based on both 4. The data flow control device according to claim 3, further comprising a data output means for outputting from the input terminal. 5. The data switching means includes the latest first input data including the latest first input data when the latest first input data is input from the first input terminal. A plurality of first input data traced back in the order of input from the first input data forming the array, permitting insertion of the first input data within a predetermined number that does not form the array between the first input data. Depending on whether or not any one of the arrays is included, at least a part or all of the bits of the second input data input from the second input terminal are defined corresponding to the array. First output data replaced with the replacement data, second output data having the same logic as the second input data input from the second input terminal, and logic based on the first output data Third generated by calculation Output data and different data selected from a data group consisting of fourth output data generated by a logical operation based on both the first output data and the second output data, The data flow control device according to claim 1, wherein the output data is output from the output terminal. 6. The memory means includes one or a plurality of memory areas, and each of the memory areas represents the replacement data, feedback data used for searching the array, and the predetermined number, as required. Distance data, and output control data indicating whether or not it is the final stage of the array, the data switching means, a register for storing the feedback data read from the memory means, After storing the distance data read from the memory means, after the storage, before the next input of the first input data forming the array from the first input terminal, A cow that terminates the search of the array being searched when the first input data that does not form the array exceeds the predetermined number that is determined and is input from the first input terminal. And a search data consisting of a pair of the first input data input from the first input terminal and the feedback data stored in the register, or A plurality of searched data are stored, and when a match between the search data and one of the searched data is detected in the search, the memory area of the memory means corresponding to the searched data for which a match is detected. From the second input terminal according to the data reference means for outputting an access signal for reading the data stored in the memory area, and the output control data in the data read from the memory means. At least a part or all of the bits of the generated second input data are replaced with the replacement data in the data read from the memory area. First output data, second output data having the same logic as the second input data input from the second input terminal, third output generated by a logical operation based on the first output data The different data selected from the data group consisting of the data and the fourth output data generated by the logical operation based on both the first output data and the second output data are the output data. 6. The data flow control device according to claim 5, further comprising data output means for outputting from the output terminal. 7. The data reference means stores the searched data defined by a combination of an enhancement transistor and a depletion transistor, and the data reference means stores the searched data. The data flow control device according to the paragraph. 8. The data according to claim 2, 4 or 6, wherein said memory means stores data defined by a combination of an enhancement transistor and a depletion transistor. Flow control device. 9. The first input means inputs address data input to a storage device that stores a large number of data as the first input data, and the second input means outputs the address data. 2. The data flow control device according to claim 1, wherein data output from a storage device is input as the second input data. 10. The replacement means corresponding to a first array composed of a plurality of the first input data, a plurality of first input data constituting the first array, and a plurality of the plurality of first input data. 2. The replacement data corresponding to a second array consisting of one or a plurality of the first input data arranged after the first input data of the above is stored. The described data flow control device. 11. The memory means stores a plurality of the replacement data corresponding to each of the plurality of arrays including the same first input data in a final stage. The described data flow control device. 12. The first data is address data representing an address on a memory in which an instruction to be executed by a CPU is stored, and the array is executed at a branch instruction or before the branch instruction. The address at which the instruction is stored and the address at which the instruction executed after the branch instruction is stored, and the branch instruction is stored at the address distant from the address at which the branch instruction is stored 2. The data flow control device according to claim 1, comprising a plurality of address data representing a plurality of addresses including a generated address. 13. The first data is address data representing an address on a memory in which an instruction to be executed by a CPU is stored, and the array is executed as a subroutine call instruction or before the subroutine call instruction. 2. A plurality of address data representing a plurality of addresses including an address at which an instruction to be stored is stored and an address at which an instruction to be executed after the subroutine call instruction is stored. Data flow controller. 14. The first data is address data representing an address on a memory in which an instruction executed by a CPU is stored, and the array is a return instruction from a subroutine or before the return instruction. 2. A plurality of address data representing a plurality of addresses including an address at which an instruction to be executed is stored and an address at which an instruction to be executed after the return instruction is stored. Data flow controller. 15. The first data is address data representing an address on a memory where an instruction executed by a CPU is stored, and the array corresponds to a predetermined event when the predetermined event occurs. A plurality of address data representing a plurality of addresses including an address at which a call instruction for instructing the calling of a predetermined routine is stored and an address at which an instruction executed after the call instruction is stored. The data flow control device according to claim 1. 16. The first data is address data representing an address on a memory in which an instruction executed by a CPU and data accessed by the CPU are stored, and the array stores data on the memory. A plurality of addresses representing a plurality of addresses including a data access instruction to be accessed or an instruction to be executed before the data access instruction and an address to store data accessed by the data access instruction The data flow control device according to claim 1, wherein the data flow control device comprises data. 17. A first input terminal to which first input data is sequentially input, a second input terminal to which second input data is sequentially input, an output terminal to which output data is sequentially output, and a plurality of first input terminals. Substitution data defined corresponding to one or more respective arrays of one input data, and defined corresponding to the first input data included in at least one of the arrays. Memory means for storing feedback data, a register for storing the feedback data read from the memory means, the second input data input from the second input terminal, and read from the memory means The replacement data is input, and the second input data, or at least a part or all of the bits of the second input data is replaced with the replacement data according to a predetermined control signal. A selector for outputting to the output terminal as the output signal, the first data included in any one of the arrays, and the array including the first data, Of the first data included in any one of the arrays, the searched data including a pair with the feedback data defined corresponding to the first data arrayed immediately before the data of Stored in each searched data memory area corresponding to each, and stored in the register and the first data input from the first input terminal,
The searched-data memory area in which the searched-data that is paired with the return data read from the memory means is compared with the searched-data, and the searched-data that matches the searched-data is stored. In response to the coincidence detecting means for outputting a coincidence signal to the signal line provided corresponding to, and the coincidence signal being outputted to the signal line,
From the memory means, the feedback data defined corresponding to the first data forming the searched data stored in the searched data memory area corresponding to the signal line to which the match signal is output is stored. The first data which is read and stored in the register and which constitutes the search data
Depending on whether or not the input data of the above is the first input data arranged at the end of any one of the arrays, the replacement data defined corresponding to the array is stored in the memory. Data from which at least a part or all of the bits of the second data read from the means and input from the second input means are replaced with the replacement data, or the selector outputs the data. A data flow control device comprising a control means for causing the selector to output the second data input from the selector. 18. A first input terminal to which first input data is sequentially input, a second input terminal to which second input data is sequentially input, an output terminal to which output data is sequentially output, and a plurality of first input terminals. Substitution data defined corresponding to one or more respective arrays of one input data, and defined corresponding to the first input data included in any one of the arrays. Feedback data, and the first data, which is defined corresponding to the first input data, is input to the first input terminal and then forms the array including the first data. Another first input allowed to be input from the first input terminal until the first data arranged immediately after the first data is input from the first input terminal. Memory means for storing distance data indicating the number of data, A register for storing the return data read from the memory means, the distance data read from the memory means, and the first input input from the first input terminal after the storage By comparing the number of pieces of data with the distance data, another first input data is input from the first input terminal while two predetermined first input data adjacent to each other in the array are input. A counter that terminates the search of the array when the number of input data of 1 exceeds the number determined by the distance data, the second input data input from the second input terminal, and read from the memory means. The output replacement data is input, and the second input data, or at least a part or all of the bits of the second input data, is input in response to a predetermined control signal. A selector that outputs the data replaced with the replacement data to the output terminal as the output signal, the first data included in any one of the arrays, and the array including the first data The searched data, which is made up of a pair with the feedback data defined corresponding to the first data arranged immediately before the first data, in any one of the arrays. The first data input from the first input terminal and the first data input from the first input terminal and stored in the register, corresponding to each of the first data included therein.
Search data composed of a pair of the return data read from the memory means is compared with each of the searched data, and the searched data matching the search data is stored in the searched data memory area. Correspondence detecting means for outputting a match signal to the corresponding signal line, and, in response to the match signal being output to the signal line, the target signal corresponding to the signal line to which the match signal is output The feedback data and the distance data defined corresponding to the first data forming the searched data stored in the search data memory area are read out from the memory means, and are respectively read into the register and the counter. Before storing the first input data constituting the search data and arranging it at the end of any one of the arrays Depending on whether or not it is the first input data, the replacement data defined corresponding to the array is read from the memory means and at least the second data input from the second input means. Control means for causing the selector to output data in which some or all of the bits are replaced with the replacement data or for outputting the second data input from the second input means from the selector And a data flow control device. 19. An input terminal to which input data is sequentially input, an output terminal to which output data is sequentially output, and a first storage unit for storing a plurality of storage data respectively defined corresponding to each of the plurality of input data. Memory means, second memory means for storing one or more replacement data defined corresponding to one or more respective arrays of the plurality of input data, and latest input data from the input terminal. When entered,
Depending on whether or not a plurality of first input data including the latest input data and traced back from the latest input data in the input order corresponds to the latest input data, Corresponding to the latest output data, first output data obtained by replacing at least a part or all of the bits of the correspondingly defined storage data with the replacement data defined corresponding to the array. Second output data having the same logic as the defined storage data, third output data generated by a logical operation based on the first output data, and the first output data and the second output data Fourth generated by logical operation based on both
And a read control means for outputting different data selected from the data group consisting of the output data to the output terminal as the output data. 20. The read control means, when the latest input data is input from the input terminal,
A plurality of first input data including the latest input data and traced back in the order of input from the latest input data allows the insertion of the input data that does not form the array between the input data that forms the array. Depending on whether or not any one of the arrays is included, at least some or all of the bits of the storage data defined corresponding to the latest input data are defined corresponding to the array. First output data replaced by the replaced data, second output data having the same logic as the storage data defined corresponding to the latest input data, and logic based on the first output data Third output data generated by the calculation,
And different data selected from a data group consisting of fourth output data generated by a logical operation based on both the first output data and the second output data, as the output data. 20. The memory device according to claim 19, wherein the memory device outputs to an output terminal. 21. The read control means, when the latest input data is input from the input terminal,
A plurality of first input data including the most recent input data and traced back in the order of input from the latest input data, the input data being within a predetermined number each not forming the array between the input data forming the array. Depending on whether or not any one of the arrays is included, the at least some or all of the bits of the storage data defined corresponding to the latest input data are stored in the array. First output data replaced by the correspondingly defined replacement data, second output data having the same logic as the storage data defined corresponding to the latest input data, and the first output Third generated by logical operation based on data
Output data, and the first output data and the second output data
Different output data selected from a data group consisting of fourth output data generated by a logical operation based on both the output data and the output data are output to the output terminal as the output data. Claim 1
9. The memory device according to item 9. 22. The memory device according to claim 19, wherein the input data is address data. 23. The output data output from the output terminal includes data representing an instruction executed by a CPU, and the different data output from the output terminal have the same instruction code, and 20. The memory device according to claim 19, wherein the data is data representing instructions having different operands. 24. The memory device according to claim 23, wherein the different data are data representing instructions for storing different values in the same register. 25. The memory device according to claim 23, wherein the different data are instructions for storing predetermined values in different memory addresses. 26. The memory device of claim 23, wherein the different data are branch instructions to different addresses. 27. Output data output from the output terminal includes data representing an instruction executed by a CPU, and at least one of the different data output from the output terminal is a return instruction from a subroutine. 20. The memory device according to claim 19, which is data representing 28. The output data output from the output terminal includes data representing a predetermined instruction executed by the CPU, and the different data output from the output terminal are data representing different instructions. The memory device according to claim 19, wherein the memory device is a memory device. 29. The output data output from the output terminal includes data referred to by a predetermined instruction executed by a CPU, and the different data output from the output terminal is referred to by the predetermined instruction. 20. The memory device according to claim 19, wherein the data is different data having different values.