JPH0731916B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a nonvolatile semiconductor memory device using BiCMOS, and more particularly to a data read circuit thereof.

(Prior Art) Conventionally, a data read circuit (sense amplifier) in a nonvolatile semiconductor memory device is configured, for example, as shown in FIG. The EPROM is shown here as an example, and the difference between the conductance of the memory cell MC on the main body side and the conductance of the dummy cell DC is used, and the difference is amplified by the differential amplifier 11 composed of MOS transistors Q1 to Q4. Thus, the storage data D is read from the memory cell MC. Note that Q5 and Q6 are MOS transistors that act as loads.

In the above configuration, the conductance of this transistor is low (the threshold voltage V _TH is high) in the state where the electric charge is accumulated in the memory cell MC (the program mode), and the state where the electric charge is not accumulated (the erase mode). ), The conductance is high (threshold voltage V _TH is low). Since the dummy cell DC has the same shape as the memory cell MC, the conductance is the memory cell MC.
It is the same as the erase mode of. Therefore, the memory cell MC
In order to detect the erase mode of the memory cell MC, the resistance value of the load MOS transistor Q5 of the memory cell MC is changed to the load MOS of the dummy cell DC.
The resistance value of the transistor Q6 is set to be larger than that of the transistor Q6, and the potential of the node N1 is lower than that of the node N2 under the same conductance. Of course, the potential of the node N1 when the conductance of the memory cell MC becomes low is
It is set to be lower than the potential of the node N2. In this state, the control gates of memory cell MC and dummy cell DC are set to the level of power supply Vcc.

FIG. 7 shows changes in the potentials of the nodes N1 and N2 with respect to changes in the power supply Vcc voltage of the data read circuit described above. The potential of the node N2 (reference potential) is the MOS transistor Q
Since the resistance value of 6 is lower than that of the MOS transistor Q5, the solid line 12
As shown in, the voltage drop is small even if the power supply Vcc voltage rises, and the degree of following the fluctuation of the power supply Vcc voltage is stronger than that of the node N1. The memory cell MC has a different value depending on the difference (ΔV _TH ) in the threshold voltage of the cell characteristics, but as shown by the solid lines 13a to 13d, has a smaller tendency to change in the power supply Vcc voltage than the reference potential. In addition, ΔV _TH = 0.0 (solid line 13a) is in the erased state.

By the way, the ΔV _{TH of the} memory cell MC is easily influenced by the shape variation and the like due to the process variation, and even on the same chip, it varies depending on the sem. For example, in Fig. 7, ΔV _TH = 2.0 is ± 0.5V as shown by hatching.
If there are variations, the maximum operating voltage of this memory (Vccm
ax) drops from the point of V1 to the point of V2. As a countermeasure in this case, lower the resistance value of the MOS transistor Q6 and
It is conceivable to reduce the gradient of the above, but if this is done, the point where the power supply Vcc voltage is low, that is, the region 14 surrounded by the alternate long and short dash line becomes indistinguishable from the erased state. Moreover, there is a drawback that the minimum operating voltage (Vccmin) rises because the characteristics of the memory cell MC in the erased state and the characteristics of the dummy cell DC itself are easily affected.

(Problems to be Solved by the Invention) As described above, the conventional data read circuit in the semiconductor memory device has a drawback that the margin for the fluctuation of the power supply voltage is small.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device including a data read circuit capable of providing a large margin for fluctuations in power supply voltage.

[Structure of the Invention] (Means and Actions for Solving Problems) That is, in the present invention, in order to achieve the above object, it is generated according to the difference between the conductance of the memory cell and the conductance of the dummy cell. In a non-volatile semiconductor memory device that amplifies a potential difference and reads stored data, the potential difference between a first potential supply source and a second potential supply source is divided and A first gate potential generating circuit for generating a first potential independent of the potential of the second potential supply source and applying the first potential to the gate of the memory cell, the first potential supply source and the second potential A potential difference from the supply source is divided to generate a second potential that depends on the potential of the first potential supply source, does not depend on the potential of the second potential supply source, and is different from the first potential. The gate of the above dummy cell Characterized by comprising a second gate voltage generation circuit for applying.

With such a configuration, the first and second gate potential generation circuits are based on the potential of the first potential supply source (ground point) even if the potential of the second potential supply source (power supply) changes. Since a constant potential is output, a large margin can be secured for fluctuations in the power supply voltage.

Further, in a nonvolatile semiconductor memory device that amplifies the potential difference generated according to the difference between the conductance of the memory cell and the conductance of the dummy cell by a differential amplifier to read the stored data, the first potential supply source and the first potential supply source The potential difference between the second potential supply source and the second potential supply source is divided to generate a first potential that depends on the potential of the first potential supply source and does not depend on the potential of the second potential supply source and is applied to the gate of the memory cell. And a second gate potential generating circuit that divides the potential difference between the first potential supply source and the second potential supply source, and that depends on the potential of the first potential supply source. A second gate potential generating circuit that generates a second potential that does not depend on the potential of the supply source and is different from the first potential and applies the second potential to the gate of the dummy cell; and the first and second potential supply sources The potential difference between them reaches the maximum operating voltage At the same time, the outputs of the first and second gate potential generation circuits are set to the potential of the second potential supply source, respectively, and at least one of the load connected to the memory cell and the load connected to the dummy cell. And a monitor means for generating a potential difference between the input terminals of the differential amplifier.

In the above configuration, since the monitor means is provided,
The fluctuation of the threshold voltage of the memory cell can be monitored by setting the second potential supply source to the maximum operating voltage and detecting the potential at which the output of the differential amplifier is inverted.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 6 are designated by the same reference numerals, and one input terminal of the differential amplifier 11 is connected to one end of an intrinsic type MOS transistor Q5. The power supply Vcc is applied to the other end of the MOS transistor Q5.
Is connected and the gate is connected to the ground point Vss to act as a load. The memory cell MC is connected between one end of the MOS transistor Q5 and the ground point Vss, and the output terminal of the first gate potential generating circuit 15 is connected to the control gate of the memory cell MC. On the other hand, the differential amplifier 11
One end of an intrinsic type MOS transistor Q6 is connected to the other input terminal of the. The power supply Vcc is connected to the other end of the MOS transistor Q6, and the gate thereof is connected to the ground point Vss so that it works as a load. A dummy cell DC is connected between one end of the MOS transistor Q6 and the ground point Vss, and the output terminal of the second gate potential generating circuit 16 is connected to the control gate of the dummy cell DC. The first gate potential generation circuit 15 is composed of a resistor R1 and NPN type bipolar transistors Q7 to Q10 connected in series between the power source Vcc and the ground point Vss.
7 to Q10 have a diode configuration in which the base and collector are connected. Then, the resistor R1 and the transistor Q7
The gate bias potential for the memory cell MC is obtained from the connection point with. Similarly, the second gate potential generation circuit 16 is composed of a resistor R2 and an NPN type bipolar transistor Q11 to Q13 connected in series between the power source Vcc and the ground point Vss. These transistors Q11 to Q13 are base and collector. The two are connected to form a diode. Then, the gate bias potential for the dummy cell DC is obtained from the connection point between the resistor R2 and the transistor Q12.

As shown, the control gate of the memory cell MC is
The dummy cells DC are biased based on the forward voltages of the four-stage bipolar transistors Q7 to Q11, and the dummy cell DC is biased based on the forward voltages of the three-stage bipolar transistors Q11 to Q13. In the above configuration, set the resistance values of the MOS transistors Q5 and Q6 that act as loads to the same,
The input nodes N1 and N of the differential amplifier 11 depend on the potential difference applied to the control gates of the memory cell MC and the dummy cell DC.
Generate a potential difference at 2.

First, when the memory cell MC is in the erased state, that is, when the dummy cells DC of the memory cell MC have the same characteristics, more current flows to the memory cell MC side due to the potential difference of the control gate, and the potential of the node N1 is higher than that of the node N2. Will also be lower. On the other hand, by programming the data in the memory cell MC, when the threshold voltage V _TH of this cell MC becomes equal to or higher than the sum of the forward voltage Vf of the bipolar transistors Q7 to Q10, more current flows through the dummy cell DC side and the node The potential of N2 drops and a potential difference occurs between the memory cell MC and the dummy cell DC. This is sensed and amplified by the differential amplifier 11 to read the stored data D from the memory cell MC.

The power supply voltage dependence of the circuit shown in FIG. 1 is exactly the same on the memory cell MC side and the dummy cell DC side because the circuit portion formed by the MOS transistors is symmetrical. On the other hand, in the circuit portion using the bipolar transistor, the forward voltage Vf of the bipolar transistor is determined by the logarithm of the current, so that it is constant even if the power supply voltage changes, and the potential difference between the control gates of the memory cell MC and the dummy cell DC is It is held as long as the bipolar transistors Q7 to Q13 are on. As a result, the dependence of the potentials of the nodes N1 and N2 on the power supply Vcc voltage becomes as shown in FIG. 2, and a circuit resistant to cell variation can be obtained. In FIG. 2, 17 is a reference potential (potential of the node N2), 18a is a potential of the node N1 when the memory cell MC is on, and 18b is a power source of the potential of the node N1 when the memory cell MC is off. Vcc
It is voltage-dependent.

FIG. 3 shows another embodiment of the present invention. This circuit is an improvement of the circuit shown in FIG. 1 so that the cell characteristics can be monitored (measurement of variation in ΔV _TH ) by the maximum operating voltage Vccmax, which was possible in the circuit shown in FIG. That is, in the circuit of FIG. 6, since the nodes N1 and N2 have different dependences on the power supply Vcc voltage, the intersection of the solid line 12 and the solid lines 13a to 13d (the point at which the output of the differential amplifier 11 is inverted), for example, The variation of ΔV _TH could be measured by searching V1 and V2. However, in the circuit shown in FIG. 1, since the solid line 17 (potential of the node N2) and the solid lines 18a and 18b (potential of the node N1) do not intersect, the variation of ΔV _TH cannot be measured by the above method. Therefore, the following configuration is used to measure the variation of ΔV _TH . That is, an intrinsic type MOS transistor Q14 is provided in parallel with the transistor Q6 in the circuit of FIG. 1, and the gate of the MOS transistor Q14 has the bipolar transistor Q10 and the ground point V.
The base of NPN bipolar transistor Q15 connected between ss and the bipolar transistor Q13 and ground point V
The base of the NPN bipolar transistor Q16 connected to ss is connected. At this connection point, the power supply Vcc and the ground point Vss
A connection point between the resistor R3 and the NPN bipolar transistor Q17 connected in series is connected between them. The power supply Vcc and the ground point Vs are connected to the base of the bipolar transistor Q17.
A connection point between a Zener diode ZD and a resistor R4 connected in series between s is connected.

In the above-mentioned configuration, in the normal operation in which the power supply Vcc voltage is 8 V or less and the Zener diode ZD is off, the transistor Q17 is turned off, the transistors Q15 and Q16 are turned on, and the load MOS transistor Q14 is turned off. First
The operation is exactly the same as the circuit shown. On the other hand, the power supply Vcc voltage is 8
When V exceeds V and Zener diode ZD turns on (breakdown), transistor Q17 turns on and transistor Q17 turns on.
15, Q16 turns off, and transistor Q14 turns on. As a result, the gates of the memory cell MC and the dummy cell DC are biased to the power supply Vcc voltage. At this time, a potential difference is generated at the nodes N1 and N2 due to the difference in load. Node N
The power supply voltage dependency of 2 changes at the discontinuous point X3 as shown by the solid line 17 'in FIG. 4 and intersects with ΔV _TH = 2.0, ΔV _TH = 2.5, and ΔV _TH = 3.0, respectively. The potential at a point exceeding the potential V3 at the discontinuous point X3, for example, V4, V5, becomes the maximum operating voltage (Vccmax) at each threshold voltage (ΔV _TH = 2.0, ΔV _TH = 3.0), and the memory is based on this potential. It is also possible to detect the cell write amount.

In this way, when the discontinuity characteristic is given, the discontinuity point X3
Oscillation in the vicinity may be a problem.

However, in the circuit of FIG. 4 described above, this is alleviated because of the hysteresis characteristic of the transistor. That is, since bipolar transistors are used for the transistors Q15, Q16, and Q17, the turn-off time of the transistors due to the base accumulation effect is much longer than the turn-on time. Therefore, it does not oscillate at high frequencies below this time. Of course, the discontinuity point (inflection point) X3 is outside the normal operating range, and it is impossible to pass through this point other than the monitor of ΔV _TH .

Although the Zener diode ZD is used for monitoring the high voltage in the circuit shown in FIG. 4, other configurations such as series connection of diodes may be used.

FIG. 5 shows another embodiment of the present invention, in which the first gate potential generating circuit 15 in FIG. 1 is composed of NPN type bipolar transistors Q18 and Q19 and resistors R5 to R7, and The second gate potential generating circuit 16 is composed of NPN type bipolar transistors Q20 and Q21 and resistors R8 to R10. That is, the collector of the transistor Q18 and one end of the resistor R5 are connected to the power supply Vcc. The base of the transistor Q18 is connected to the other end of the resistor R5 and the collector of the transistor Q19, and the emitter is connected to the control gate of the memory cell MC and one end of the resistor R6. The other end of the resistor R6 is connected to the base of the transistor Q19 and one end of the resistor R7. The ground point Vss is connected to the emitter of the transistor Q19 and the other end of the resistor R7 to form a first gate potential generation circuit 15. Similarly, the power supply Vcc is connected to the collector of the transistor Q20 and one end of the resistor R8.
The other end of the resistor R8 and the collector of the transistor Q21 are connected to the base of Q20, and the control gate of the dummy cell DC and one end of the resistor R9 are connected to the emitter. The other end of the resistor R9 is connected to the base of the transistor Q12 and one end of the resistor R10. The ground point Vss is connected to the emitter of the transistor Q21 and the other end of the resistor R10 to form the second gate potential generation circuit 16.

In the above configuration, resistors R6 and R7 and R9 and R10
The output of the first gate potential generation circuit 15 and the second gate potential generation circuit 16 are changed by changing the ratio of the resistance values of
To produce a potential difference with the output of.

Even in such a configuration, basically, the same operation as that of the circuit of FIG. 1 is performed and the same effect is obtained.

[Effects of the Invention] As described above, according to the present invention, a semiconductor memory device including a data read circuit capable of providing a large margin for fluctuations in power supply voltage can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing power supply voltage dependence of the circuit of FIG. 1, and FIG. 5 is a circuit diagram for explaining another embodiment of the present invention, FIG. 4 is a characteristic diagram showing the power supply voltage dependence of the circuit of FIG. 3, and FIG.
FIG. 6 is a circuit diagram for explaining another embodiment of the present invention, FIG. 6 is a circuit diagram for explaining a conventional semiconductor memory device, and FIG. 7 is a power supply voltage dependence of the circuit of FIG. It is a characteristic view to show. 11 ... Differential amplifier, 15 ... First gate potential generation circuit,
16 ... Second gate potential generation circuit, MC ... Memory cell,
DC: dummy cell, Vcc: power supply, Vss: ground point, R1, R
2 ... Resistor (load element), Q7-Q13, Q18-Q21 ... Bipolar transistor, R5-R10 ... Resistor.

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory device for amplifying a potential difference generated according to a difference between a conductance of a memory cell and a conductance of a dummy cell to read stored data, wherein a first potential supply source and a second potential supply source are provided. The potential difference from the potential supply source is generated, and a first potential that depends on the potential of the first potential supply source and does not depend on the potential of the second potential supply source is generated and applied to the gate of the memory cell. A first gate potential generating circuit, a potential difference between the first potential supply source and the second potential supply source is divided, and the second potential supply is dependent on the potential of the first potential supply source. 2. A semiconductor memory device comprising: a second gate potential generation circuit that generates a second potential that does not depend on the source potential and is different from the first potential and applies the second potential to the gate of the dummy cell. 2. A load element having one end connected to the second potential supply source, each of the first and second gate potential generation circuits, the other end of the load element, and the first potential supply source. A diode-connected bipolar transistor having a base and a collector connected in series between the load element and the bipolar transistor, and an output is obtained from a connection point between the load element and the bipolar transistor. 2. The semiconductor memory device according to claim 1, wherein the number of stages of the bipolar transistors connected in series is changed with the second gate potential generating circuit. 3. The first and second gate potential generation circuits respectively include a first bipolar transistor whose collector is connected to the second potential supply source, and a collector and a base of the first bipolar transistor. A first resistor connected, a second and a third resistor connected in series between the emitter of the first bipolar transistor and the first potential supply source, and a collector connected to the base of the first bipolar transistor. A second bipolar transistor having an emitter connected to the first potential supply source and a base connected to the connection point of the second and third resistors, and the emitter side of the first bipolar transistor. Is obtained by changing the ratio of the second and third resistors between the first gate potential generating circuit and the second gate potential generating circuit. Huh claim semiconductor memory device of the range preceding claim in. 4. A first potential supply in a non-volatile semiconductor memory device for amplifying a potential difference generated according to a difference between a conductance of a memory cell and a conductance of a dummy cell by a differential amplifier to read stored data. Source and second
The potential difference from the potential supply source is generated, and a first potential that depends on the potential of the first potential supply source and does not depend on the potential of the second potential supply source is generated and applied to the gate of the memory cell. A first gate potential generating circuit, a potential difference between the first potential supply source and the second potential supply source is divided, and the second potential supply is dependent on the potential of the first potential supply source. Between a second gate potential generating circuit that generates a second potential that does not depend on the potential of the source and is different from the first potential and applies the second potential to the gate of the dummy cell; and the first and second potential supply sources When the potential difference between the first and second gate potential generating circuits reaches the maximum operating voltage, the outputs of the first and second gate potential generating circuits are respectively set to the potential of the second potential supply source, and the load connected to the memory cell and the load By changing at least one of the loads connected to the dummy cells, the differential A semiconductor memory device comprising: monitor means for generating a potential difference between input terminals of an amplifier. 5. The potential detecting means for detecting that the potential difference between the first and second potential supply sources has reached the maximum operating voltage, and the potential detecting means for detecting the maximum operating voltage. Sometimes, the first switch means for setting the output of the first gate potential generating circuit to the potential of the second potential supply source, and the second gate when the operating maximum voltage is detected by the potential detecting means. Second switch means for setting the output of the potential generating circuit to the potential of the second potential supply source, and the dummy cell side input end of the differential amplifier when the operation maximum voltage is detected by the potential detecting means. 5. A semiconductor memory device according to claim 4, further comprising means for reducing a load.