JPH0731623B2 - Lockout prevention circuit - Google Patents

Description

DETAILED DESCRIPTION (Related Application) This application is the assignee of this application, Honeywell Information Sy.
RJ Koe filed on the same day transferred to stems
US patents such as gel It relates to a control system access device having a multi-command level conditional rotating port service priority hierarchy.

[Industrial application field]

The present invention relates to a circuit for preventing a predetermined command format for a system controller of a data processing system from being locked out, and more particularly to a system controller having a priority hierarchy of conditional command service of multiple command levels. Signal generator for preventing lockout of high priority requests to the.

[Conventional technology and problems to be solved]

The system controller of the system includes port priority based port groups so that blocked ports can be bypassed. Blocked ports are especially designed for two central processing units (CPUs) to make requests to each of the two corresponding system control units (SCUs).
One input / output (I / O) device can occur in a tandem configuration of the data processing system, each connected to both SCUs. The present invention is incorporated into a system controller having multiple command types with predetermined priority levels. The port service operation of the system controller embodying the present invention is based on two levels, high and low level commands, with high level commands having priority over low level commands. Each level is independent of the others. The priority within a level is based on the assumption that the higher priority port within this level does not have any pending service requests blocked due to some required part of the system being unavailable. Rotated on. If it is determined that lower high priority requests have been serviced a predetermined number of times more than pending higher high priority requests, the circuit of the present invention allows the system controller to control A control signal is generated to prevent further requests from the CPU and its associated I / O devices) from being processed by the SCU. The user of an individual port can change its command level within the established system requirements if this is not selected in some predetermined selection interval.

[Means for solving problems]

Therefore, in accordance with the present invention, a system having a multi-command level conditional rotary multi-port service priority hierarchy
Circuitry is provided to prevent lockout of high priority requests to the controller.

The data processing system includes a system controller for controlling access to at least one subsystem in response to access requests from a plurality of devices operatively connected to corresponding ports of the system controller. . The access request is of a plurality of command levels, where the command levels have predetermined predetermined interrelated priority levels, and each port has a pre-determined relative port priority within each command level. There is one. The priority of this port is conditionally rotated within the command level corresponding to the access request from the device to which access is permitted. The system controller includes circuitry that prevents lockout of pending higher priority requests. The circuit includes a counter element for counting the number of times a pending higher priority request was not granted access. The result of this count is
Provides the count value temporarily stored in the counter element. A comparison element operatively associated with the counter element compares the count value with a predetermined value, the predetermined value bypassing a higher priority request pending by the data processing system. It is a predetermined number that is the predetermined number of times that it is allowed. A control signal is output from the comparison element when the count value is equal to the predetermined value. This control signal is connected to each port to prevent further access requests from the devices from being accepted by the system controller.

The circuit is also operatively connected to the comparison element to latch a control signal when it is determined that a subsequent higher priority request allowed to access is not the highest higher priority request. This control signal is maintained until all pending high priority requests, including elements, are granted access. When a higher priority request is granted access and a higher priority request is not pending,
A reset element operatively connected to the counter element resets the count value.

Accordingly, it is an object of the present invention to provide a circuit that prevents lockout of pending higher priority requests.

Another object of the present invention is to provide a circuit for preventing lockout of pending higher priority requests to a system controller having multiple command level conditional rotation priority hierarchies.

Yet another object of the present invention is to provide a circuit which prevents the lockout of pending higher priority requests to a system controller having multiple command levels, each having a predetermined priority.

Another object of the invention is to prevent lockout of pending higher priority requests to system controllers having multiple levels, each having a predetermined priority, each level being independent of the others. To provide a circuit for doing so.

Yet another object of the present invention is to have a service request pending, with each port having a predetermined priority and having multiple levels independent of the other, one higher priority port within the level. Provide a circuit to prevent lockout of pending higher priority requests to the system controller where the priority within each level of each port is rotated at the same time as the service of one port It is in.

The above and other objects of the present invention will be further clarified by referring to the drawings below. In the drawing,
The same symbols indicate similar parts.

〔Example〕

Referring to FIG. 1, a data processing system (DPS) 10 including a system controller (SCU) 50 incorporating the circuit of the present invention.
It is shown. The DPS 10 includes a memory 20, a central processing unit (CPU) 30, and an input / output I / O device 40 that interfaces with various peripheral devices (PER). CPU
30 and I / O device 40 interface with memory 20 via a system controller (SCU) 50. CPU30 and I
The / O device 40 makes a request to the memory 20 to perform a predetermined task of the DPS 10. The SCU 50 (sometimes referred to as the memory controller) determines which of the CPU 30 or the I / O device 40 will gain access to the memory 20 when making requests at the same or near the same time. Access to memory 20 (or internal SC
In order to resolve contention in the (access to U) request, the SCU50 logic includes a priority scheme where higher priority requests are allowed first. Generally, CPU3
0 can wait for a short period of time before access to memory 20 is granted. In some cases, when I / O device 40 is interfacing with a device such as a disk file, I / O device 40 may generate I / O between I / O device 40 and the disk file (ie, Due to the nature of (data transfer) one cannot wait. In some cases, I / O device 40 interfaces with peripheral devices that do not require quick access to memory 20, in which case the I / O device can wait. As a result, various types of commands, such as high and low priority commands, are included in DPS10, and the commands are stored in memory 20.
In order to help ensure that an appropriate decision is made by the SCU50 when allowing access to a device (ie DP
Issued by the CPU 30 or I / O device 40) of the preferred embodiment of S10. The command format used in the preferred embodiment is shown in Table 1. SCU 50 includes a plurality of ports, and in the preferred embodiment, SCU 50 includes ports 0-7 having an initial priority based on the number of ports within a command level. I / O device 40 or CPU3
0, or as a result of servicing a request from another device that can connect to the corresponding port, priorities within a command level can be rotated to avoid blocking lower priority ports. it can. In addition, priority rotation is contingent on the fact that there are no higher priority requests pending in the command level that have not been answered. This further ensures that higher priority requests are not vaguely overlooked. Although the preferred embodiment includes only two command levels, it will be appreciated by those skilled in the art that many command levels can be increased. Further, while only ports 0 and 1 are used in the discussion of the preferred embodiment of SCU 50, it will be appreciated that other devices can be interfaced to the available ports, or the number of ports can be modified.

Memory 20 of the preferred embodiment of data processing system 10.
Includes 16 memory devices, namely, memory device 0 200 to memory device 15 215, each memory device 0-15 being 1
One bus 220 is connected to the bus 220. The bus 220 has one input bus and one output bus (not shown), and the SCU 50 is also connected to the bus 220.

Between the SCU 50 and the CPU 30, and between the SCU 50 and the I / O device 40, there are I / O protocols for exchanging data via lines 31 and 41 that are mutually connected. CPU30 or
When either one of the I / O devices 40 requests access to the memory 20, a request signal is placed on each tie line 31 ', 41', which lines are shown on the tie lines 31, 41 shown. It is a part. The connecting lines 31, 41 and the bus 220 are data lines,
It should be understood to include address lines and command and control lines. In addition, the signal indicating the command and the signal indicating the memory location are transmitted to the requesting side (that is, CPU 30 or I / O device
40) placed on each connecting line 31 ", 41". SCU5
The logic of 0 determines whether to accept the request signal from the CPU 30 or the I / O device 40. If a predetermined condition is met (eg, memory is available, etc.), the request is accepted according to the priority hierarchy of the SCU50 logic, and the accept signal is sent from the SCU50 to the port, and from this port to the CPU30 or I / O device 40 sent to port
Data transfer between CPUs 30 or between I / O devices 40 occurs according to an established protocol. Here, the problem is the logic of the SCU 50 for accepting a request from the CPU 30 or the I / O device 40 according to the conditional rotation multi-port service priority hierarchy of the multiple command level of the present invention,
This will be discussed in detail below. A discussion of the circuit of the invention used in SCU 50 will be given below. The transfer of data once the SCU 50 has accepted the CPU 30 or I / O device 40 for data transfer is in accordance with the established protocol and is not relevant to the discussion of the SCU 50 or the circuit of the invention,
No further discussion will be given in the text.

Before discussing the circuit of the present invention, the SC described below
U50 must be clearly understood. In FIG. 2, a functional block diagram of the SCU 50 is shown. The SCU 50 of the preferred embodiment comprises eight ports, namely ports 0 through 7, 51-0 through 51-7, each port being connected to a respective device. In the preferred embodiment of SCU 50, port 0 51-0 is connected to I / O device 40 via link 41.
(Not shown), port 151-1 is connected line 31
Is connected to the CPU 30 (not shown) via. In the preferred embodiment of the SCU 50, the remaining ports, Port 2 through Port 7 (51-2 through 51-7), are not connected to any device. The ports 51-0 to 51-7 are connected to the port requesting devices 52-0 to 52-7. Port 0 request control device which is an output of each port request control device 52-
0, ... Request controller 52-7 at port 7 connects the corresponding specific request signal to the active priority, specifically device 56. Based on the timing of the request, such as the memory device selected, the type of request made and the availability of the hardware required to grant the request, the active priority selection controller 56 accepts the request and accepts the request. Signal P0−
ACPT-REQ, ..., P7-ACPT-REQ are connected to the corresponding ports, port 0 51-0, ..., Port 7 51-7. In addition, various control signals from the active priority select controller 56 for interfacing with the bus 220 to the active register 58, and the memory register of the active register logic device 58 for interfacing with the bus 220 ( (Not shown). In the preferred embodiment of the SCU 50, 5 are put into processing simultaneously.
There is logic to provide up to 3 activity states,
The active state is the acceptance of port requests. The active state priority selection controller 56 connects the control signal HOLD-REQ,
When it determines that a relatively lower high priority request has been serviced a predetermined number of times greater than the pending higher higher priority request, it connects so that no more requests are connected through port 51. The signal HOLD-REQ is connected to each of the ports, namely ports 0-51-0 to ports 7 51-7.
A discussion of preferred embodiments of the circuit of the present invention is made below. A memory device busy controller 54 is included for processing and maintaining information regarding the busy / non-busy status of memory devices 0 200 through memory device 15 215.
Corresponding status signals are connected from the memory device busy controller 54 to the corresponding port request control logic 52-0 through 52-7.

When simultaneous (or nearly simultaneous) requests are made by a device connected to the SCU50, this causes the SCU50 / memory 20
The acceptance of ports that allow communication with is based on a hierarchy of priorities in which the priority within a command level changes (ie, rotates) when a request within that command level is serviced. However, the priority change is conditional on there being no higher priority port requests pending within this command level. The servicing port is based on the command level from the equipment attached to the SCU50,
The preferred embodiment of 0 includes two levels, high and low commands. The receiving operation of the preferred embodiment of the present invention is described next with respect to FIGS. 2, 3 and 4. FIG. 3 shows a timing diagram of requests having the same command level for the same memory device,
One request is made after one clock time (T time). FIG. 4 has the same command level from the device. FIG. 6 shows a timing diagram of requests made simultaneously, ie at the same clock time. It should be noted here that the interface timings of the SCU 50, the memory 20 and the SCU device are in sync.

FIG. 3 shows a clock signal also called the timing [definition] CLK-DEF. Clock cycle is T-TI
Called ME. A second clock signal (or timing, non-definition) is shown, which produces one clock pulse every half cycle of T-TIME. In the case of FIG. 3, the request from the CPU 30 for the memory 0 is T ₀ −T.
Occurs at the start of IME. This request is sent through the connection line 31. Request existence signal output from the port 1 51-1 (P1-REQ-PRES ) is outputted at the start of T _1, is connected to the corresponding port 1 request control unit 52-1. Further, at the start of T ₁ , a request for the memory 0 is made from the I / O device 40, and this request is made through the connection line 41.
After one cycle T-TIME, that is, at the start of T ₂ , port 0 51-0
Outputs the request presence signal (PO-REQ-PRES), and port 0
It is connected to the request control device 52-0. But during T ₁
Port 1 request control logic 52-1 and activity priority selection control logic 56 cause an acceptance request signal (P1-ACPT-REQ) for port 1 to reconnect with port 151-1. As a result, at the start of T ₂ , memory device 0
When 200 is selected and the requested memory is not available when port 0 request control logic 52-0 processes the request present signal from port 0, a specific request signal (PO- PREQ-GO, PO-LP
REQ-PRES, PO-HPREQ-PRES, and PO-HPRI-REQ) can be displayed to indicate the in-use condition to be held (ie, low or inactive).

In FIG. 4 the control signals resulting from simultaneous requests are shown (the timing in FIG. 4 shows a two word write for a memory operation, the request being for a command within the same command level). Good). I / during T ₀
Requests from the O device 40 and the CPU device 30 are made via the connection lines 41 and 31 at the start of the T ₀ period, respectively. Connection line
The information contained in 41, 31 includes address, zone, data and command / control information. In port 0 51-0 and port 1 51-1, each memory selection bit (0-3) is connected to the memory device busy control device 54, and a command bit (0-3).
5) each port 51 to its corresponding port request controller
Performs some processing on commands and address information during T ₀ to connect with 52. Logic device where address bits (0-27), command bits (0-5) and zone bits (0-3) from each port 51 are activity registers.
Connected with 58. In the preferred embodiment of the SCU 50, a 36-bit CPU word is used (plus 4 additional parity bits), each word having four 9-bit bytes. Zone bits identify a byte within a word and address bits define the location of a memory location and memory device. In response to the request for the corresponding device, port 0 requests the port 0 request present signal (P0-RE
Q-PRES) generates, port 1 51-1 produces the port 1 request present signal (P1-REQ-PRES) at the beginning of the period T _1.
As a result, the port 0 request control device 52-0 and the port 1
The request control device 52-1 receives the corresponding specific request signal (PX-
PREQ-GO, PX-LPREQ-PRES and PX-HPRI-REQ, where X = 0 for port 0 and X for port 1
= 1) to the corresponding activity priority selection controller 56. At this time, the priority selection logic of the activity priority selection controller 56 becomes active, resulting in port 0
Or a decision is made to accept one of the requests from either port 1 and the accepted request is the one from the port with the highest priority. This decision is made during T ₁ . If the command levels are equal, the highest priority port within the command level is serviced first. If the command levels are not equal, the port with the highest command level will be serviced first. As a result of the operation of the priority selection logic of the activity priority selection controller 56, a request acceptance signal is generated for port 0 (P0
-ACPT-REQ), this signal is again connected to port 0 51-0 before the start of T ₂ T-TIME (for the purposes of this example, port 0 then has a relatively high priority). Shall have). If the memory device selected by port 1 is different than the memory device selected by port 0, the bus 220 is available for a reasonable period of time, and other conditions are met (ie, execution of the command). logic proper time required for, i.e. if available) when the command is actually executed, the port 1 request T ₂ T-TIM
Will be accepted between the E (which signal P1-ACPT-REQ. The signal shown by a dotted line in Figure 4 is, T ₃ T-TIME
Will be connected to port 151-1 again before the start of). The memory of the start of the activity start signal (START-ACT)
Begin the cycle and display the condition in use by the memory device selected by the port 0 request. The rest of the signals shown in FIG. 4 basically show some with memory interface timing. During the T _2, the command for the address bits ADR (2-27) and zone bit (0-3) and memory are connected to the memory 20. In addition, the data from the port, in this example port 0 (PC-DTA), is connected to the activity register 58 so that the first 40-bit word can only be used for the first half of the period T _2. The word is available to the active register 58 for the first half of the period T ₂ . It includes a 40-bit data word of the preferred embodiment of the DPS 10, plus 4 parity bits. Therefore, the data written to memory is placed on bus 220 for the duration of T ₄ . During time period T ₆ , the memory status word is read from memory 20 to SCU 50. This cycle constitutes the shortest write cycle time of the system of the preferred embodiment.

The various signals received by the port 51 over the link lines 31, 41 are recorded in the port logic (not shown) during the period T ₀ . As a result, various signals necessary for processing the request (PX-REQ-PRES, where X represents ports 0 to 7), that is, the command signal (PX-CMD [0 to 5]), the memory selection signal (PX -MEM-SEL [0-3]) and address and zone signals (P ₀ -ADR [0-27] and PX-ZONE
[0-3]) are available from the rest of the SCU50 logic.

Before proceeding with a detailed discussion of the operation of the SCU 50, it is necessary to provide access to the memory 20 in response to a request from the device.
An overview of the operation of the SCU50 is summarized here as an example. Assume that the data processing system has an SCU 50 having 8 ports numbered 0-7. Suppose during a predetermined period of time the port priority and command level are as shown in Table 2, the command level is fixed and the port priority can (conditionally) rotate. Furthermore, let us assume that during this predetermined time period there is a demand command at port 6 with a command level D and a demand command at port 2 with a command level B. Since these requests are simultaneous (ie, during the same predetermined period of time), the priority logic must determine which requests should be allowed (ie, serviced). Port 2
Since the request from B is a B level command, and B level is a higher priority command than D level, the request on port 2 will be given access prior to the request on port 6 (ie. , The request at port 6 is bypassed). The command level is considered to be the first in the hierarchy of priorities using the B command level port priorities. Thus, if there are no higher priority port requests pending in the B command level port priority, then the port priority is port 2, the port just serviced requests the lowest priority. Will be rotated so as to result in a B command level port priority of 3 (highest priority), 4, 5, 6, 7, 0, 1, 2. In this way, rotation occurs within one command level. In the above sequence (prior to rotation), if a port request with a command level of B has ports 5, 6,
If it does not have a "GO" condition because it is pending for any of 7, 0, 1 but these ports do not have available hardware to answer the request, rotation within the B command level will be prohibited. Although not shown in Table 2, there are port priorities for the A command level, the C command level and the D command level.

A functional block diagram of the port request controller 52 is shown in FIG. The request present signal and the command signal are sent to the memory device usage control device 54 and the activity status register
Received from the corresponding port, along with various control signals from 58. (Note that the port request controller 52 signal representations shown in FIG. 5 have reference numbers that are specifically related to port 0 request controller 52-0. Is repeated for each of the port request control devices 52 each having X, and X represents each port.) A lock inhibit signal, P0-INH-LK, is a control signal generated in response to a read lock command, and this lock command is Command the SCU to lock all memory devices against read lock and write grant lock commands from other ports. The memory device is unlocked by the next serviced instruction from the original lock port. The activity register 58 includes a number of shift registers, each location of which corresponds to a time slot which becomes active as a result of the activity at which the memory input bus or the memory output bus of bus 220 is accepted. There is. The data in the shift register of the activity register 58 forms the control signals (ACT-DIN-SR-B [0-7]) that indicate the expected busy conditions of the input bus for some future period, and the memory Connected to the data-in-bus comparison device 151. Similarly, if data is read from some memory as a result of the activity, the second shift register of activity register 58 indicates the time slot in which the data output bus of bus 220 is busy, and The predetermined bits (bits 8 to 10) of the second shift register are control signals ACT-DOU.
T-SR-B (8-10) is formed and is connected to the data out bus comparator 152 of the memory. Similarly, the interrupt / connection queue, which is an internal register of the SCU50, can also be accessed, and a control signal ACT-IC-SR-B (1-2) indicating that some internal logic of the SCU50 is in use.
Is connected to the INT / CON write comparator 153. The control signal ADRU-GO from the control unit 54 during use of the memory device indicates that the upper memory device, that is, the memory devices 0 to 7 (200 to 20).
7) indicates whether it can be used, and also the control signal ADRL
-GO is a relatively low-level memory device, that is, memory device 8
-15 (208-215) is available and these control signals are connected to the memory comparator 154. The output of each of the comparators 150-154 is connected to a port request admission controller 156. Port request admission controller if the memory and bus required for the commanded operation are not in use and available for a predetermined future period (s) with the logic required for the commanded operation 156 outputs a predetermined specific request signal to the activity priority selection control device 56.

Referring to FIG. 6, a functional block diagram of activity priority selection controller 56 is shown. The port priority admission controller 160 receives a request present GO signal (PREQ-GO) from each of the port request controllers 52, one or more of which may be true, all of these signals for a period T-TIME. Within the same command level. Based on these inputs, the logic of the port priority admission controller 160 is
-TIME Make a decision to accept only one request,
Output the acceptance request signal (PX-ACPT-REQ) to the corresponding port. After some acceptance, the port priority is conditionally rotated at the beginning of the next period T. The port priority forwarding control device 161 is the port priority acceptance control device 1
Interface with 60. The port priority advance prohibition control device 161 receives the request presence signal of low priority (LPREQ-PRES) and the request presence signal of high priority (HPREQ-PRES) from each port request control device 52, and receives the command just received. Based on the higher priority pending requests within the level, the logic will allow the port priority admission controller 160 to
The rotation is prohibited, so it is determined whether it is allowed. The port priority selection controller 167, which receives the accept signal (ACPT) indicating which port had the accepted request, and other control signals, including high priority request signals from each port, is active. It provides a control signal to load the status register with the necessary information to perform the required operation, and a memory start (START-MEM) signal which is also connected to the busy controller 54 of the memory device.

Next, the priority order logic will be described. As described above, the activity priority selection control device 56 includes the port priority reception control device 160 and the port priority advance transmission prohibition control device 161.
And a port priority selection controller 162 and an active state selection controller 163. In FIG. 7, a logic diagram of the port priority acceptance controller 160 is shown.
The port priority acceptance controller 160 includes a first plurality of switches or rotary switches (ROT SW1 to ROT SW8) 201.
.About.208, each rotary switch having eight inputs or 0-7. These rotary switches use the signal P0-PREQ-
GO is the 0 input of the first rotary switch 201, the 7th input position of the 2nd rotary switch 202, the 6th input position of the 3rd rotary switch 203, the 5th input position of the 4th rotary switch 204. The fourth input position of the fifth rotary switch 205, the third input position of the sixth rotary switch 206,
7th rotary switch 207 2nd input position and 8
It receives the signal PX-PREQ-GO from each port to be connected to the first input position of the second rotary switch 208. Similarly, all remaining signals PX-REQ-GO are connected to predetermined positions on each of the remaining rotary switches 202-208. The output of each rotary switch is the corresponding NAND gate 21
Connected with 1-218. In addition, the complementary (ie, bar) output of each rotary switch is connected to each of its subordinate NAND gates in priority order as described below. NA
The first rotary switch 201 associated with the ND gate 211 has a higher priority than the second rotary switch 202, so the bar output of the first rotary switch 201 is the second NAND switch.
It is connected to the gate 212 and the NAND gates 213 to 218 below it. NAND gates form a priority tree of port priority admission control logic 160. A second plurality of switches, the steering switches 221-228, are connected to the priority tree so that the output of the second switch connects the acceptance signal to the proper port again based on priority rotation. . The selection positions of the steering switches 221-228 and the rotary switches 201-208 are provided with the selection control signal PRI-SW.
-SEL4,2,1 and 4A, 2A, 1A are connected respectively.
These selection control signals correspond to the same signal. That is, they are logically the same. As an example, when the select control signal has a binary number of 010, the third input terminal of each rotary switch 201-208 (ie, input to 2) is selected, thereby giving port 2 the highest priority. If port 2 performs the element, signal REQ1 will indicate acceptance, but steering switches 221-228 will also select 2 inputs. This corresponds to the receiving input on the 2nd input of the third steering switch 223 driving the signal P2-ACPT connected to port 2. Rotary switch
Each of 201-208 and steering switches 221-228 is manufactured by TI
This is the same type as the 74S151 type 8-to-1 selection switch.

The first NAND gate 211 outputs the request signal with the highest priority. The highest priority port is obtained by the select signal PRI-SW-SEL and rotated as described below. Initially, when the select inputs of the switch are all 0's, port 0 connected to input 0 of rotary switch 201 will have the highest priority. When the selection signal is equal to the binary number 001, the 1 input of each of the rotary switches 201-208 is enabled. At this point, P1-PREQ-GO, which is the input request signal for port 1, is input 1 for ROT SW1 201.
, And this input is connected to the highest priority NAND gate 211 in the priority tree, thus port 1 will have the highest priority. Furthermore, at this point, the input 1 of the second rotary switch 202, which is connected to the input request signal of the port 2, has the second highest priority, and such priority is given as the line goes down. It becomes a ranking. Therefore, each port has the highest priority NA in the priority tree according to the rotation scheme described below.
Can be used for ND gates.

Next, the prohibition of priority rotation will be described. In FIG. 8, a logic diagram of the port advancement forward control device 161 is shown. The port priority forwarding control device 161 responds to this request from each port by a low priority request presence signal and a high priority request presence signal, PX
-LPREQ-PRES and PX-HPREQ-PRES are connected respectively. The high priority request present signal and the low priority request present signal are respectively sent to the 2-to-1 selector (SE
L) connected to the corresponding 1 and 0 inputs of 341, 342. Connected to the select inputs of the selectors 341, 342 is the high priority request signal HPRI-REQ, which if there is a high priority request for any of the eight ports, this signal is It goes high, or a logical one, and operates to indicate that there is a high priority request on at least one port. The respective outputs from the selectors 341 and 342 are connected to predetermined inputs of the inhibition switches (INHSW) 301 to 306. The connection configuration described below is similar to the configuration described above regarding the wiring of the rotary switch, that is, the selector 341 indicating the request of port 0.
Is connected to the 0 position of the first prohibition switch 301, the 7th position of the second prohibition switch 302, the 6th position of the third prohibition switch 303, and so on. The third selector 345 also produces selection control signals corresponding to those previously described in connection with the rotary and steering switches. To describe the inhibit process, assume for example that the select control signal PRI-SW-SEL4B, 2B, 1B has the binary number 101. This corresponds to the selection of port 5 as having the highest priority because the 6th input terminal of rotary switches 201-208 (position 5) is selected, the signal of port 5 being as shown in FIG. Is connected to the input position 5 of the first rotary switch 201. In this case, the priority order is 5, 6, 7, 0, 1, 2,
Three and four. A high priority request is pending for port 5 and a high priority request is pending for port 7 for some reason, eg the memory required by port 5 is in use but port 7 The memory required by is available and therefore the port 7 request GO signal P7-RE
Since Q-GO exists, the port 5 request GO signal (P5-REQ
-GO) is assumed to be inactive. As a result, the port 7 request G connected to the input position 5 of the rotary switch 203
The O signal will give rise to the request 3 signal REQ3, which is connected to the input terminal 5 of the steering switch 228,
The switch also outputs an acceptance signal to port 7.
In this example, the output of the inhibit switch 301 will hold 0 because there is a high priority request signal for port 5 and the input of position 5 of the inhibit switch 301 is selected. As a result, the output of the inhibit switch 301 is connected to each of the inhibit NAND gates 321-326,
Each will have a 0 input at one of the input terminals of the inhibit NAND gate, resulting in an input 1 for each input of NOR gate 303. This results in the output of the logical value 0 of the priority advance advance prohibition signal (INH-PRI-ADV '), and the logical value 0 of the priority advance advance prohibition signal prohibits the advance advance of the priority order. It will be readily apparent that REQ3-GO will be a logical 1 if input port 5 does not have a pending request and port 6 does not have a pending request. The output of inhibit switch 301 will also be a logical one and the output of inhibit switch 302 will also be a logical one, resulting in a zero output of inhibit NAND gate 322. This output, which is connected to the NOR gate 330, will result in the output of a logical advance 1 of the priority advance inhibit signal, which inhibits the priority advance inhibit of the rotary switches 201-208. The switches 201 to 208 normally perform the advance operation.

In FIG. 9, some of the logic of the port priority selection controller 162 is shown. Selection control signal for rotary switch and selection switch PRI-SW-SEL1A, 2
When A, 4A and PRI-SW-SEL 1, 2, 4 are generated, they are output from selectors (SEL) 401, 402. The selection control selectors 401 and 402 output the selection control signal in both cases of low priority and high priority.
These selection control selectors are high priority registers (RE
The output of G) 411 is connected to the output of 1, and the output of the low priority register (REG) 412 is connected to the output of 0. The low priority register 412 holds the current spinning state (ie, the priority list of low command level ports) for low priority requests, and the high priority register 411 is the priority for high priority requests. Holds the state (ie, the priority list of high command level ports). Adder 421 connects the output of selector 402 to the B input, and the A input of adder 421 is connected to the input tree that represents the accepted port number. When a port is accepted and rotation is not prohibited, this port is placed at the bottom of the list of port priorities in the accepted command level, and the next port in the order receives the highest priority and thus rotation. Are rotated sequentially, only after an admission occurs, and the accepted port is placed at the bottom of the port priority list. The priority list remains the same until some acceptance signal is generated. The high priority signal HPRI-REQ is generated by ORing the high priority request signals from each of the ports PX-HPRI-REQ, this OR operation being performed by NOR gate 425. The high priority request signal is used to select the output of the high priority register 411 or the low priority register 412 via the selectors 401 and 402. Thus, for example, if the high priority situation is where port 0 was given the highest priority, the select control signal PRI-SW-S.
EL1,2,4 becomes binary number 000. If request for port 4
If the GO signal is available and no other port made the request, port 4 will be accepted. As a result, the rotary switch 20 having an input request for the port 4
An input position 0 of 5 will produce an output signal REQ5 of logical 1's. The bar outputs of all rotary switches above switch 5, i.e., switches 1-4, 201-204, have a bar output, such as a logic one, which results in the output of NOR gate 431 being a logic zero, REQ5-GO '. Will occur. Thus, the outputs of NOR gates 431, 432, 433 would be such that the outputs are 101 each. Furthermore, since requests of higher priority are not held in this example, the priority advance prohibition signal has the logical value 1, that is, the rotation operation is not prohibited. AN
Each of the D gates 435, 436 and 437 has a binary 101 output, and the A output of the adder 421 is 5. The current value corresponding to the select control signal in the high priority register 411 is 0, and in the next clock cycle the high priority register 411 will be incremented to contain the value 5. Therefore, in the next cycle, the select control signal has a value of 5, which gives port 5 the highest priority. Configuring the adder in the preferred embodiment of SCU 50 adds each cycle. in this way,
A count of 0 is added to adder 42 to maintain the same priority when no admissions are generated and priority advance is active.
The A input requests the value 0, which is set by 1 and at the same time. If there are no higher priority requests and there are lower priority requests, then the lower priority requests will be served.

Referring to FIG. 10, a functional block diagram of the circuitry used to generate the HOLD-REQ signal is shown. This request hold signal is determined to have been serviced a predetermined number of times prior to a pending relatively high high priority request with a relatively low high priority request,
A control signal sent to all ports 51 indicating that port 51 inhibits further requests from the device from connecting to the corresponding port request logic 52. Each time a relatively high priority request is withheld and simultaneously with the servicing of a request on a port, counter 520 is incremented and compared in comparator 530 with a predetermined value set in preset register 510. To be done. A preset count (ie value) in register 510 is set before the system has a higher priority port with some pending request locking out further requests from devices. It is some predetermined count that allows bypassing. This preset register 510 may be a manually set value, or it may be set by other logic in data processing system 10 via an interface (not shown). When the number of times a relatively high priority request is bypassed is equal to the value set in the preset register 510, the comparator (COMP) 530 will output one signal, which is then all the signals. Hold request connected to port 51. The preferred embodiment of port 51 includes logic that inhibits further requests from being accepted by port 51 once the signal HOLD-REQ has been initiated until all high priority type requests have been serviced. Including. A latch 540 for holding the signal HOLD-REQ is included. When the compare hold request signal (ie, the output of comparator 530) is generated, its duration depends on the next highest priority acceptance. If the next highest priority acceptance corresponds to the pending highest priority request, counter 520 is reset via gate 580 and the hold request signal is reset. If the next highest priority acceptance is not the highest pending priority request (ie, priority is not rotated), latch 540 causes AND gate 570 and OR gate 5
Set through 50. If Latch 540 is set, it remains set and port 0
Held by any of the pending high priority port request signals input to the OR gate 560 via port 7. This hold request signal then remains active until all high priority requests have been serviced.

In FIG. 11, a logic diagram of the hold signal generation circuit of FIG. 10 is shown. Counter 520 is implemented as a shift register 520 in the preferred embodiment. The comparator 530 of the preferred embodiment is an AND gate.
Consists of 531-534 and OR gate 535. The preset register 510 of the preferred embodiment is a count (or value)
It is a three-stage register for storing control information including, and includes a position for the least significant bit (LSB) of the count, a position for the most significant bit (MSB) of the count, and the control stage S1. As mentioned above, preset register 510
Can be loaded from some external source, as is well understood by those skilled in the art. Shift register 520
Has one input terminal SR connected to a logical one. If certain acceptance signals ACPT are generated and there is a high priority request HPRI-REQ, these signals will be a logical one. As explained previously, if a pending relatively high priority request is not serviced, priority rotation is prohibited and the priority advance inhibit signal is issued.
INH-PRI-ADV has a logical value of 1. If the acceptance signal is a logical one and the signal INH-PRI-ADV is a logical one indicating that priority rotation is prohibited, it means that a relatively low priority request has been serviced. , 1 is preferably added to the counter (shift register) 520. In this condition, NAND gate 545 has a logic zero output, and OR gate 546 produces a one output. Assuming that the output of latch 540 is logical 0, NAN
The output of D-gate 547 is a logical 1 from the above conditions,
The output from the OR gate is a logical 0. Therefore, the control signals S0 and S1 of the shift register have the logical value 01, respectively, and as a result, the shift register 520 inputs the logical value 1 to the first position of the shift register 520. Each time shift register 520 is forwarded right, a logical one value shifts right one position, which is equivalent to adding a count of one. The contents of shift register 520 are compared to the value set in preset register 510. In the preferred embodiment, a count of 1-4 (ie,
The binary value 0-3) becomes valid and is compared in the comparator 530. When the shift register 520 reaches the count which is the output of the comparator 530 set in the preset register 510, the OR gate 535 becomes a logical value 1 and the hold request signal HOLD-REQ is generated. Once the hold request signal occurs, hold this hold request signal, ie, latch by latch 540, if acceptance of the next port's high priority request inhibits the port's high priority advance. You can Latch 540 holds NAND gate 55 as long as a high priority request signal is present on any port.
Held by 1.

If an acceptance signal ACPT is generated, i.e. there is a high priority request and priority forwarding is not prohibited, i.e. the signal INH-PRI-ADV is a logic 0, a NAND gate The output of 545 is a logical one and the output of NAND gate 547 is a logical zero. In this case, the port with the highest priority is being serviced. this is,
Not a condition that means to generate a hold request signal,
As a result, the outputs of the OR gates 546 and 548 both have a logical value of 1, and the control signals S0 and S1 of the shift register have a logical value of 1, respectively.
It will be 11. This condition resets the shift register 520 to the value zero. If no acceptance signal is generated, there is no higher priority request, and the hold request signal is not pending, then the outputs of OR gates 546 and 548 will each be a logical 00 shift register control signal SO, S1 will be generated, and no operation will effectively occur in the shift register 520. After all pending high priority requests have been serviced, the input from the NAND gate connecting the outputs of NAND gate 551 and comparator 552 is such that it resets latch 540, thus resetting latch 540. It will be. The shift register 520 of the preferred embodiment can be implemented using a TI 74LS158. In a preferred embodiment,
This is also present when the signal HOLD-REQ is present, causing a low priority request signal (INH-LRPI-REQ) using position S1 in register 510 which can also be preset or set dynamically by DPS10. Inhibit all lower priority port request services. Although the preferred embodiment of the present invention is for two command levels (ie, high and low), those skilled in the art will find that the present invention is also directly applicable to systems having multiple command levels. Be understood.

In FIG. 12, a functional block diagram of some of the activity registers 58 is shown. As mentioned before, SC
The preferred embodiment of the U50 allows 5 activities to be simultaneously accepted in the process. Three of the activity registers (cycle length, data in and data out) are shift registers, and each position of this shift register uses a predetermined logic with SCU 50 and / or memory 20. It indicates the time slot to be used, which allows the SCU 50 to know when various hardware or logic is in use.

A logic diagram of the port request controller 52 is shown in Figures 13A and 13B, which together comprise Figure 13. The command decoder 155 has three multiplexers, namely M
UX1, MUX2, MUX3, and PX from each port
-CMD- (0-5) is accepted. In addition, various control signals from the activity register 58 and the memory device busy controller 54 are combined to provide the port request acceptance controller 15
Entered for 6. If there is a high priority request, the activity is not full, the form of the directive is for memory, memory is available, memory is
The bus is available for the specified command, and if there is a request, the gate 160 outputs the port high priority request signal PX-PPRI-REQ '. Command signal bit 2
The low is used in combination with the request signal to produce a low priority request present signal (PX-LPREQ-PRES) for the port at gate 161, gate 162 combines command bit 2 high with the request present signal for the higher priority port. Request presence signal (PX-HPREQ
-PRES). If a high priority request exists and is available when all logic and hardware operations are performed, the high priority request GO signal generated by gate 163 is OR'd by NOR gate 164 to obtain the port priority. Generates a GO request signal (PX-PREQ-GO). If there is a low priority request and the request is a GO condition, i.e. all logic and hardware required by the operation is available at a predetermined point in time to perform the requested operation, and from any other port If there is no higher priority request signal, port priority request GO signal PX-PR
The EQ-GO will be generated by the output of gate 165. In this way, low priority requests from each port are separated from high priority requests. Therefore, a request with a high priority will be processed first, and in particular, the request GO signal input to the rotary switches 201 to 208 will be a GO signal with a high priority or a GO signal with a low priority, The two are not mixed and the high priority request signal will always have a preference over the low priority request signal.

Referring to FIG. 14, a functional block diagram illustrating the data register and flow of data through the SCU 50 is shown.

Figure 15 shows a timing diagram of the memory 20 interface showing the time required for reading or writing 2 words, 4 words, 6 words and 8 words (2W, 4W, 6W and 8W respectively). . In addition, the timing for read-after-write (RAR) is also shown.

While we have set forth what is considered to be the preferred embodiments of the invention, it will be apparent that many changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the appended claims are intended to cover all such changes and modifications that fall within the true scope of the invention.

[Brief description of drawings]

1 is a schematic diagram showing a data processing system including a system controller in which the circuit of the present invention can be found, FIG. 2 is a functional block diagram showing the system controller of the data processing system in FIG. 1, and FIG. The figure shows two for the same storage device
Timing diagram showing requests from two different ports, No. 4
FIG. 6 is a timing diagram showing simultaneous requests from two different ports. FIG. 5 is a functional block diagram showing a port request control device of a tastem control device using the circuit of the present invention.
FIG. 7 is a functional block diagram showing an active priority selection controller of a system controller using the circuit of the present invention. FIG. 7 is a port of the active priority selection controller of FIG. 6 using the circuit of the present invention. Logic diagram showing the priority acceptance control device,
FIG. 8 is a logic diagram showing a port priority progress prohibition control device of the active state priority selection control device of FIG. 6 using the circuit of the present invention, and FIG. 9 is a partial logic diagram showing the port priority selection control device. FIG. 11 is a functional block diagram showing a circuit of the present invention, FIG. 11 is a logic diagram showing a preferred embodiment of the circuit of the present invention shown in FIG. 10, and FIG. 12 is a partial functional block showing an activity status register of a system controller. FIGS. 13A and 13B are partial views constituting a logic diagram of the port request control device of the preferred embodiment of the present invention, and FIG. 14 is a functional block diagram of a data digitizer showing a data flow in the system control device. , And FIG. 15 are timing diagrams showing a preferred embodiment of the memory interface of the system controller. 10 …… Data processing system (DPS), 20 …… Memory, 3
0 …… Central processing unit (CPU), 31, 41 …… Connecting line, 40 ……
Input / output I / O device, 50 ... System control unit (SCU), 51 ...
… Port, 52 …… Port request controller, 54 …… Memory device busy controller, 56 …… Activity priority selection controller, 58 …… Activity register, 152 …… Memory data out bus comparison Device, 153 …… INT / CON write comparison device, 156 …… Port request acceptance control device, 160 …… Port priority acceptance control device, 161 …… Port priority advance prohibition control device, 162 …… Port priority selection Controller, 163 ... Activity selection controller, 165 ... Gate, 16
7 ... Port priority selection control device, 201-208 ... Rotation switch (ROT SW1-ROT SW8), 211-218 ... NAND gate, 220 ... Bus, 221-228 ... Steering switch, 301-30
6 …… Inhibition switch (INHSW), 321-326 …… Inhibition NAND gate, 330 …… NOR gate, 401, 402 …… Selection control selector, 411 …… High priority register (REG), 412 …… Low priority Register (REG), 421 ... Adder, 431-433
...... NOR gate, 435-437, 570, 531-534 …… AND gate, 510 …… Preset register, 520 …… Counter,
530 …… Comparator (COMP), 540 …… Latch, 550, 5
60 …… OR gate, 580 …… gate, 535 …… OR gate, 54
5,547,551 …… NAND gate, 546,548 …… OR gate, 5
52 …… Comparator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-51-132733 (JP, A) JP-A-58-72230 (JP, A) JP-A-57-71032 (JP, A) JP-A-55- 52153 (JP, A)

Claims (5)

[Claims] 1. At least one subsystem (2) in response to an access request from a plurality of devices (30, 40) operatively connected to respective ports of a system controller.
0) in a data processing system comprising a system controller (50) for controlling access to
The ports have predetermined port priorities that are interrelated for the granting of access requests from each port, the port priorities being the conditions under which an access request is granted access to the subsystem. Rotatably, the system controller includes circuitry for preventing lockout of certain pending higher priority requests, the circuit comprising: (a) accessing pending higher priority requests; When a request is not granted, a counter (520) for counting the number of times a request is allowed to access is provided, and as a result of the counting, a count value temporarily stored in the counter is provided, and (b) the counter Operatively connected, comparing the count value in the counter with a predetermined value (510) and when the count value is equal to the predetermined value, a control signal (HOLD-REQ And a predetermined value is the number of times the data processing system allows bypassing a relatively high priority request pending, and the control signal to each port. A circuit connected to inhibit further requests for access from the plurality of devices from being accepted by the system controller. 2. Each of the access requests is made at a particular one of a plurality of command levels, the command levels having a predetermined interrelated priority and the circuit having different command levels. The pending according to claim 1, characterized in that when a plurality of requests made at a level are simultaneously pending, access is granted to the request made at the highest priority command level. A circuit that prevents lockout of relatively high priority requests of. 3. After the high priority request connected to the comparison device has gained access, all pending high priority requests are sent if the request is not the highest priority pending at that time. Preventing lockout of pending higher priority requests according to claim 1, further comprising means (540) for keeping said control signal valid until access is obtained. Circuit to do. 4. Resetting means (580) connected to said counter for resetting said counter after a higher priority request has gained access and no further higher priority requests are pending. A circuit for preventing lockout of a pending higher priority request according to claim 1. 5. A data processing system having a plurality of subsystems including a system controller (50),
The system controller has a plurality of ports for controlling access to at least one subsystem (20) of the data processing system, the ports having a plurality of devices (30, 40) operatively connected thereto. ) In response to an access request command from the device, each of the access requests provided by the device to the port has a priority of one of a plurality of command priority levels, one of which is the highest. And each port of the system controller has a different port priority associated with it for each given command priority level and is connected to the given port with the highest port priority. When an access request for a device is granted by the system controller, the port priority level of the port for the given command priority level. Is conditionally rotated, the system controller including circuitry for preventing lockout of access requests having higher command priority levels or higher port priorities, the circuit comprising: (a) higher command priority While an access request command with priority or higher port priority is pending,
A counter device (520) is provided for counting the number of times an access request command having a lower command priority level or a lower port priority is granted access by the system controller, the counter device having a temporary device therein. (B) is operatively connected to the counter device and compares the count value in the counter device with a predetermined value (510) so that the count value is previously stored. When it is equal to the specified value,
A comparator device (530) for generating a control signal (HOLD-REQ) is provided, said control signal being connected to each port of said system controller and further from said plurality of devices connected to said port. A circuit characterized by prohibiting acceptance of an access request command for the port.