JPH0730425A - D/a converter - Google Patents

Abstract

PURPOSE:To provide a D/A converter form a PCM codec having a small group delay value. CONSTITUTION:A signal outputted from a selection means 2 by applying interpolation of 8 times to 8kHz PCM data linearly converted into 14 bits and outputted from a code conversion means 1 is inputted to a digital low pass filter(LPF) 3. Namely a signal obtained by executing constant interpolation 7 times after one input of 8kHz input data is inputted to the LPF 3. Consequently sampling and holding time can be omitted and a group delay value can be limited to a range capable of following CCITT recommendation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a MOS LS.
The present invention relates to a DA converter for a PCM codec receiving system realized by using a digital filter formed on I and a digital Δε modulator, and a DA converter having a small group delay.

[0002]

2. Description of the Related Art Conventionally, a PCM codec receiving system DA converter realized by using a digital low-pass filter and a digital Δε modulator interpolates an input signal and changes a sampling frequency in order to easily remove spurious noise by a digital filter. The input is performed by raising it and inputting it to the digital filter, and the configuration is as shown in the block diagram of FIG. That is, in order to interpolate (interpolate) the digital code input data, the input data is held (sampled and held) using the storage means 11, and the same data converted into the linear code by the code conversion means 12 is Inputting to a digital low pass filter was performed until data was input. The output of the digital low-pass filter 13 is input to the digital Δε modulator 14, the output of the digital Δε modulator 14 is input to the analog filter 15, and the analog filter 15 outputs an analog signal.

[0003]

However, in the DA converter as described above, the sample delay of the input data causes a group delay of half the input data interval. Especially by digital filter CC
Realizes the frequency characteristics specified in ITT Recommendation G714,
In a DA converter that changes to high-speed (for example, 128 times the input data rate) low bit (for example, 1 bit) data by a digital ΔΣ modulator and removes high frequency noise components by SCF (switched capacitor filter), the operation of the digital filter 62.5μs by sample hold, about 150μs by filter function, and about 20 by ΔΣ modulator
Due to μs and SCF, the total group delay time becomes about 260 μs in about 30 μs, and it was extremely difficult to realize a circuit that complies with the group delay allowable value of 240 μs in Recommendation G714. In addition, since the digital Δε modulator generates a large tone signal output with respect to zero input, some countermeasure is required to suppress the generation of this tone signal.

Therefore, an object of the present invention is to provide a DA converter that solves the above problems.

[0005]

In order to achieve the above object, the present invention provides a DA converter for interpolating a digital code compressed according to the μ-law rule or the A-law rule and converting it into an analog signal. Code conversion means for converting an input into a linear code and outputting it, constant setting means for outputting a predetermined constant code, and only one of the output of the code conversion means and the output of the constant setting means is selected. Selection means for outputting, a digital low-pass filter having the output of the selecting means as an input, a digital Δε modulator having the output of the digital low-pass filter as an input, and an output of the digital Δε modulator as an input and outputting an analog signal It is characterized by comprising an analog filter.

[0006]

According to the present invention, in a PCM codec of 8 KHz and 8 bits, the delay time is reduced by inserting a constant. In particular, when the input data is used only once and the same constants are inserted in all other cases, the group delay is 62.5 μs compared to the conventional case where the input data is sampled and held until the next data is input. Time is running out. Furthermore, in the DA converter that digitally stores the 8-bit PCM codec input data,
The RAM for storing the input data or the eight flip-flops is omitted, or more storage circuits are omitted when storing the input data converted from the linear data, and the silicon on the MOS LSI is occupied. The area is reduced.

When the constant to be inserted is other than zero, the digital low-pass filter output has an offset even with respect to the zero signal input, and the offset value can be input to the Δε modulator. As a result, an operation equivalent to the operation of adding an offset to the input of the Δε modulator in order to reduce the tone signal generated from the Δε modulator, which is conventionally performed, can be realized without an adder.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. As input data, 8 KHz, 8-bit μ-Law or A-L
The data according to aw is converted by the code conversion means 1 into 14
It is converted to bit linear data, and is converted to 6 via the selecting means 2.
5th-order digital low-pass filter 3 operating at 4 KHz
To enter. The output from the digital low-pass filter 3 operates at 1024 KHz, and is input to a third-order digital ΔΣ modulator 4 that samples and holds the input.
(Switched capacitor low pass filter)
An analog signal is obtained at the output end of the analog filter 5.

The DA converter having such a structure could be manufactured by a double metal, double polysilicon 1.2-micron CMOS process.

Here, the digital low-pass filter 3 is obtained by subjecting the 8 KHz PCM input data linearly converted to 14 bits from the code converting means 1 to 8 times interpolation by the selecting means 2. Is entered. That is, 6 is a constant setting means, which sets a digital constant (including "0") having the same number of bits as the code converting means 1 and inputs this to the selecting means 2 for interpolation. In the selection means 2, at a timing as shown in FIG. 4, the input data of 8 KHz from the code conversion means 1 is followed by the constant of 7 times (1 LSB of 14-bit linear data) from the constant setting means 6. It is inserted and input to the digital low pass filter 3. The constant code output from the constant setting means 6 can be introduced into the digital low-pass filter by using a switch or logic gate selecting means, but in this example, the constant setting means 6 is used.
The selection circuit 2 and the selection means 2 are logic circuits that are simultaneously realized by AND and OR gates.

That is, as shown in FIG. 3, the selection means 2
Inserts an AND gate 7 and an OR gate 8 in an input path of 14-bit parallel data from the coded conversion means 1, and inputs a control signal to one input end of the gate 7 at one input end of the gate 7. An input signal to the digital low-pass filter 3 is set to 1 by inputting an inverted signal of the control signal to the end and setting this control signal to "Low".

In the group delay value of the DA converter having the above-mentioned structure, the time for sampling and holding is omitted.
Approximately 150μs by filter function, approximately 20μs by digital ΔΣ modulator 4, approximately 30μ by SCF5
s, about 20 μs due to the operation timing of the digital low-pass filter 3, and the total was about 220 μs. Therefore, it is possible to realize a DA converter that can comply with the allowable value of 240 μs in the CCITT recommendation. At the time of zero input, no tone specific to the digital Δε modulator was observed in the analog output signal.

[0014]

As described above, according to the present invention, by using a specific constant code with a small group delay value, the tone of the digital Δε modulator does not occur.
An A converter can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a diagram showing a specific example of selecting means.

FIG. 4 is a diagram illustrating interpolation in input data to a digital low pass filter.

[Explanation of symbols]

 1 code conversion means 2 selection means 3 digital low-pass filter 4 digital ΔΣ modulator 5 analog filter 6 constant setting means

Claims (1)

[Claims] 1. A DA converter for interpolating a digital code compressed according to the μ-Law rule or A-Law rule and converting it into an analog signal, and a code converting means for converting the digital code input into a linear code and outputting the linear code. , A constant setting means for outputting a predetermined constant code, a selecting means for selecting and outputting only one of the output of the code converting means and the output of the constant setting means, and the output of the selecting means And a digital low-pass filter, a digital Δε modulator having an output of the digital low-pass filter as an input, and an analog filter having an output of the digital Δε modulator as an input and outputting an analog signal. .