JPH0730399A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To supply a stable output waveform to the output load of an output buffer circuit even when an external load resistance is added to the output load. CONSTITUTION:When an input terminal IN falls from an 'H' level to an 'L' level and the gate signal S10 of an NMOS 10 for output rises to the 'H' level to make an output waveform fall, the gate signal S10 gradually rises by the ON resistance of a PMOS 12 at the time of the start of the variation of the pertinent gate signal S10. The PMOS 13 turns ON after a certain period of time set by a delay circuit 15 later, so the gate signal S10 rises speedily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a semiconductor memory device having an output buffer circuit for charging and discharging an output load.

[0002]

2. Description of the Related Art Conventionally, in an output buffer circuit provided in a semiconductor integrated circuit device, as a technique for suppressing power supply noise generated at the time of switching of the output buffer circuit, for example, there is one described in the following document. It was
Reference: Japanese Patent Application Laid-Open No. 1-212023 FIG. 2 is a circuit diagram showing a configuration example of the conventional output buffer circuit described in the reference. This output buffer circuit is provided in a semiconductor integrated circuit device such as a semiconductor memory device, and an input terminal IN for inputting a signal in the semiconductor integrated circuit device is connected to an input terminal of an output control inverter 1. ing. The output terminal of the inverter 1 has a P-channel MOS transistor for outputting "H" level (hereinafter referred to as PMO).
N) MO for 2) and “L” level output
The gates of S transistors (hereinafter referred to as NMOS) 3 are commonly connected, and their PMOS 2 and NMOS 3 are connected in series between the power supply potential VCC and the ground potential VSS. An output terminal O is provided at the connection point between the PMOS2 and the NMOS3.
UT is connected. The gate of the NMOS 5 is connected to the output terminal of the inverter 1 via the delay circuit 4, the drain of the NMOS 5 is connected to the output terminal OUT, and the source is connected to the ground potential VSS. A load capacitance C, which is an external load, is connected to the output terminal OUT. In this type of output buffer circuit, the output transistors for discharging the external load capacitance C are NMOS3 and NMOS.
It is divided into five. Then, when changing the output level of the output terminal OUT from the “H” level to the “L” level, first, the “L” level is input to the input terminal IN, which is inverted by the inverter 1 to be the “H” level. The NMOS 3 is turned on by the potential of the. Then, the charge accumulated in the load capacitance C is discharged to the ground potential VSS through the NMOS3. Next, after the "H" level output of the inverter 1 is delayed by the delay circuit 4 for a certain period of time, the NMOS 5 is turned on, so that the charge of the load capacitance C is discharged to the ground potential VSS through the NMOS 5. Such an NMO
By the operations of S3 and 5, the transient current that flows when the external load capacitance C is discharged is suppressed, and the power supply noise is suppressed.

[0003]

However, in the conventional circuit configuration shown in FIG. 2, when an open drain circuit as shown in FIG. 3 is used and external load resistors R1 and R2 are added to its output terminal OUT, When the external load capacitance C is small, there are the following problems and it is difficult to solve them. FIG. 3 is a circuit diagram of another conventional output buffer circuit provided in the semiconductor integrated circuit device, and FIG. 4 is a voltage waveform diagram thereof. Elements common to those in FIG. 2 are designated by common reference numerals. ing. The output buffer circuit of FIG. 3 has a circuit configuration in which the PMOS 2 for “H” level output in FIG. 2 is omitted. 4, V _in is the input voltage of the input terminal IN, V _out 1 is the output voltage when the load capacitance C is small, V _out 2 is the output voltage when the load capacitance C is large, and T out
1, T2 and T3 are time. An external load capacitance C and load resistors R1 and R2 are connected to the output terminal OUT of FIG.
If the load capacitance C is small, the falls in the input voltage V _in is at the "L" level of the input terminal IN, it is NMOS3 is turned on by the inverted by "H" level potential by the inverter 1, the output terminal OUT Output voltage V _out 1 is pulled down to the “L” level side. Then, the NMOS 5 is turned on by the output of the delay circuit 4, and the output voltage V
_out 1 is further pulled down to the “L” level side. That is,
During the falling of the output voltage V _{o ut} 1, only NMOS3 is first turned on, the load capacitance C is small time T
Change rapidly in 1. However, the load resistance R
Due to 1 and R2, the output voltage V _out 1 does not reach the complete “L” level at the time T2, and then the output voltage V _out 1 changes to the complete “L” level by the operation of the NMOS 5 which is turned on after a certain time at the time T3. To do. Thus, at time T2, the waveform of the output voltage V _out 1 becomes extremely gentle (stepwise), which causes a malfunction to the integrated circuit in the next stage connected to the output terminal OUT, which is a problem. . SUMMARY OF THE INVENTION The present invention solves the problem that the conventional technique has by solving the problem that an external load resistance is added to the external load of the output buffer circuit and the output waveform becomes stepwise when the external load capacitance is small. A semiconductor integrated circuit device provided with an output buffer circuit that suppresses power supply noise generated during switching of a buffer circuit and operates without impairing high-speed performance.

[0004]

In order to solve the above problems, the present invention has an output MOS transistor having a drain connected to an output terminal to which an output load is connected and a source connected to a ground potential. In a semiconductor integrated circuit device such as a semiconductor memory device, an output buffer circuit for applying a power supply potential to the gate of the output MOS transistor based on an input signal and outputting an “L” level potential to the output terminal is provided. A plurality of paths for supplying the power supply potential to the gate of the MOS transistor are provided. One path of the plurality of paths is connected to the power supply potential and has a resistance value larger than that of the other path, and a first resistance element connected in series to the resistance element and controlled to be conducted by the input signal. MOS transistor. Further, the other path includes a delay circuit that delays a change in the input signal in a certain direction, and a second MOS transistor that is conduction-controlled by an output of the delay circuit and supplies the power supply potential to a gate of the output MOS transistor. And have.

[0005]

According to the present invention, since the output buffer circuit provided in the semiconductor integrated circuit device is configured as described above,
For example, when a load resistance is attached to an output load such as an open drain output buffer, one path having a resistance element gradually changes the gate potential of the output MOS transistor at the start of the change of the gate potential, and , The gate potential of the first MOS transistor is rapidly changed after a certain period of time by the delay circuit provided on the other path. Therefore, the above problem can be solved.

[0006]

First Embodiment FIG. 1 shows a first embodiment of the present invention and is a circuit diagram of an output buffer circuit provided in a semiconductor integrated circuit device such as a semiconductor memory device. This output buffer circuit is an open drain output buffer circuit, and has an input terminal IN for inputting a signal in the semiconductor integrated circuit device, an output terminal OUT to which an external load is connected, and an NMOS 10 for "L" level output. , The drain of the NMOS 10 is connected to the output terminal OUT, and the source is connected to the ground potential VSS. The gate of the NMOS 10 is provided with first and second paths for supplying the power supply potential VCC to the gate. The first path has PMOSs 11 and 12, the source of the PMOS 11 is connected to the power supply potential VCC, the drain is connected to the source of the PMOS 12, and the gate is connected to the input terminal IN. The PMOS 12 has a drain connected to the gate of the NMOS 10 and a gate connected to the ground potential VSS. The second path has the PMOS 13, the source of the PMOS 13 is connected to the power supply potential VCC, and the drain is connected to the gate of the NMOS 10. The gate of the NMOS 10 is connected to the drain of the NMOS 14 which supplies the ground potential VSS to the gate, and the source of the NMOS 14 is connected to the ground potential VS.
The S and gate are connected to the input terminal IN, respectively.
A PMOS is connected to the input terminal IN via a delay circuit 15.
Thirteen gates are connected. When the input signal of the input terminal IN transits from "H" to "L", the delay circuit 15 delays the input signal by a certain time and supplies it to the gate of the PMOS 13, and the input signal is changed from "L" to "H". When transitioning to ", PM is applied to the input signal without delay.
It is a circuit for transmitting to the gate of the OS 13, and is composed of various circuits such as a CR time constant circuit and a gate circuit. The output terminal OUT is connected to a load capacitance C that constitutes an external load and load resistors R1 and R2. The load capacitance C is connected between the output terminal OUT and the ground potential VSS. The load resistor R1 is connected between the output terminal OUT and the power supply potential VCC, and the load resistor R2 is connected to the output terminal OUT.
And ground potential VSS. In addition, NM
The gate signal of OS10 is S10. Also, the PMOS
The on resistance of 12 has a large resistance value.

Next, referring to FIG. 5, the operation (a) when the output waveform falls and the operation (b) when the output waveform rises in the output buffer circuit shown in FIG. 1 will be described. FIG. 5 is a voltage waveform diagram when the output waveform in the output buffer circuit of FIG. 1 falls. V _in is an input voltage of the input terminal IN, V _out 11 is an output voltage when the load capacitance C is small, V _out 12 is an output voltage when the load capacitance C is large, and T1 and T2 are times. (A) Operation at Fall of Output Waveform As shown in FIG. 5, when the input terminal IN is at “H” level, the PMOS 11 is in the off state, the PMOS 12 is always in the on state, and the delay circuit 15 is in the positive logic so that the PMOS 13 Is off. Furthermore, since the NMOS 14 is in the ON state, the gate signal S10 becomes "L" level
10 is in the off state. When the power supply potential VCC is, for example, 5V, the output terminal OUT has an output level of about 3V (output “H”) due to external load resistors R1 and R2.
Level and). When the input terminal IN changes from the "H" level to the "L" level at time T1, the PMOS 11 is turned on and the NMOS 14 is turned off, and the gate signal S10 is changed from the "L" level to the "H" level through the PMOSs 11 and 12. "It changes to the level.
At this time, the gate signal S10 changes gently depending on the on-resistance value of the PMOS 12. Then, the output voltages V _out 11 and V _out 12 of the output terminal OUT are passed through the NMOS 10.
Starts changing from "L" level to "H" level. Next, the input voltage V _in is delayed by the delay circuit 15 and the PMOS
Since it is given to the gate of No. 13, time T2 after a fixed time
, The PMOS 13 is turned on, and the gate signal S
10 changes more quickly than time T1. For this reason,
Output voltage V _{out of the} output terminal OUT through the NMOS 10.
11, V _out , 12 also change more quickly than time T1. This change is particularly effective when the output voltage V _out 12 is when the load capacitance C is large. As described above, since the gate signal S10 is gently changed at the time T1, the transient current flowing to the ground potential VSS can be suppressed and the power supply noise can be suppressed. Moreover, since the gate signal S10 is changed rapidly at the time T2, high speed can be provided. Especially, the capacitive load C
Is high, the output voltage V _out 12 has high speed. Since the gate signal S10 constantly keeps changing from the "L" level to the "H" level, the waveforms of the output voltages V _out 11 and V _out 12 at the output terminal OUT do not become extremely gentle.

[0008] (b) the input voltage V _in the operating input terminal IN at the rise of the output waveform is "L" level to "H"
When it changes to the level, the PMOS 11 turns off, and NM
The OS 14 is turned on. When the input voltage V _in changes from “L” to “H” level, the PMOS 13 causes the NMO
The input voltage V _{in is set} so that a through current does not flow to S14.
However, the delay circuit 15 does not delay and the PMOS1
It is sent to Gate 3. For that reason, the input voltage V _in is changed from the "L" level to the "H" level, PMOS
Since 13 is turned off, the gate signal S10 changes from "H" level to "L" level through the NMOS 14, and the NMOS 10 is turned off. When the NMOS 10 is turned off, the output voltages V _out 11, V _out , 12 of the output terminal OUT are caused by the functions of the external load resistors R1, R2.
Becomes "H" level. As described above, in the output buffer circuit of the present embodiment, the gate signal S10 of the NMOS 10 is gradually changed at the time of its operation, and is rapidly changed after a certain period of time, so that the power supply noise generated during the operation is suppressed. be able to. Moreover, the output terminal OU
Even if external load resistors R1 and R2 are added to T,
Output voltage V _out 11 having a stable waveform with respect to an external load,
V _out 12 can be supplied.

Second Embodiment FIG. 6 is a circuit diagram of an output buffer circuit provided in a semiconductor integrated circuit device showing a second embodiment of the present invention. Elements that are common to the elements are given common reference numerals. Although this output buffer circuit is an open drain output buffer circuit as in the first embodiment, the source of the PMOS 13 is the power supply potential VCC in FIG.
In the present embodiment, the PMOS 1 is connected to
It differs from the first embodiment only in that the source of No. 3 is connected to the drain of the PMOS 11. The on resistance value of the PMOS 12 is set to a value larger than the on resistance value of the PMOS 13. In this embodiment, the gate signal S11 of the NMOS 10 for "L" level output basically has the same operation waveform as the gate signal S10 of the first embodiment.
The difference from the first embodiment is that the source of the PMOS 13 is P
Since it is connected to the drain of the MOS 11, the through current from the PMOS 13 to the NMOS 14 when the output waveform rises is suppressed, and the other advantages are almost the same as those of the first embodiment.

Third Embodiment FIG. 7 is a circuit diagram of an output buffer circuit provided in a semiconductor integrated circuit device showing a third embodiment of the present invention. Elements that are common to the elements are given common reference numerals. This output buffer circuit is an open drain output buffer circuit as in the first embodiment. However, in the first embodiment, the gate of the PMOS 12 is connected to the ground potential VSS. P
The gate of the MOS 12 is the inverting output terminal 15 of the delay circuit 15.
It differs from the first embodiment only in that it is connected to a. The on resistance value of the PMOS 12 is set to a value larger than the on resistance value of the PMOS 13. N in this embodiment
The gate signal S13 of the MOS10 performs basically the same operation as the gate signal S10 of the first embodiment. The difference is that
When the gate signal S13 changes from the "L" level to the "H" level when the output waveform falls, the PMOS 12 is on and the PMOS 13 is off at time T1 in FIG. Therefore, the gate signal S13 changes gently, and the PMOS 12 changes at a time T2 after a certain time.
Is turned off, the PMOS 13 is turned on, and the gate signal S13 changes rapidly. Therefore, substantially the same advantages as the first embodiment can be obtained. The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, there are two paths for supplying the power supply potential VCC to the gate of the NMOS 10 for "L" level output, but three or more paths may be provided. Also, PMOS1
1 and the gate side of the NMOS 14 and the input side of the delay circuit 15 may be provided with the conventional output control inverter 1 as shown in FIG.

[0011]

As described in detail above, according to the present invention, in the output buffer circuit provided in the semiconductor integrated circuit device, a plurality of paths for supplying the power supply potential to the gate of the output MOS transistor are provided, One of the paths has a resistance element having a larger resistance value than the other path,
Since the other path has the delay circuit, it gradually changes by one path when the gate potential of the output MOS transistor starts to change, and the gate potential changes quickly by the other path after a certain period of time elapses. Therefore, power supply noise generated when the output buffer circuit charges and discharges the output load can be suppressed, and malfunction of the integrated circuit due to the power supply noise can be prevented. Moreover, even when an external additional resistance is loaded, an output signal having a stable waveform can be supplied to the output load, so that the malfunction of the integrated circuit at the next stage connected to the output terminal can be prevented properly.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit in a semiconductor integrated circuit device showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output buffer circuit in a conventional semiconductor integrated circuit device.

FIG. 3 is a circuit diagram of another output buffer circuit in the conventional semiconductor integrated circuit device.

FIG. 4 is a voltage waveform diagram of FIG.

FIG. 5 is a voltage waveform diagram of FIG.

FIG. 6 is a circuit diagram of an output buffer circuit in a semiconductor integrated circuit device showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an output buffer circuit in a semiconductor integrated circuit device showing a third embodiment of the present invention.

[Explanation of reference signs] 10 NMOS (output MOS transistor) 11 PMOS (first transistor) 12 PMOS (resistive element) 13 PMOS (second MOS transistor) 14 NMOS 15 delay circuit C load capacitance IN input terminal OUT output terminal R1 , R2 Load resistance VCC Power supply potential VSS Ground potential

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03K 17/16 H 9184-5J 17/687 G11C 11/34 354 A 9473-5J H03K 17/687 F

Claims (1)

[Claims] 1. An output MOS transistor having a drain connected to an output terminal to which an output load is connected and a source connected to a ground potential, and a power supply potential is applied to a gate of the output MOS transistor based on an input signal. In a semiconductor integrated circuit device including an output buffer circuit that outputs an “L” level potential to the output terminal, a plurality of paths for respectively supplying the power supply potential to the gate of the output MOS transistor are provided, and the plurality of paths are provided. One of the paths includes a resistance element that is connected to the power supply potential and has a larger resistance value than the other paths, and a first MOS transistor that is connected in series to the resistance element and that is conductively controlled by the input signal. The other path has a delay circuit that delays a change in the input signal in a certain direction, and a conduction circuit controlled by an output of the delay circuit. And a second MOS transistor for supplying the power supply potential to the gate of the output MOS transistor.