JPH07302842A - Load drive circuit - Google Patents

Abstract

PURPOSE:To increase current between the source and drain of a second element, improve load driving capability of the second element and increase the switching speed of a load drive circuit by permitting the gate oxide film of the second element to be thinner than the gate oxide film of a first element. CONSTITUTION:Since MOS transistors M3, M4 and M6 do not need a structure that has high breakdown strength, the gate oxide films are permitted to be thinner compared with those of MOS transistors Ml, M2 and M5. The mutual conductance of the MOS transistors is increased by thinning the gate oxide films of the MOS transistors M1, M2 and M5 in this manner. Thus, switching speed is increased by the improvement of driving performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load drive circuit for driving a load by converting a signal having a low amplitude level into a signal having a high amplitude level and applying a high voltage to the load based on the signal. For example, the present invention relates to a technique effectively applied to a display drive circuit.

[0002]

2. Description of the Related Art Examples of displays include liquid crystal displays, plasma display panels, electroluminescence displays, fluorescent display displays and the like. Since liquid crystal displays are relatively low in cost, they are used in portable word processors, small color televisions, and the like. Also, plasma display panel,
The electroluminescent display is also applied to personal computers and the like by taking advantage of its features such as brightness, quick response, and wide viewing angle. The display drive circuit is for driving such a display, and is usually provided by a semiconductor integrated circuit.
This display drive circuit has a level shift circuit for converting a signal with a low amplitude level of, for example, 3 to 5 V into a signal with a high amplitude level of 20 V or more, and a high level signal for a display based on the output of this level shift circuit. A high voltage output circuit for applying a voltage. In order to shorten the switching time and reduce the current consumption, the constituent elements of the high voltage output circuit are bipolar transistors to MO transistors.
It is changing to an S transistor.

As an example of a document describing a display driving circuit, Nikkei B was published on April 6, 1987.
"Nikkei Electronics (No. 107
Page ~) ".

[0004]

A MOS transistor having a high breakdown voltage structure is applied to the display driving circuit as described above in order to handle a high voltage for driving the display. In the high breakdown voltage structure of the MOS transistor, the gate oxide film is made thick, and further, an offset oxide film is formed between the gate electrode and the drain electrode and between the gate electrode and the source electrode to increase the breakdown voltage. . Since the transconductance of the MOS transistor having such a structure is inevitably low, it is disadvantageous in achieving high-speed switching.

An object of the present invention is to apply a technique for improving the switching speed.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a level shift circuit for converting a signal with a low amplitude level into a signal with a high amplitude level is connected in series with a first element whose gate applied voltage is a high amplitude level, and the first element. When the gate applied voltage is configured to include a second element having a low amplitude level, the thickness of the gate oxide film of the second element is made smaller than the thickness of the gate oxide film of the first element. . A high voltage output circuit for supplying a high voltage to the load based on the output of the level shift circuit is connected in series with the third element in which the gate applied voltage has a high amplitude level, and the third element. When the gate applied voltage is formed to include the fourth element having a low amplitude level, the thickness of the gate oxide film of the fourth element is made thinner than the thickness of the gate oxide film of the third element. .

[0009]

According to the above-mentioned means, making the thickness of the gate oxide film of the second element smaller than the thickness of the gate oxide film of the first element means that the current between the source and drain of the second element is reduced. increase. This increases the load driving capability of the second element and achieves an improvement in the switching speed of the load driving circuit. Further, making the thickness of the gate oxide film of the fourth element smaller than the thickness of the gate oxide film of the third element increases the current between the source and drain of the fourth element, as in the above case. By increasing the load driving capability of the fourth element, the switching speed of the load driving circuit is improved.

[0010]

FIG. 5 shows a display driving circuit according to an embodiment of the present invention. Although not particularly limited, the display driving circuit 50 shown in FIG. 5 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, the display drive circuit 50 is a display drive circuit capable of displaying four floors and includes shift registers 51 to 54, a latch unit 55, a select unit 56, a load drive circuit 57, and a pulse generation unit 58. Consists of The shift register 51
Each of 54 to 54 has a 32-bit structure, and sequentially shifts the input data signal in synchronization with a clock signal supplied from the outside. The output signals of the shift registers 51 to 54 are latched by the latch circuit 55 in the subsequent stage to adjust the data output timing. The pulse generator 58 generates four types of pulse signals having different duty ratios. This pulse signal latch unit 5
5, the output signals of the shift registers 51 to 54 are pulse-width modulated by each pulse width, and the output signals are transmitted to the selection unit 56 at a predetermined timing. Since the data signal is composed of 4 bits, 16 floors can be output. A select unit 56 for selecting the output signal of the latch circuit 55 is provided in the subsequent stage of the latch circuit 55, and the signal selected by the select unit 56 is transmitted to the load drive circuit 57 in the subsequent stage. There is. The discharge time of the display pixel is determined by the selected pulse signal. That is, the discharge time of the pixel is changed to express the floor length. Although not particularly limited, the shift registers 51 to 54, the latch circuit 55, the selection unit 56,
The power supply voltage supplied to the pulse generation circuit 58 is set to 5V.

The load drive circuit 57 is not particularly limited, but the level shift circuit 1 for converting the low amplitude level signal from the select section 56 into a high amplitude level signal.
0, and a high voltage output circuit 57 for applying a high voltage to an external load based on the output of the level shift circuit 10.

FIG. 1 shows a structural example of the load drive circuit 57. The load drive circuit 57 includes the level shift circuit 10
And a high-voltage output circuit 20 arranged in the latter stage of the circuit are coupled to each other, and a MOS transistor is applied as a constituent element. The level shift circuit 10 uses the high voltage power supply Vd.
p-channel MOS transistor M coupled to dh
1 and n-channel type MO coupled to ground GND
Series connection circuit with S-transistor M3 and high voltage power supply V
p-channel type MOS transistor M2 coupled to ddh and n-channel type M coupled to ground GND
Series connection circuit with OS transistor M4 and input signal I
An inverter INV for inverting N.
The MOS transistor M1, M3 connected in series is a MOS
The gate electrode of the transistor M2 is coupled, and the serial connection point of the MOS transistors M2 and M4 is coupled to the gate electrode of the MOS transistor M1. The level of the input signal IN is not particularly limited and is set to 5V. That is, the high level is +5 V with respect to the ground GND, and the low level is the ground GND level. The high voltage power supply Vddh is not particularly limited, but is set to 20 V or higher.

The high voltage output circuit 20 is not particularly limited, but is a p-channel type M coupled to the high voltage power supply Vddh.
The OS transistor M5 and an n-channel MOS transistor M6 coupled to the ground GND are connected in series. This serial connection point is the high voltage output circuit 2
An output node of 0, and a load L such as a display is connected thereto. The gate electrode of the MOS transistor M5 is coupled to the serial connection point of the MOS transistors M1 and M3 and the gate electrode of the MOS transistor M2.
The gate electrode of the MOS transistor M6 is an inverter IN
It is coupled to the output terminal of V and the gate electrode of the MOS transistor M4.

When the input signal IN is at low level, the MOS
The transistor M3 is turned off, and the MOS transistor M
4, M6 is turned on. At this time, the drain electrode of the MOS transistor M4 is set to the low level,
Since the transistor M1 is turned on and the drain electrode of the MOS transistor M3 is set to the high level, the MO
The S transistors M2 and M5 are turned off. Therefore, M
The output signal OUT from the serially connected portion of the OS transistors M5 and M6 is at low level (ground level). On the other hand, when the input signal IN is at high level,
The MOS transistor M3 is turned on and the MOS transistors M4 and M6 are turned off. At this time, since the drain electrode of the MOS transistor M3 is at low level, M
Since the OS transistors M2 and M5 are turned on, and the drain electrode of the MOS transistor M4 is set to the high level, the MOS transistor M1 is turned off. for that reason,
The output signal OUT from the connection point of the MOS transistors M5 and M6 in series is at a high level (high voltage power supply Vddh level). As such, the low amplitude level input signal I
N is converted into a high amplitude level signal, and the high voltage output circuit 20 is controlled based on the converted output.

Here, according to the prior art, this type of semiconductor integrated circuit handles a high voltage for driving a display, so that the level shift circuit 10 and the high voltage output circuit 2 are handled.
A MOS transistor having a high withstand voltage structure is applied to the 0 constituent transistor. That is, the MOS transistor M1
All of M6 had a high breakdown voltage structure, and the gate oxide film was thick. However, paying attention to the MOS transistors M3, M4, and M6 to which a signal of a low amplitude level is input, the MOS transistors M3, M4, and M6 have a gate electrode and a substrate, and a gate electrode and a source electrode. , High electric field is not applied. Therefore, such a MOS
It is not necessary for the transistor to have a high breakdown voltage structure by thickening the gate oxide film unlike the MOS transistors M1, M2, M5 to which a high voltage is applied. That is, MOS
Since a high voltage is applied to the gate electrodes of the transistors M1, M2 and M5, it is necessary to make the gate oxide film thick to have a high breakdown voltage structure. However, the MOS transistors M3, M4 and M6 have a high breakdown voltage structure. Since it is not necessary, the thickness of the gate oxide film can be made thinner than that of the MOS transistors M1, M2 and M5. By thus reducing the thickness of the gate oxide film of each of the MOS transistors M1, M2, M5, the mutual conductance of the MOS transistor can be increased and the current between the source and the drain can be increased. Higher switching speed can be achieved by improving the driving capability. In this way, the MOS transistors M3,
Since the switching speed of M4 is increased, the fall time of the output signal of the level shift circuit 10 can be shortened. Thereby, the rise time of the signal output from the high voltage output circuit 20 can be shortened. Also, MOS
By increasing the switching speed of the transistor M6, the fall time of the signal output from the high voltage output circuit 20 can be shortened.

The MOS transistor forming the inverter INV is not particularly limited, but may have a gate oxide film thickness generally applied in the case of a 5V power source, for example.

The semiconductor integrated circuit having the MOS transistor as described above is realized by performing the gate oxidation step twice. That is, a gate oxide film having a normal breakdown voltage is formed in the first gate oxidation step, and the gate oxide film is selectively thickened in the second gate oxidation step performed thereafter. At this time, the MOS transistors M3, M4,
M6 may be masked so that the gate oxide film is not thickened. By undergoing such a gate oxidation process, the gate oxide film of the MOS transistors M1, M2, M5 is thickened, and the MOS transistors M3, M3
For M4 and M6, the gate oxide film can be thinned.

Further, in this embodiment, the MO is similar to the above.
Since it is not necessary for the S transistors M3, M4 and M6 to have a high breakdown voltage structure, an offset oxide film is formed only between the gate electrode and the drain electrode, and the offset oxide film between the gate electrode and the drain electrode is omitted. can do. That is, when the MOS transistors M1, M2, M5, etc. have a high breakdown voltage structure, as shown in FIG. 3, the drain side of the gate oxide film 34 (diffusion layer 35).
Side) and the source side (diffusion layer 36 side) are made particularly thick to achieve high breakdown voltage. The portion where the gate oxide film is particularly thick is called an offset oxide film and is effective for increasing the breakdown voltage. However, as described above, the MOS transistors M3, M4, M6
With respect to the above, since there is no need for a high breakdown voltage structure, such an offset oxide film can be partially omitted. Specifically, as shown in FIG. 4, the source side (diffusion layer 3
By omitting the offset oxide film on the (6 side), the switching speed is further increased. The offset oxide film 42 on the drain electrode side (diffusion layer 35 side) is formed because a high voltage is applied to the drain electrode.

According to the above embodiment, the following operational effects can be obtained. (1) Regarding the MOS transistors M1, M2, M5, since a high voltage is applied to the gate electrode, it is necessary to make the gate oxide film thick to have a high breakdown voltage structure.
Since the MOS transistors M3, M4, M6 do not need to have a high breakdown voltage structure, the MOS transistors M1, M4
2, the thickness of the gate oxide film can be made thinner than that of M5. By thus reducing the thickness of the gate oxide film, the transconductance of the MOS transistor can be increased and the current between the source and the drain can be increased. Can be realized. As described above, by increasing the switching speed of the MOS transistors M3 and M4, the fall time of the output signal of the level shift circuit 10 can be shortened. As a result, the rise time of the signal output from the high voltage output circuit 20 can be shortened, and due to the faster switching of the MOS transistor M6, the fall time of the signal output from the high voltage output circuit 20 can be reduced. It can be shortened. (2) Since it is not necessary for the MOS transistors M3, M4, M6 to have a high breakdown voltage structure, an offset oxide film is formed only between the gate electrode and the drain electrode, and the offset oxidation film between the gate electrode and the drain electrode is formed. By forming a film and using a one-sided offset structure, it is possible to further improve the speedup of switching. (3) As described above, the MO included in the load drive circuit 57
By making the oxide film of the S-transistor thin or having a one-sided offset structure, the area occupied by the element can be reduced, so that the semiconductor chip size can be reduced.

FIG. 2 shows another configuration example of the load drive circuit 57. The load drive circuit 57 shown in FIG. 2 is different from that shown in FIG. 1 in that p forming a high voltage output circuit is different.
The point is that the gate electrodes of the channel-type MOS transistor M5 and the n-channel-type MOS transistor M6 are commonly connected to the output terminal of the level shift circuit 10. In this case, the gate electrodes of the MOS transistors M5 and M6 are
Since a high voltage is applied, the MOS transistors M5, M
It is necessary to apply a MOS transistor having a high breakdown voltage to both of the above. However, the MOS transistors M3 and M4
For the same reason as in the case of the above embodiment, it is not necessary to have a high breakdown voltage structure. Therefore, by making the gate oxide film thin or using a one-sided offset structure, the same as in the case of the above embodiment. In addition, the switching speed can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the input signal IN is set to 5
Although it is set to V system, 3.3 V system or the like can be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the display drive circuit which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto and the level shift is performed. Can be applied to various semiconductor integrated circuits that require.

The present invention can be applied under the condition that at least a signal with a low amplitude level is converted into a signal with a high amplitude level.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by making the thickness of the gate oxide film of the second element smaller than the thickness of the gate oxide film of the first element, the current between the source and drain of this second element is increased, and as a result, Since the load driving capability of the second element can be increased, the switching speed of the load driving circuit can be improved. Further, by making the thickness of the gate oxide film of the fourth element smaller than the thickness of the gate oxide film of the third element, the current between the source and drain of the fourth element is increased, as in the above case. Since the load driving capability of the fourth element can be increased, the switching speed of the load driving circuit can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a load drive circuit included in a display drive circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of another configuration example of a load drive circuit included in the display drive circuit.

FIG. 3 is a sectional view of a general high breakdown voltage MOS transistor.

FIG. 4 is a cross-sectional view of a MOS transistor applied to the load driving circuit.

FIG. 5 is a block diagram of a configuration example of the display drive circuit.

[Explanation of symbols]

 10 Level Shift Circuit 20 High Voltage Output Circuit 31 Gate Electrode 32 Offset Oxide Film 33 Offset Oxide Film 34 Gate Oxide Film 35 Diffusion Layer 36 Diffusion Layer 50 Display Driver Circuit 51 Shift Register 52 Shift Register 53 Shift Register 54 Shift Register 55 Latch Circuit 56 Select unit 57 Load drive circuit 58 Pulse generator M1 p-channel type MOS transistor M2 p-channel type MOS transistor M3 n-channel type MOS transistor M4 n-channel type MOS transistor M5 p-channel type MOS transistor M6 n-channel type MOS transistor INV inverter L load

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Masumura 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. 5-20-1 Incorporated company Hitachi, Ltd. Semiconductor Division (72) Inventor Teru Chiyokawa 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Ltd.

Claims (3)

[Claims] 1. A level shift circuit for converting a signal of low amplitude level into a signal of high amplitude level, and a high voltage output circuit for applying a high voltage to a load based on the output of the level shift circuit. In the load driving circuit including the above, the level shift circuit includes a first element whose gate applied voltage has a high amplitude level and a second element which is connected in series with the first element and has a gate applied voltage of a low amplitude level. A load drive circuit including an element, wherein the thickness of the gate oxide film of the second element is smaller than the thickness of the gate oxide film of the first element. 2. The high voltage output circuit according to claim 4, wherein a third element whose gate applied voltage has a high amplitude level and a fourth element connected in series with the third element and whose gate applied voltage has a low amplitude level. 2. The load drive circuit according to claim 1, further comprising an element, wherein the thickness of the gate oxide film of the fourth element is smaller than the thickness of the gate oxide film of the third element. 3. The load drive circuit according to claim 1, wherein the second element and the fourth element have a one-sided offset structure in which an offset oxide film is formed only between a gate electrode and a drain electrode. .