JPH07302061A - Display processing method of video and its device - Google Patents

Abstract

PURPOSE:To suppress generation of disturbing fringes without degradation of resolution by increasing the number of gradations with a display panel of a small number of display gradations. CONSTITUTION:The moving parts of a screen are detected by delaying video data by two frames in frame memories 1, 2 and a subtraction section 3. On the other hand, vertical and horizontal synchronizing signals are divided down by 4 in first and second frequency dividing sections 6, 7. The horizontal synchronizing signals are counted by clocks in a horizontal address counter 8. The mask pattern data generated with the outputs of the first and second frequency dividing parts 6, 7 and the output of the horizontal address counter 8 as the addresses of a ROM 5 and the lower two bits of the video data delayed by the two frames are compared in a comparator section 9 to obtain the putting out and light emitting data in the field direction at every one pixel. This data and the upper five bits of the video data delayed by the two frames are latched in a flip-flop circuit 10. A selector 11 is changed over by the differential signal obtd. in the subtraction section 3, by which the parts having no movements and the parts having the movement are separately processed and the output video data is obtd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display processing technique in a display system such as a television, and more particularly, to a display panel having a small number of display gradations (for example, PDP or LCD).
The present invention relates to a video display processing method and apparatus for obtaining a good display video.

[0002]

2. Description of the Related Art For example, a PDP (plasma display panel) is excellent in a large screen among flat displays, and is capable of full-color display and high-speed gradation display. Wall-mounted television) is about to be used.

Generally, about 8 bits are required to display an image of a normal television signal (NTSC signal) or a signal (LD signal, VTR signal, etc.) corresponding thereto on a display panel, that is, when an input image signal is processed as a digital signal. Need a resolution of.

That is, each time the resolution decreases,
This is because the number of display gradations is reduced, and as a result, the resolution is reduced and pseudo contours (those that occur at the boundary of luminance) are generated, which deteriorates the display image.

[0005]

In order to solve the above-mentioned drawbacks, there is a method of increasing the number of display gradations by software processing using, for example, a microcomputer or DSP (digital signal processor), but it is too costly. It becomes expensive.

There is also a mask pattern method that easily realizes the same effect as the above-described method by software processing.
There is a problem that the resolution is lowered. For example, as shown in FIGS. 7 and 8, a mask pattern (for example, a value of 0 to 3) of 2 × 2 pixels (2 pixels in the horizontal direction, 2 pixels in the vertical direction) is preset, and the 2 × 2 pixels are set. One area.

Then, for each area (2 × 2 pixels), the input video data (for example, shown in FIG. 9) and the mask pattern (for example, shown in FIG. 8) are compared, and the value of the input video data (for example, lower 2 bits) is compared. ) Emits light from a pixel larger than the mask pattern, and conversely turns off the pixel from which the input data value is smaller than the mask pattern. Specifically, when the mask pattern has the values shown in FIG. 8 and the input video data has the values shown in FIG. 9, each pixel in the area is in a light emitting state as shown in FIG.

According to the principle of the method of increasing the number of display gradations, not only the resolution of pixels is reduced to ¼, but also interference fringes are generated in a picture portion where the correlation between pixels is large. That is, since gradation display is performed using 2 × 2 pixels as one area, the resolution is ¼ of the original pixel resolution.

Explaining the cause of the interference fringes, since the input image data has the same value as shown in FIG. 11 in the large pattern portion (still portion), each area (2 × 2
When the pixel), the mask pattern data (the repetition of the pattern shown in FIG. 8) and the input video data are compared, the comparison result becomes the same in each area (shown in FIG. 13).

In order to prevent the interference fringes, for example, FIG.
As shown in FIG. 4, there is a method of switching the value of the mask pattern data, that is, a method of changing the data array of the mask pattern. In this case, as shown in the emission state diagram of FIG. 15, the interference fringes are certainly improved as compared with FIG. 13, but the interference fringes cannot be eliminated at all.

The present invention has been made in view of the above problems, and an object thereof is to increase the number of gradations and suppress the generation of interference fringes without lowering the resolution even in a display panel having a small number of display gradations. Accordingly, it is an object of the present invention to provide a video display processing method and an apparatus for the same, which can improve the image quality of the displayed video.

[0012]

In order to achieve the above object, a video display processing method and apparatus of the present invention are
When displaying an image based on the input image data (R, G, B image data) on a display panel having a predetermined number of display gradations, mask pattern data is preset for each pixel in the time axis direction of the screen of the display image. Therefore, the gist is that the mask pattern data is compared with the lower several bits of the video data, and the pixel is turned off and emits light according to the comparison result.

[0013]

According to the above means, the input video data (8 bits) is delayed by 2 frames (4 fields), and the moving portion of the screen is detected by the difference between the input video data and the video data delayed by 2 frames. Meanwhile, the preset mask pattern data (2 bits) is read.

The lower 2 bits of the video data delayed by the above two frames and the mask pattern data are compared with each other, and as a result of this comparison, data for turning off and emitting light of the one pixel is obtained. When the moving part of the screen is not detected, the upper 5 bits of the video data delayed by 2 frames and the 1-bit data of the comparison result are used as the display video data of the display panel, and when the moving part is detected, it is delayed by 2 frames. The upper 6 bits of the video data are directly used as the display video data on the display panel.

Then, only when there is a moving part on the screen,
Light is turned off and emitted in the field direction for each pixel, that is, only 1 bit of display image data (6 bits) is turned off and used as emission data, so that even in a display panel with a small number of display gradations, It is possible to increase the number of gradations and suppress the occurrence of interference fringes without lowering the resolution.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A video display processing method and apparatus according to the present invention include mask pattern data for input video data (R, G, B video data) pixel by pixel in the time axis direction (field direction) of the screen. Focusing on the fact that the setting can suppress the decrease in resolution and the occurrence of interference fringes when the mask pattern data is set within one screen, the mask pattern is set for each pixel in each field direction, and About field (N) to field (N + 3)
For the same pixel, four different mask pattern data are set.

Therefore, the video display processing apparatus of the present invention has the configuration shown in FIG. In FIG. 1, this display processing device receives input image data (R, G, B image data) for displaying an image on a display panel having an effective display gradation number of 64 bits of 6 bits out of 8 bits, for example.
2 delays by 2 frames (4 fields).

The subtraction unit 3 calculates the difference between the video data delayed by the frame memories 1 and 2 and the original signal (input video data), and the calculated difference signal contains a significant signal (moving part of the screen). ) Is detected by the decoder 4, and when there is a difference (when there is a moving part), an H level signal is output, and conversely, when the difference is zero (when there is no moving part), an L level signal is output. If the difference signal contains noise or the like, a noise canceling circuit (coring circuit) may be arranged in front of the decoder 4.

On the other hand, the mask pattern data set in the time axis direction (field direction) of the screen for each pixel is stored in the ROM.
5, the vertical synchronizing signal V is stored in the first frequency divider 6 in order to obtain the 2-bit address of the ROM 5 by the vertical synchronizing signal V of the video data (for example, an NTSC signal in the case of a television). Divided by (V / 2, V / 4),
Further, in order to obtain the 2-bit address of the ROM 5, the horizontal synchronizing signal H of the video signal is divided by the second dividing unit 7 (H /
2, H / 4), and a clock (corresponding to a pixel) between the horizontal synchronizing signals to obtain a 4-bit address of the ROM 5 is counted by the horizontal address counter 8. The first frequency dividing unit 6, the second frequency dividing unit 7 and the horizontal address counter 8 serve as an address generating means of the ROM 5.

The 8-bit address obtained above causes RO
The comparison unit 9 compares the mask pattern data read from M5 with the video data delayed by 2 frames (lower 2 bits), and the 1-bit data of the comparison result and the frame memories 1 and 2 for 2 frames. The delayed data (upper 5 bits) is latched by the D-type flip-flop circuit (FF) 10.

Further, the data delayed by two frames in the frame memories 1 and 2 (upper 6 bits) and the data 6 bits latched in the flip-flop circuit 10 are switched by the selector 11 by the output signal of the decoder 4, The switched data is latched by the D type flip-flop circuit (FF) 12 and used as output video data.

The frame memories 1 and 2, the horizontal address counter 8 and the flip-flop circuits 10 and 11
The clock is used in the circuit for digital signal processing of the video signal for obtaining the input video data.

As the address generating means, 1
Focusing on one pixel, it suffices to generate an address that allows the mask pattern data of the same pixel to be read from the ROM 5 in the field direction, and may be realized by another circuit configuration.

Further, although not shown, the frame memories 1 and 2, the subtracting section 3, the decoder 4, the comparing section 9 and the flip-flop circuits 10 and 12 respectively correspond to R video data, G video data and B video data. Three are provided.

Next, the operation of the video display processing apparatus having the above-mentioned structure will be described in detail with reference to the principle diagram shown in FIG. 2 and the mask pattern schematic diagrams shown in FIGS. R, G, B video data) of the above are input to the device.

Then, the frame memories 1 and 2 sequentially store the video data for each clock and delay by one frame, and the frame memory 2 sequentially store the video data of the frame memory 1 at each clock and delay by one frame. . Therefore, the frame memories 1 and 2 always store the video data for two frames, that is, the video data delayed by two frames are sequentially output to the subtraction unit 3.

The input video data is input to the subtraction unit 3, and the subtraction unit 3 calculates the difference (motion detection information) between the original video data and the video data delayed by two frames. Based on this difference signal, the decoder 4 determines the presence or absence of motion information, that is, when the difference is greater than a certain value, outputs an H level signal and switches the selector 11 to the a side. The difference is zero (value smaller than a certain value)
Is output, the L level signal is output and the selector 11
To the b side.

On the other hand, the vertical synchronizing signal V of the video signal, which is digitally processed to obtain the input video data of the device, is divided into four by the first frequency dividing section 6, and the horizontal synchronizing signal H of the video signal is obtained. The second frequency division unit 7 divides the frequency by 4. The horizontal synchronizing signal is counted by the horizontal address counter 8.

Since the output signals (each 2 bits) of the first and second frequency dividers 6 and 7 and the output signal (4 bits) of the horizontal address counter 8 are input to the ROM 5 as an address, the ROM 5 is masked. The pattern data (for example, shown in FIGS. 3 to 6) are sequentially output.

For example, focusing on the pixel a1 shown in FIG. 2, the mask pattern data read from the ROM 5 is 0 in the field (N), 1 in the field (N + 1), 2 in the field (N + 2) and 2 (N + 3). 3 (shown in FIGS. 3 to 6), and these mask pattern data are repeated every 4 fields.

Focusing on the pixel b1 shown in FIG. 2, the mask pattern data read from the ROM 5 is 1 in the field (N), 2 in the field (N + 1), 3 in the field (N + 2), and 3 in the field (N + 3). 4 (as shown in FIGS. 3 to 6), and these mask pattern data are repeated every 4 fields.

Pixels c1 and d1 shown in FIGS. 2 to 6 below.
The ROM 5 outputs mask pattern data at the timings of the other pixels, and repeatedly outputs the same for every four fields.

Therefore, for example, a1 and a shown in FIG.
Different mask pattern data 0, 1, 2 and 3 are stored in four different addresses of the ROM 5 for the pixels a2, a3 and a4 (pixels in different fields), and the mask pattern data is similarly stored in other pixels. Has been done.

Therefore, the ROM 5 generates different mask pattern data for each field for the same pixel, and repeats the same mask pattern data for every four fields.

The mask pattern data (2 bits) generated in the ROM 5 is input to the comparison unit 9 every clock,
The comparison unit 9 uses the lower 2 bits of the video data delayed by 2 frames.
The bit is compared with the mask pattern data and 1-bit data of the same comparison result is output.

For example, assuming that the lower 2 bits of the video data corresponding to the pixel of a1 shown in FIG. 2 are 1 which is the same value for 4 fields, the mask pattern data generated in the ROM 5 is shown in FIGS. As shown, when 0, 1, 2, 3, the comparison unit 9 uses the same pixel a1, in different fields.
Data (1 bit) of extinguishing and light emission of a2, a3, a4 (shown in FIG. 2) is output. In this case, the field (N)
In the field (N + 1), data to be turned off is obtained as indicated by the diagonal lines in FIG.
In 2) and the field (N + 3), data for emitting light is obtained.

The data (1 bit) resulting from the above comparison and the video data delayed by 2 frames (upper 5 bits) are input to the flip-flop circuit 10, and the flip-flop circuit 10 sets 1 bit to the lower 6 bits. Latch the data as output video data.

As described above, the selector 11 is switched to either the a side or the b side, and, for example, in the part where there is no movement, the flip-flop circuit 10 thereof.
The 6-bit data latched in is latched in the output flip-flop circuit 12.

Therefore, as shown in FIG. 2, one pixel is extinguished and emitted in the time axis direction (field direction) rather than in the screen as in the conventional example, and the lower part of the video data of the non-moving portion is displayed. Whether the 2 bits have the same value or the display panel (the number of gray scales is 64), the number of gray scales is increased, and the interference fringes are not generated without lowering the over-resolution.

It is to be noted that a stationary picture (picture without motion) having a large correlation in the horizontal, vertical and time axis directions of the screen, for example, a screen by an input signal of a personal computer, a teletext signal or an animation signal, has a completely disturbing pattern. However, there is a pattern having a large correlation only in the direction of the time axis, for example, a very effective effect in a still portion of a natural image, and most of the interference fringes can be removed.

In the moving part, the upper 6 bits of the video data delayed by 2 frames are selected by the selector 11.
It is latched in the flip-flop circuit 12 for output via.

As described above, since the mask pattern is set for each pixel in the time axis direction (field direction) of the screen, the number of display gradations is increased and the resolution is reduced, which is a drawback of the conventional example. Since interference fringes can be prevented, image quality can be improved, and no software processing is required, the cost can be reduced.

The above operation simultaneously executes the same processing for R video data, G video data and B video data. Also, for the moving part of the image, the above mask pattern method is not used in consideration of the improvement in the number of display gradations, but the visual characteristics of a person may not be so good compared to the static part. Moreover, there is no basis for increasing the number of display gradations by providing a mask pattern for a moving portion and controlling the light emitting state of a certain pixel.

[0044]

As described above, the present invention provides a video display processing method and apparatus for displaying a display video of input video data (R, G, B) on a display panel having a predetermined number of display gradations. Since the mask pattern is set for each pixel in the time axis direction (field direction) of the input video data, the number of gradations is increased even if the display panel has a small number of display gradations. Further, there is an effect that it is possible to suppress the occurrence of interference fringes without lowering the resolution, and it is possible to improve the image quality of a display image, and it is possible to reduce the cost because no software processing is required.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a video display processing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic principle diagram for explaining an operation of the display processing device shown in FIG.

FIG. 3 is a schematic diagram of mask pattern data for explaining the operation of the display processing apparatus shown in FIG.

FIG. 4 is a schematic diagram of mask pattern data for explaining the operation of the display processing apparatus shown in FIG.

5 is a schematic diagram of mask pattern data for explaining the operation of the display processing apparatus shown in FIG.

FIG. 6 is a schematic diagram of mask pattern data for explaining the operation of the display processing apparatus shown in FIG.

FIG. 7 is a schematic display screen diagram for explaining a conventional image display processing method.

FIG. 8 is a schematic diagram of mask pattern data used in a conventional image display processing method.

FIG. 9 is a schematic diagram of input video data for explaining a conventional video display processing method.

FIG. 10 is a schematic light emission state diagram for explaining a conventional image display processing method.

FIG. 11 is a schematic diagram of input video data for explaining a conventional video display processing method.

FIG. 12 is a schematic diagram of mask pattern data used in a conventional image display processing method.

FIG. 13 is a schematic light emission state diagram for explaining a conventional image display processing method.

FIG. 14 is a schematic diagram of mask pattern data used in a conventional image display processing method.

FIG. 15 is a schematic light emission state diagram for explaining a conventional image display processing method.

[Explanation of symbols]

 1, 2 Frame memory 3 Subtraction unit 4 Decoder 5 ROM 6 First frequency division unit 7 Second frequency division unit 8 Horizontal address counter 9 Comparison unit 10, 12 Flip-flop circuit 11 Selector

Claims (3)

[Claims] 1. When displaying an image based on input image data (R, G, B image data) on a display panel having a predetermined display gradation number, mask pattern data for each pixel in the time axis direction of the screen of the display image. Is set in advance, the mask pattern data is compared with the lower several bits of the video data, and the pixel is turned off and emits light according to the comparison result. 2. When displaying an image based on the input image data (R, G, B image data) on a display panel having a predetermined display gradation number, mask pattern data is preset for each pixel in the field direction of the image. The input video data is delayed by 2 frames to detect a moving part of the screen, and when there is no moving part, the lower several bits of the video data delayed by 2 frames is compared with the mask pattern data. Data for turning off and emitting the pixel is obtained for each field based on the comparison result, and the obtained data is used as a lower bit of video data for displaying a video on the display panel, and the video delayed by the two frames. An image display processing method, wherein the upper several bits of the data are the upper bits of the image data for displaying the image on the display panel. 3. A video display processing apparatus for displaying a video based on input video data (R, G, B video data) on a display panel having a predetermined display gradation number, wherein a mask pattern is provided for each pixel in the field direction of the video. Storage means for storing data in advance, a frame memory for delaying the input video data by 2 frames, the video data delayed by 2 frames for detecting a moving part of the screen, and the input video data Subtracting means for calculating a difference, address generating means for generating an address for reading the mask pattern data of the storage means, mask pattern data read by the generated address and lower order of the video data delayed by two frames. And a comparison means for comparing the data of several bits to obtain data for turning off and emitting light of the one pixel. When there is no moving part, the image data of the display panel is obtained from the upper several bits of the image data delayed by the two frames and the data obtained by the comparing means, and when there is a moving part on the screen, the two frames are delayed. An image display processing device, wherein the image data of the display panel is obtained from the image data.