JPH0729990A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the structure of a MOSFET wherein a gate insulating film can be protected without decreasing the integration degree of a semiconduc tor circuit by forming an opposite conductivity type gate protective region which is brought into direct contact with the semiconductor substrate and by connecting an output wiring onto a drain region, being apart from the gate protective region. CONSTITUTION:In one corner of drain regions 8Dp and 8Dn of a p-channel MOSFETpTr1 and an N-channel MOSFETnTr1 respectively, which constitute a first-stage CMOS inverter CMOS1, an n+ type gate protective region 9n or a p<+> type gate protective region 9p which has a conductivity type opposite to that of the drain region and part of the side face of which is brought into contact with an n-type substrate 1 or a p-type well 2A which is located around the drain region is formed. With diodes (gate protective elements) GPD1 and GPD2, insulation breakdown in a gate oxide film of a second stage CMOS inverter CMOS 2 to which output wirings of the CMOS 1 which are led out from the drain regions 8DP and 8Dn are connected is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MIS having a structure in which an output wiring derived from a drain region of a preceding stage MISFET is connected to a gate electrode of a succeeding stage MISFET and having a gate protection element. Type semiconductor device.

The output wiring derived from the drain region of the MISFET of the previous stage, for example, the MOSFET is the MISSF of the next stage.
ET In a semiconductor device including a structure connected to a gate electrode of a MOSFET, for example, plasma etching when patterning a wiring in the manufacturing process or plasma C when an insulating film is formed on a wiring pattern
In the process of using plasma such as VD, there is a problem that charges generated by the plasma are applied to the gate oxide film via the wiring connected to the gate electrode and the gate electrode, and the gate oxide film is damaged. For this purpose, the output wiring is provided with a gate protection element M
Although an OS type semiconductor device has been proposed, the degree of integration is reduced by providing a gate protection element, and improvement is desired.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional M having a gate protection device.
It is a schematic cross section which shows the principal part of an OS type semiconductor device.

In the figure, Tr1 is the MOSFET in the previous stage,
Tr2 is the next MOSFET, GPD is the gate protection device
(Iode), 51 is an n-type silicon substrate, 52A, 52B, 52C
Is the first, second, and third p-type wells, and 53 is field oxidation
Films, 54A and 54B are gate oxide films, and 55A and 55B are, for example,
56S, first and second gate electrodes made of silicon_A,
56S_BIs the first and second n-type low concentration source regions, 56D_A,
56D_BIs the first and second n-type low-concentration drain regions, and 57 is an acid
Silicon oxide (SiO₂) Sidewall, 58S_A, 58S_BIs the
1st and 2nd n⁺Mold high concentration source area, 58D_A, 58D_BIs
First and second n ⁺-Type high-concentration drain region, 59 is gate protection
Protective element (GPD) p⁺Mold area, 60 is n of GPD⁺Mold area, 61
Is an interlayer insulating film, and 62A, 62B, 62C, 62D, and 62E are contact points.
, 63S is made of aluminum alloy, etc.
Source wiring of MOSFET (Tr1), 63D is also drain
Wiring (output wiring), 64 is for the next stage MOSFET (Tr2)
The drain wiring (output wiring) is shown.

As shown in this figure, in the conventional n-channel type MOS semiconductor device, for example, the MOSF of the preceding stage is used.
Drain region 58D _A of ET (Tr1) and next MOSFET
Forming a third well 52C forming region and separated independent p-type MOSFET (Tr1) (Tr2) in the region corresponding to the lower portion of the middle of the output line 63D which connects the gate electrode 56S _B of (Tr2), the A protective element (GPD) consisting of a diode composed of an n ⁺ type region 60 and ap ⁺ type region 59 including it is formed in the well 52C, and the output wiring 63D is provided with a contact hole 62C in the middle thereof. Through the above protection device (GPD)
(For details, connect to the n ⁺ -type region 60 of GPD) so that the next-stage MOSFET (T
The gate oxide film 54B of r2) was protected.

[0006]

However, in the conventional MOS type semiconductor device thus formed, as described above, it is separated from the formation regions of the MOSFETs (Tr1) (Tr2) and the like, for example, the wells 52A and 52B. Area such as the well
Since the protection device (GPD) is formed in 52C, the area of the region where the protection device (GPD) is separated and the area where the MOSFET is formed are reduced by the area corresponding to the area occupied by the protection device. There is a problem that the degree of integration of the circuit of the semiconductor device in which the circuit configured by the above is integrated is reduced.

Therefore, the present invention is a MOS capable of protecting the gate insulating film without lowering the degree of integration of the semiconductor circuit.
The purpose is to provide a structure of a FET.

[0008]

To solve the above-mentioned problems, a semiconductor device including a structure in which an output wiring derived from one conductivity type drain region of a preceding stage MISFET is connected to a gate electrode of a succeeding stage MISFET, At least a part of the drain region of the preceding MISFET is provided with the MISF.
An opposite conductivity type gate protection region having a higher impurity concentration than the opposite conductivity type semiconductor substrate on which ET is formed and directly contacting the semiconductor substrate is provided, and the output wiring is separated from the gate protection region and the drain is provided. In the semiconductor device according to the present invention connected to a region, or in the above semiconductor device, at least the surface of the drain region of the preceding MISFET is covered with a metal silicide layer separated from the gate protection region, and the metal silicide layer is formed on the metal silicide layer. This is achieved by the semiconductor device according to the present invention to which the output wiring is connected.

[0009]

FIG. 1 is a principle explanatory view showing the principle of the present invention in a structure using an n-channel MOSFET having an LDD structure.

In the figure, Tr1 is the MOSFE of the previous stage.
T and Tr2 are the next stage MOSFET, GPD is the gate protection device
(Diode) 1 is, for example, n-type silicon substrate, 2A, 2B
Is a p-type well, 3 is a field oxide film, and 4A and 4B are gates.
Oxide film, 5A and 5B are gate electrodes, 6S_A, 6S_BIs n-type low concentration
Source area, 6D_A, 6D_BIs an n-type lightly doped drain region, 7
Is SiO₂Sidewall, 8S_A, 8S_BIs n⁺Type high concentration saw
Area, 8D_A, 8D_BIs n ⁺Type high concentration drain region, 9A,
9B is p⁺Type gate protection region, 11 is an interlayer insulating film, 12A to 12
G is the contact hole, 13S is the source wiring of Tr1 (con
Connect to well 2A where Tr1 is formed in tact hole 12E
13D is the drain wiring of Tr1 (the output wiring of the previous stage).
Line), 14S is the source wiring of Tr2 (contact hole 12G)
Well is connected to well 2B where Tr2 is formed), 14D is
The drain wiring of Tr2 (output wiring of the next stage) is shown.

As shown in this figure, the preceding MOSF
In the semiconductor device according to the present invention, which has a circuit configuration in which the output wiring (drain wiring) 13D at the previous stage derived from the drain region of ET (Tr1) is connected to the gate electrode 5B of the MOSFET (Tr2) at the next stage, At least the previous MOSFET
Part of the n ⁺ -type high-concentration drain region 8D _A of (Tr1) has a p-type opposite in conductivity type to the drain region 8D _A.
A p ⁺ -type gate protection region 9A having a higher concentration than the p-type well 2A which is the substrate on which T is formed and which is in direct contact with the p-type well 2A is provided. The impurity concentration of the p ⁺ type gate protection region 9A is the same as that of the region 9A and the n ⁺ type high concentration drain region.
The breakdown voltage of the junction formed between 8D _A is F
It is higher than the operating voltage of ET and the MOSFET (T
The concentration is selected to be a value lower than the breakdown voltage of the gate oxide film 4B of r2).

By doing so, the plasma is accumulated in the wiring 13D during the plasma etching for patterning the wiring 13D connected to the next-stage gate electrode 5B and during the plasma CVD of the insulating film on the wiring pattern 13D. When the charge reaches the breakdown voltage of the junction between the gate protection region 9A and the drain region 13D, the charge is discharged through this junction into the semiconductor substrate in which the FET (Tr1) in the preceding stage is formed, that is, the p-type well 2A, and Stage MOSFET (Tr
The gate oxide film 4B in 2) is prevented from being destroyed.

In the structure of the present invention, as shown,
Since the gate protection region 9A is provided in the high-concentration drain region 8D _A , a special space for forming the gate protection region is not needed, and the degree of integration of semiconductor elements and semiconductor circuits can be improved accordingly. The p-channel MO
Even in a circuit configured using SFET, the same effect can be produced by reversing the conductivity type of the gate protection region.

In another structure of the present invention, as shown in FIG. 4, the drain region 8D except the gate protection region GPD is formed.
_A metal silicide layer is formed on the surface of _A so that it does not contact the gate protection region GPD, and the sheet resistance and contact resistance of the drain region 8D _A are reduced to speed up the FET and at the same time improve gate protection reliability. Planned.

[0015]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. 2A and 2B are explanatory views of an embodiment of the present invention in a semiconductor device having a circuit in which CMOS inverters are connected in two stages. FIG. 2A is a circuit diagram and FIG. 3B is a schematic plan view, and FIG. FIG. 6 is a plan view of a step showing the main part of the manufacturing method. 4A and 4B are explanatory views of another embodiment of the present invention. FIG. 4A is a schematic plan view of an essential part, and FIG. 4B is a schematic sectional view of an essential part. Throughout the drawings, the same object is denoted by the same reference numeral.

In FIG. 2 above, CMOS1 is the first stage CM.
OS inverter, CMOS2 is the second stage CMOS inverter, Vss is the source power supply, GND is the ground power supply, Vin is the signal input terminal, Vout is the signal output terminal, and pTr1 and pTr2 are p-channel MO.
SFET, nTr1 and nTr2 are n-channel MOSFET and GPD
1, GPD11 is a p-type gate protection device (diode), GPD
2, GPD12 is an n-type gate protection device (diode), 1 is an n-type silicon substrate, 2A and 2B are p-type wells, 5A and 5B are gate electrodes, 8S _P and 18S _P are p ⁺ type source regions, 8D _P , 18D
_P is a p ⁺ type drain region, 8S _n and 18S _n are p ⁺ type source regions, 8D _n and 18D _n are n ⁺ type drain regions, 9p and 19p are p ⁺ type gate protection regions, and 9n and 19n are n ⁺ type Gate protection area, 12A to 12M contact holes, 13A pTr1 and nTr1
CMOS1 output wiring consisting of the drain wiring, and 13B is pTr2
And CMOS2 output wiring consisting of nTr2 drain wiring, 13
p ₁ and 13p ₂ indicate Vss wiring, and 13n ₁ and 13n ₂ indicate GND wiring. In addition, GND wiring 13n ₁ and 13n ₂ are contact holes 12D and 12n.
It is also connected to p-type wells 2A and 2B at K, respectively.

In this embodiment, the first stage CMOS
P-channel MOSFET that constitutes an inverter (CMOS1)
(pTr1) and drain region of n-channel MOSFET (nTr1)
In one corner of 8D _P and 8D _n, an n ⁺ type gate protection region 9n or an n ⁺ type gate protection region 9n of the opposite conductivity type to each drain region and at least a part of the side surface is in contact with the n type substrate 1 or p type well 2A around the drain region The p ⁺ type gate protection region 9p is formed, and the drain region is formed by the diodes (gate protection elements) GPD1 and GPD2 which are composed of the gate protection region and the p ⁺ type drain region 8D _P or the n ⁺ type drain region 8D _n. CMOS1 output wiring derived from 8D _P and 8D _n 13
The dielectric breakdown of the gate oxide film (not shown because it is hidden under the gate electrode 5B) of the second-stage CMOS inverter (CMOS2) to which A is connected is prevented.

In this embodiment, the thickness of the gate oxide film is controlled to 80 to 100 Å and the dielectric breakdown voltage is 8
~ 10V. The operating voltage of this circuit is 3.5V. The impurity concentration of the p ⁺ type drain region 8D _P is 1
× 10 ²⁰ cm ^-3 , n ⁺ type drain region 8D _{n has} an impurity concentration of 1
It is controlled to approximately 10 ²⁰ cm ^-3 .

Therefore, in this embodiment, n⁺Type gate guard
The impurity concentration of the protection region 9n is 2 × 10¹⁸cm ^-3Again, p⁺
Type gate protection region 9p, the impurity concentration of 2 × 10¹⁸cm^-3degree
Set to.

As a result, the breakdown voltage of the n-type and p-type gate protection device GPD1 becomes a value of about 5 to 6 V which is between the operating voltage of the circuit and the breakdown voltage of the gate oxide film.

Therefore, in the semiconductor device having the structure of this embodiment, the first stage CMO connected to the gate electrode is formed.
In plasma etching such as plasma etching when patterning the output wiring 13A of the S inverter CMOS1 and plasma CVD such as plasma CVD when forming an insulating film on the wiring pattern, the voltage accumulated in the wiring 13A due to plasma irradiation is the same as that of the GPD1. Below the breakdown voltage of 2
The FET (p that constitutes the second-stage CMOS inverter (CMOS2)
The dielectric breakdown of the gate oxide film below the gate electrode 5B of Tr2 and nTr2) is prevented. Since the breakdown voltage exceeds the operating voltage of the circuit by about 1.5 to 2.5 V, the gate protection element does not break down at the operating voltage and the circuit operation is not hindered.

In this embodiment, the p-channel M which constitutes the CMOS inverter (CMOS1) in the preceding stage as described above.
In the p ⁺ type drain region 8D _{P of the} OSFET (pTr1) and the n ⁺ type drain region 8D _{n of the} n channel MOSFET (nTr1), a p-channel MOSFET (pTr2) and an n-channel MOSFET nTr2)
Gate protection device GP that prevents dielectric breakdown of the gate oxide film of
D1 and GPD2 are formed. Therefore, the provision of the gate protection element does not cause enlargement of the element and deterioration of the degree of integration.

The main part of the semiconductor device of this embodiment is, for example,
According to the manufacturing method shown below with reference to the process plan view of FIG.
It is formed. See FIG. 3 (a). That is, a felt oxide film (not shown) is used as usual.
Then, the impurity concentration for forming a CMOS 10¹⁶cm^-3Degree
Degree p-type well 2A and impurity concentration 10¹⁴cm^-3Degree n ^-Type
For thermal oxidation using a substrate with one exposed recon substrate
A well-exposed well 2A surface and a silicon substrate 1 surface with a thickness of 80 ~
After forming a 100 Å gate oxide film (not shown),
From this well 2A onto the substrate by well known means.
A gate made of, for example, polysilicon that extends over the control substrate 1.
The gate electrode 5A is formed, and then the first mask (not shown) is formed.
N) The n-type drain formation region 10 of the well 2A
In a predetermined area that becomes a part of 8n, p⁺Type gate protection area 9p
Boron for forming¹⁴cm^-2Dose of degree
Ion implantation in a quantity. 109p is boron implantation for gate protection element
Indicates the area.

Next, as shown in FIG. 3B, n ⁺ type gate protection is performed on a predetermined region which is a part of the p type drain formation region 108p of the silicon substrate 1 through the opening of the second mask (not shown). Arsenic for forming the region 9n is ion-implanted with a dose amount of, for example, 10 ¹⁴ cm ^-2 .
109n represents an arsenic implantation region for a gate protection element.

See FIG. 3 (c). Then, through a hole in a third mask (not shown) and a gate.
Gate protection of well 2A using gate electrode 5A as a mask
N is set in a predetermined region except the element boron implantation region 109p. ⁺Type saw
For example, an arsenic for forming a drain / drain region is¹⁵cm^-2degree
Ion implantation with a dose amount of. 8n for source / drain
An arsenic implantation region is shown.

Next, referring to FIG. 3D, through the opening of the fourth mask (not shown) and by using the gate electrode 5A as a mask, a predetermined portion of the silicon substrate 1 except the boron-implanted region 109n for the gate protection element is predetermined. P ^{+ in} the area
Type boron for forming the source / drain regions is, for example, 10 ¹⁶ cm ^-2
Ion implantation is performed at a dose of about the same. Reference numeral 8p indicates a source / drain boron implantation region.

Next, as shown in FIG. 3 (e), heat treatment is performed at a temperature of, for example, about 900 ° C. for a predetermined time to activate the implanted arsenic and the implanted boron. C having a gate protection region of opposite conductivity type to the drain region
A MOSFET can be formed. In this figure, 8D
_n is an n ⁺ type drain region, 8S _n is an n ⁺ type source region, 8D
_p is p ⁺ type drain region, 8S _p is p ⁺ type source region, 9p
Indicates a p ⁺ type gate protection region, and 9n indicates an n ⁺ type gate protection region.

FIG. 4 is a diagram showing another embodiment of the present invention. In this figure, 21 is a p ^- type silicon substrate, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode,
6S _n is an n-type low-concentration source region, 6D _n is an n-type low-concentration drain region, 7 is a SiO ₂ sidewall, 8S _n is an n ⁺ -type high-concentration drain region, 8D _n is an n ⁺ -type high-concentration drain region, 9p Is p
⁺ Type gate protection region, 11 is an interlayer insulating film, 12A and 12B are contact holes, 13S is a source wiring, 13D is a drain wiring (output wiring) connected to the gate electrode of the next stage (not shown), and 15 is a titanium silicide layer. Show.

In this embodiment, the drain region 13 is formed on the entire surface of the source region 8S and the upper part of the gate protection region 9p.
A titanium silicide layer 15 is formed on a region which is not in contact with the gate protection region 9p on D. This titanium silicide layer
In 15, the gate protection region 9p is masked with an insulating film, a titanium layer is deposited, and a heat treatment is performed to form a titanium silicide layer 15 on the exposed surface of the silicon. It is formed by a method of selectively dissolving and removing.

With such a structure, the presence of the low-resistance titanium silicide layer can reduce the sheet resistance and the contact resistance of the source region 8S and the drain region 8D, thereby speeding up the device operation and at the same time, The electric charge accumulated in the gate electrode of the stage is surely discharged, and the reliability of the gate protection effect is improved.

[0031]

As described above, according to the present invention, in a semiconductor device having a structure in which the drain region of the preceding MISFET is connected to the gate electrode of the succeeding MISFET, the element region is enlarged or a dedicated region is provided. Without MI
It is possible to prevent dielectric breakdown of the gate insulating film of the SFET. Therefore, the present invention largely contributes to the improvement of the integration of the semiconductor device.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is an explanatory diagram of an embodiment of the present invention.

FIG. 3 is a process plan view of a manufacturing method according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of another embodiment of the present invention.

FIG. 5 is a schematic sectional view of a main part of a conventional MOS semiconductor device having a gate protection element.

[Explanation of symbols]

Tr1 Previous MOSFET Tr2 Next MOSFET GPD Gate protection device (diode) 1 n type silicon substrate 2A, 2B p type well 3 field oxide film 4A, 4B gate oxide film 5A, 5B gate electrode 6S _A , 6S _B n type low Concentration source region 6D _A , 6D _B n type low concentration drain region 7 SiO ₂ sidewall 8S _A , 8S _B n ⁺ type high concentration source region 8D _A , 8D _B n ⁺ type high concentration drain region 9A, 9B p ⁺ type gate Protective area 11 Interlayer insulation film 12A to 12M Contact hole 13S Tr1 source wiring 13D Tr1 drain wiring (previous stage output wiring) 14S Tr2 source wiring 14D Tr2 drain wiring (next stage output wiring)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (2)

[Claims] 1. A semiconductor device including a structure in which an output wiring derived from one conductivity type drain region of a preceding-stage MISFET is connected to a gate electrode of a next-stage MISFET, wherein at least one of the drain regions of the preceding-stage MISFET is provided. A gate protection region of opposite conductivity type having a higher impurity concentration than the semiconductor substrate of opposite conductivity type in which the MISFET is formed and being in direct contact with the semiconductor substrate, and the output wiring from the gate protection region. A semiconductor device characterized in that it is spaced apart and connected to the drain region. 2. The surface of at least the drain region of the preceding MISFET is covered with a metal silicide layer separated from the gate protection region, and the output wiring is connected on the metal silicide layer. Item 1. The semiconductor device according to item 1.