JPH07295925A - Scsi bus repeater - Google Patents

Abstract

PURPOSE:To secure improved transmission quality without asking whether relayed and transmitted signals are Fast-SCSI or the SCSI of a normal speed and without changing setting at all, to perform coping without the need of a switching operation and to facilitate utilization for everyone. CONSTITUTION:A retiming means 15 provided with a timer circuit 18, a timing control circuit 19 and an output circuit 20 for matching the send-out timing of data synchronizing signals STB in an information transfer phase to an SCSI standard is provided. Then, the output starting timing of the data synchronizing signals STBD sent out from the output circuit 20 is defined as the point of time when the time longer than 55ns and shorter than 70ns elapses for the output timing of data signals and the output ending timing of the data synchronizing signals STBD is defined as the point of time when the reception of the leading edge of the next data synchronizing signals STB is detected or the point of time when more than 90ns elapses after output is started and the data synchronizing signals STB during reception are ended.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is based on SCSI (Scaj = S
SCSI systems such as a local area network (LAN) system using a mall computer system interface bus, and especially an SCS using an optical bus using parallel optical fibers.
The present invention relates to a SCSI bus relay device suitable for widening the I system.

[0002]

2. Description of the Related Art In recent years, the SCSI bus has been widely used as a standard interface. Here, in order to perform communication between devices connected to different types of SCSI buses, a relay device that transmits a signal from one SCSI bus to the other SCSI bus is required. Regarding such a relay device, for example, Japanese Patent Laid-Open No.
There is one disclosed in Japanese Patent Nos. 10150 to 10152. First, Japanese Patent Laid-Open No. 4-10150 discloses that the level of each bus is judged and the signal is transmitted by driving the bus which is not driven. Further, JP-A-4-10151 discloses a method for transmitting a busy signal (BSY signal) which is driven by a plurality of devices while being switched without interruption. However, according to the conventional techniques disclosed in these publications, the signal is transmitted while judging the level of the bus, so that the transmission takes time. Therefore, JP-A-4-10152
According to the publication, an improvement measure is disclosed in which the transfer direction is known from the I / O signal in the information transfer phase, and the data can be transferred at a high speed correspondingly without making a bus level judgment.

The information transfer phase under the SCSI standard will be described below. First, in a SCSI system, S that acquires the right to use the SCSI bus and requests some operation from another SCSI device (target)
The CSI device is called an “initiator”, the SCSI device that executes the operation requested by the initiator is called a “target”, and the SCSI device exists as either an initiator or a target. Peripheral devices can also be initiators, but generally the host computer will be the initiator. The “information transfer phase” is a generic term for each phase of command, data, status, and message, and is classified into in (target → initiator) and out (initiator → target) depending on the transfer direction of information. The target side holds all control rights in the information transfer phase, and information transfer is
It is controlled by a transfer request signal (REQ signal) driven by the target and a response signal (ACK signal) driven by the initiator. One byte of information is transferred by one set of REQ signal and ACK signal.
There are two types of transfer control methods, an asynchronous transfer mode and a synchronous transfer mode, depending on the difference between the signal and response confirmation methods.

Asynchronous transfer mode means REQ signal and AC
This is a method of controlling transfer while mutually confirming the K signal, and can be used in all information transfer phases. First, when the I / O signal is driven (affirmed), the information on the bus is transferred from the target to the initiator. The target drives the REQ signal after the value of the data bus is fixed. The initiator takes the value of the bus data and drives the ACK signal to respond. The target holds the value of the data bus until the ACK signal is driven, and stops driving the REQ signal when the ACK signal is driven. The initiator stops driving the ACK signal after confirming that the driving of the REQ signal is stopped. On the other hand, the I / O signal is not driven (denied)
Sometimes the information on the data bus is transferred from the initiator to the target. The target drives the REQ signal and requests the initiator to transfer information. The initiator drives the ACK signal after sending the requested type of information onto the data bus. The target takes in the data on the data bus and stops driving the REQ signal. The initiator holds the value of the data bus until it detects that the driving of the REQ signal has stopped, and when the driving of the REQ signal stops, the driving of the ACK signal also stops. Target is AC
After detecting that the driving of the K signal has stopped, the process moves to the transfer of the next byte.

The synchronous transfer mode is a transfer method that can be used only in the data phase.
The transfer cycle of the signal and the ACK signal, and the offset number at which the REQ signal can be continuously transmitted without the response of the ACK signal are arranged between the initiator and the target.
This is a high-speed data transfer method that transfers multiple bytes at once.

SCS including such an information transfer phase
Data transfer is performed according to the I convention. And
In order to keep this rule, in the above-mentioned Japanese Patent Application Laid-Open No. 4-10152, different types of S that are not directly connected to each other are used.
In a signal processing device for relaying a CSI bus, a recognizing means for recognizing a predetermined information transfer phase, a deciding means for deciding a transmission direction of a signal to be transmitted, and a recognizing means for recognizing the SCSI bus. Is provided with control means for controlling so as to transfer information at high speed in the direction judged by the judgment means.

By the way, in a bus such as a SCSI bus that transmits a plurality of signals in parallel by a plurality of signal lines, since each signal is transmitted on a different signal line, the propagation time between the transmitted signals is reduced. A difference (so-called skew between signals) occurs, which affects the quality of communication. for that reason,
According to the SCSI standard, the maximum allowable value of the signal-to-signal skew occurring on the bus is specified to be 10 ns (5 ns in Fast-SCSI).

When a plurality of SCSI buses are relayed by a relay device, not only the skew between signals in the bus increases due to the increase in the number of buses, but also the skew generated in the relay device is added. May exceed. Therefore, retiming is necessary to correct the timing relationship between signals when relaying and transferring the signals. However, according to the conventional techniques disclosed in the above-mentioned publications, no countermeasure is taken into consideration regarding the problem of signal skew.

Therefore, by providing the retiming means, the timing relationship between the received signals is guaranteed for all the devices on the plurality of SCSI buses, and the deterioration of the communication quality due to the relay transfer between the plurality of buses is prevented. The SC
An SI bus relay device has been proposed by the applicant. This is because a SCSI bus relay device that relays a transmission signal from one SCSI bus to another SCSI bus is provided with retiming means for retiming and transmitting so as to conform to the SCSI standard when relaying and transmitting the transmission signal. It is a thing. More specifically, the transmission signal to be relayed and transmitted is the REQ signal or the ACK signal in the information transfer phase (the REQ signal when the I / O signal is affirmative, and the ACK signal when the I / O signal is negative).
And the SCSI bus relay device uses the REQ signal or A
When the data signal is relayed and transmitted from the same side as the CK signal in synchronization with the leading edge of the REQ signal or the ACK signal,
The Q signal or the ACK signal is sent to the leading edge of the data signal with S-speed of 25 ns or more at the normal speed in case of Fast-SCSI
In the case of CSI, it is shown that a means for performing relay transmission with a delay of 55 ns or more is provided, and further, a switching means for switching between Fast-SCSI compatible and normal speed SCSI compatible is provided. .

FIG. 9 shows a retiming circuit 1 for the REQ signal and the ACK signal in the information transfer phase according to this proposal.
The schematic configuration of is shown. In the figure, SREQO and SACKO are a REQ signal and an ACK signal sent to the SCSI bus side, respectively. The delay means 2 delays and outputs the input signal (STB signal) by 25 ns or more, and the delay means 3 delays and outputs the input signal (STB signal) by 55 ns or more. When the I / O signal is "1" (affirmative), the output selection unit 4 has SREQO = STB and SACKO = NSTB, and when the I / O signal is "0" (negative), SREQO =
The selection is switched so that NSTB and SACKO = STB. The FST signal is a signal for switching between Fast-SCSI compatible and normal speed SCSI compatible. When the FST signal is "1", a delay time of 25 ns or more for Fast-SCSI compatible is selected. , When the FST signal is “0”, a delay time of 55 ns or more corresponding to normal speed SCSI is selected, and ST is output via the NOT gate 5, AND gates 6 and 7 and OR gate 8, respectively.
It is input to the output selection unit 4 as a BD signal. STB
The leading edge of the signal is at the same timing as the leading edge of the data signal (not shown). Therefore, the leading edge of the REQ signal or the ACK signal is 25 ns or more in the case of Fast-SCSI for the data signal, A normal speed SCSI is delayed by 55 ns or more.

[0011]

However, according to this proposal, the REQ signal or the ACK signal, which is the synchronization signal of the transfer data, depends on the transfer rate of the system (whether the system is Fast-SCSI or not). You have to switch the settings. Here, most users use SCSI without detailed knowledge, and even if they have the knowledge, it is not clear whether the performance can be easily known. Therefore, in the case of the proposed example method, there is a problem in that even if the system does not operate normally due to incorrect settings, it cannot be promptly dealt with. Even if it can be dealt with, it is troublesome to switch the settings one by one.

The REQ signal and the A signal in the synchronous transfer mode are used regardless of whether the signal is a synchronous signal for data or not.
Although it is necessary to guarantee the pulse width of the CK signal, this is not shown in the above-mentioned proposal example. That is,
Regarding the sync signal, in the synchronous transfer mode, not only the timing with the data but also the pulse width of itself must be guaranteed.
As described above, the normal speed SCSI is specified to be 90 ns or more. Although the occurrence of pulse width distortion is unavoidable in the relay transmission, the above-mentioned proposed example does not mention the correspondence in this respect.

From the above, it is desired to provide a SCSI bus relay device which can be easily used by anyone and which is superior in transmission quality.

[0014]

SCSI according to claim 1,
The bus relay device is a SCSI bus relay device that connects a plurality of SCSI buses and a relay transmission line and relays a transmission signal from one SCSI bus to the other SCSI bus, and includes a timer circuit, a timing control circuit, and an output circuit. And retiming means for adapting the transmission timing of a data synchronization signal, which is a transfer request signal or a response signal in the information transfer phase, to the SCSI standard, and the timer circuit sets the output start timing of the data synchronization signal to be transmitted from the output circuit. When the time of 55 ns or more and 70 ns or less has elapsed with respect to the output timing of the data signal due to the timing control by the timing control circuit and the timing control by the timing control circuit, the output end timing of the data synchronization signal transmitted from the output circuit is set as the next data synchronization signal. When the reception of the leading edge of the This is the time when the data synchronization signal being received has ended 90 ns or more after the start of output due to the time counting by the timer circuit and the timing control by the timing control circuit.

The SCSI bus repeater according to claim 2 is
2. The SCSI bus relay device according to claim 1, wherein the output start timing of the data synchronization signals continuously received is
For the first data synchronization signal, the time measured based on the first clock whose frequency accuracy is guaranteed is the time set by the recognition of the second clock whose oscillation start is synchronized with the start of signal reception. With respect to the second and subsequent data synchronization signals, the timing value set and stored based on the recognition of the second clock is the time point measured based on the second clock.

The SCSI bus relay device according to claim 3 is
3. The SCSI bus relay device according to claim 2, wherein when a predetermined time or more has elapsed from the input of the data synchronization signal at a certain point of time and the data synchronization signal is continuing or the next data synchronization signal is not input, the next input is performed. The data synchronization signal is the first data synchronization signal.

The SCSI bus relay device according to claim 4 is
Connecting one or more SCSI buses and relay transmission lines
A SCSI bus relay device for relaying a transmission signal from a CSI bus to another SCSI bus, comprising a timer circuit, a timing control circuit, and an output circuit, and a data synchronization signal among a transfer request signal and a response signal in an information transfer phase. A pulse width distortion correcting means for correcting the pulse width distortion of the other non-data synchronization signal is provided, and the output start timing of the data asynchronous signal sent from the output circuit is measured by the timer circuit and the timing control circuit is controlled by the timing control circuit. Therefore, it is assumed that the time of 30 ns or more and 70 ns or less has elapsed from the time of receiving this data asynchronous signal,
After the output end timing of the data asynchronous signal sent from the output circuit is detected by the reception detection of the leading edge of the next data asynchronous signal or by the time measurement by the timer circuit and the timing control by the timing control circuit, 9
This is the time when the data asynchronous signal being received has ended after the passage of 0 ns or more.

According to a fifth aspect of the SCSI bus relay device of the present invention,
5. The SCSI bus relay device according to claim 4, wherein the output start timing of continuously received data asynchronous signals is timed based on the first clock whose frequency accuracy is guaranteed for the first data asynchronous signal. Is the time set by the recognition of the second clock in which the oscillation start synchronized with the reception start of the signal is guaranteed, and the second and subsequent data asynchronous signals are set and stored based on the recognition of the second clock. The measured timing value is a time point based on the second clock.

According to a sixth aspect of the SCSI bus relay device,
6. The SCSI bus relay device according to claim 5, wherein when a predetermined time or more has elapsed from the input of the data asynchronous signal at a certain time, and the data asynchronous signal is continuing or the next data asynchronous signal is not input, the next input is made. The data asynchronous signal is the first data asynchronous signal.

[0020]

In the SCSI bus repeater according to the first aspect of the present invention, since the transmission timing of the data synchronization signal in the information transfer phase is retimed based on the control by the time management to conform to the SCSI standard, the signal to be relayed and transmitted. Whether it is Fast-SCSI or normal speed SCSI, it can be used without changing the setting and without requiring a switching operation, and the device connected via the relay transmission line can be used. There is no need to pay special attention to the layout, and the flexibility in constructing a SCSI system is dramatically improved.

Here, in order to measure the output start timing for relaying and transmitting the received data synchronization signal, it is necessary to use a clock whose frequency accuracy is guaranteed. Such a clock is synchronized with the reception signal. Therefore, if the timing is to be relayed only with this clock, pulse width distortion may occur in the output signal due to the synchronization mismatch. In a continuous signal, this appears as timing jitter, which causes deterioration of transmission quality.
On the other hand, in order to prevent the occurrence of such jitter,
A clock synchronized with the start of signal reception is required, but such a clock generally has poor frequency accuracy, and thus is not suitable for the above-described timing measurement. In this respect, in the SCSI bus repeater according to claim 2, the output start timing is controlled by using the first clock with guaranteed frequency accuracy and the second clock with guaranteed oscillation start synchronized with the start of signal reception. Therefore, it is possible to prevent the occurrence of jitter while maintaining the accuracy of the output start timing, and for this purpose, it is not necessary to use particularly high-precision elements or designs.
It can be realized with a configuration using a general-purpose inexpensive element.

By the way, when attention is paid to the second clock, the frequency accuracy is poor, and the frequency greatly changes due to, for example, temperature change under a long time condition, and the stored timing value deviates from a predetermined timing. there is a possibility. In this respect, in the SCSI bus relay device according to the third aspect, since the first data synchronization signal is clarified, stable transmission quality can be secured over time, and for this reason, particularly excellent elements and It does not require design and can be realized at low cost.

On the other hand, in the synchronous transfer mode of the information transfer phase, not only retiming but also pulse width distortion correction is necessary for the data sync signal. Such pulse width distortion correction is not a data sync signal but a data asynchronous signal ( A response signal if the I / O signal is affirmative,
It is also necessary for the transfer request signal) when the I / O signal is denied. In this respect, S according to claim 4
In the CSI bus relay device, the SCS according to claim 1.
Since the pulse width distortion correction means similar to the retiming means in the I-bus repeater is provided to guarantee the correction of the pulse width distortion of the data asynchronous signal, high quality communication is ensured in the synchronous transfer mode.

In this case also, the SCSI according to claims 5 and 6
In the bus relay device, further improvement in transmission quality can be realized at low cost.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. First, an outline of a SCSI system to which this embodiment is applied will be described with reference to FIG. The subsystem provided with the SCSI interface and connected to the SCSI bus (common transmission line) exists as either an initiator or a target as described above. Here, in the SCSI system example shown in FIG.
a relay transmission line 12 connecting the a and 11b, and an SCS connecting the SCSI buses 11a and 11b and the relay transmission line 12
It is configured to include the I-bus relay devices 13a and 13b. The relay transmission line 12 is, for example, a SCSI bus 11a, 1
It is configured as a parallel optical bus with two signal lines bidirectionally independent for each signal 1b, specifically, optical fiber signal lines.

Inside the SCSI bus relay devices 13a and 13b, for example, as shown in FIG. 8, a control circuit 14 is provided for each signal line based on the SCSI standard except for the BSY signal, and each control is provided. The circuit 14 monitors the output signals to the SCSI buses 11a and 11b. Accordingly, when there is an output signal to the SCSI buses 11a and 11b, control is performed so that the sneak reception signal is not output to the relay transmission line 12 side, and the full-duplex type relay transmission line 12 is controlled. Signal leakage is prevented.

The relay transmission line 12 in this embodiment is a full-duplex type parallel optical fiber cable (optical bus) in which optical fibers are provided in parallel, and high-quality long-distance transmission is realized. For this reason, the control circuit 14 is provided with an interface corresponding to an optical fiber, but an electrical interface is adopted between the SCSI bus relay devices 13a and 13b and the relay transmission line 12, and an ordinary coaxial cable or the like is used. It goes without saying that the present invention can be applied even when realized.

In this basic system configuration, the present embodiment is based on the SCSI bus relay device 13a or 13
b, the signal transmitted from the relay transmission line 12 to the SCSI bus 11a or 11b, particularly the signal in the information transfer phase, is subjected to retiming processing, and its configuration will be described with reference to FIGS. 1 and 2. To do. Each signal described below is a positive logic (logic “1” at H level) unless otherwise specified.

That is, as schematically shown in FIG. 2, with respect to the data synchronization signal (STB signal) in the information transfer phase, the retiming circuit (retiming means) 15 performs timing correction and pulse width distortion correction so as to conform to the SCSI standard. Then, the signal is sent as an STBD signal to the output selection unit 16 (corresponding to the output selection unit 3 shown in FIG. 9), and R is output from the output selection unit 16 to the SCSI bus 11a or 11b.
SREQO or SACK as EQ signal or ACK signal
O is sent out. Here, as described above, the data synchronization signal in the information transfer phase becomes the transfer request signal (REQ signal) when the I / O signal is affirmed, and when the I / O signal is negated. It becomes a response signal (ACK signal). Therefore, a data asynchronous signal (NSTB signal) that is not a data synchronization signal is
If the I / O signal is positive, the response signal (A
CK signal) and becomes a transfer request signal (REQ signal) when the I / O signal is denied. A pulse width distortion correction circuit (pulse width distortion correction means) 17 is provided for such a data asynchronous signal (NSTB signal), and is sent to the output selection unit 16 as a pulse width distortion corrected NSTBD signal. It is configured.

FIG. 1 shows an example of the configuration of the retiming circuit 15 which is a feature of this embodiment, and is schematically provided with a timer circuit 18, a timing control circuit 19 and an output circuit 20. It is said that. The timer circuit 1
8 is for inputting the STB signal and performing time measurement using the first clock SCLK whose frequency accuracy is guaranteed. The output T6 is 60 ns after the STB signal is input and the output T15 is 150 ns after the STB signal is input. TE>
Output TE at the time when TEns satisfying the condition of 150 ns has elapsed
Are respectively affirmed and output to the output circuit 20. That is, the output T6 manages the elapsed time of 55 ns or more and 70 ns or less, and the output T15 manages the elapsed time of 90 ns or more. Here, the timer circuit 1
All eight of these outputs, once asserted, are said to hold their output state until the circuit is initialized.

The timing control circuit 19 comprises a control circuit 21, an oscillation circuit 22, a counter 23, a memory 24 and a comparison circuit 25. The control circuit 21 controls the STB signal, the first clock SCLK, the second clock CLK described later, and the ST from the output circuit 20.
The BD signal is input, and the output OSCEN is set to be positive when the STB signal is input (the other output CTEN is already positive). This output OSCEN activates the oscillator circuit 22 in the subsequent stage. As soon as the oscillator circuit 22 is activated, the second clock C
It starts to output LK. Therefore, the second clock CLK is a clock guaranteed to start oscillation in synchronization with the start of receiving the STB signal. The counter 23 receives the output CTEN from the control circuit 21 and the second clock CLK, and when the oscillation circuit 22 starts the output of the second clock CLK, it immediately outputs the second clock CLK.
The counting of the clock CLK is started and the counted value is output in parallel as an n-bit counted value CD (n). The memory 24 writes and holds the count value CD (n), and is supplied with the second clock CLK and the STBD signal from the output circuit 20 in order to control the operation thereof. That is, until the output circuit 20 affirms the STBD signal, the memory 24 sequentially overwrites the count value CD (n) each time the second clock CLK is given, and S
When the TBD signal is affirmed, the value is set and held as a timing value. The comparison circuit 25 always compares the value written in the memory 24 with a predetermined timing value C.
Compared with D (n), the output MTCH to the output circuit 20 is affirmed only during the period when both match.

The output circuit 20 outputs the STB signal, the timer circuit 1
8 output T6, T15, TE, second clock CLK
And the output MTCH from the comparison circuit 25 is input, and when the STB signal being received is the first one, when the affirmative of the output T6 is detected by the second clock CLK, the output STBD is affirmed and is being received. When the STB signal of 2 is the second or higher, the output STBD is affirmed when the affirmation of the output MTCH of the comparison circuit 25 is detected by the second clock CLK. This controls the output start timing of the output STBD which is the retimed data synchronization signal. When the output STBD of the output circuit 20 is affirmed, the control circuit 21 receiving this output outputs the output OBD.
Both SCEN and CTEN are denied, and the oscillation operation of the oscillation circuit 22 and the counting operation of the counter 23 are stopped. However, the output CTEN is set so as to automatically return to the positive state when a time sufficient to initialize the counter 23 has elapsed (therefore, as described above, the output OSCEN
Is asserted, this output CTEN has already been asserted). Output OSCEN is the next STB
Not asserted until signal is input.

On the other hand, this output STBD is a. If the next output STBD is input (leading edge of signal received) before output T15 is asserted b. When the output T15 is affirmed and the output STBD ends (becomes “0”), the output ends. This controls the output end timing of the output STBD which is the retimed data synchronization signal.

When the TE signal is affirmed, the next input STB signal is set as the first STB signal, and the oscillation circuit 2
2 switches the detection signal for the output STBD from the output MTCH to the output T6, and the memory 24 makes it possible to write new data again. Also, the timer circuit 18 itself is reset.

FIG. 3 to FIG. 5 are timing charts showing the operation of the retiming circuit 15 of the present embodiment in which the cycle of the STB signal, which is the data synchronization signal, is made different, and the output of the output STBD is started. Timing and output end timing are regulated. In particular,
FIG. 3 shows an example of timing control during continuous reception. Further, FIG. 4 shows an example of the output end timing control in the above case a, and FIG. 5 shows an example of the output end timing control in the above case b.

Further, the oscillation circuit 22 for generating the second clock CLK has an AND gate 2 as shown in FIG. 6, for example.
6 and a plurality of delay elements 27 interposed between its output and input
Composed of and. As a result, the start and end of the oscillation of the oscillator circuit 22 are synchronized with the positive and negative of the output OSCEN, and the oscillation frequency is determined by the delay amount of the gate. The frequency also fluctuates depending on the temperature characteristic of the gate delay amount, but the frequency also becomes constant during the period when the temperature can be regarded as constant. Therefore, as a result, the second clock CLK that starts oscillation at a constant frequency in synchronization with the output OSCEN (that is, the STB signal) is obtained.

Therefore, according to the SCSI system including the SCSI bus relay devices 13a and 13b of the present embodiment, even if the signal relayed by the SCSI bus relay device 13a or 13b is Fast-SCSI, the normal speed is maintained. Even with SCSI, it is possible to deal with the setting without any change and without requiring a switching operation.
As a result, anyone can use it easily and the transmission quality is excellent. Further, it is not necessary to pay attention to the arrangement of devices (initiator or target) connected via the relay transmission line 12, and the degree of freedom in constructing a SCSI system is dramatically improved. Furthermore, since the output start timing of the signal is controlled by using the first clock SCLK with high frequency accuracy and the second clock CLK that is timing-synchronized with the start of signal reception, highly accurate control is possible, and jitter It is possible to prevent the occurrence of.

By the way, the pulse width distortion is corrected by the NS which is the data asynchronous signal which is not the STB signal which is the data synchronizing signal.
Since the TB signal is also required (the SCSI standard value of the pulse width is the same as that of the data synchronization signal), NS is used in this embodiment.
A pulse width distortion correction circuit 17 is provided for the TB signal, but its configuration may be basically the same as that of the retiming circuit 15 shown in FIG. As shown, the NSTB signal may be input instead of the STB signal, and the output NSTBD may be transmitted instead of the output STBD.

Explaining with borrowing this FIG. 1, the output start timing of the data asynchronous signal NSTBD sent from the output circuit 20 is measured from the time when the data asynchronous signal NSTB is received by the timing control by the timer circuit 18 and the timing control by the timing control circuit 19. When the time of 30 ns or more and 70 ns or less has elapsed, here, when the output T6 is positive,
Data asynchronous signal NSTB sent from the output circuit 20
The output end timing of D is set to the next data asynchronous signal NST.
It is controlled so as to be the time when the reception edge of B is detected or 90 ns or more has elapsed since the start of output (output T15 is affirmed) and the data synchronization signal NSTB being received is ended.
Also, regarding the output start timing of the data asynchronous signal continuously received, the first data asynchronous signal NST
For B, the time measured based on the first clock SCLK is set as the time set by the recognition of the second clock CLK, and for the second and subsequent data asynchronous signals NSTB, based on the recognition of the second clock CLK. The timing value CD (n), which is set and stored in the memory 24, may be a time point based on the second clock CLK. further,
When a predetermined time TE or more has elapsed from the input of the data asynchronous signal NSTB at a certain time point and the data asynchronous signal NSTB is continuing or the next data asynchronous signal is not input, the next data asynchronous signal NST is input.
B may be the first data asynchronous signal.

By providing the pulse width distortion correction circuit 17 as described above, the correction of the pulse width distortion can be guaranteed even for the REQ signal or the ACK signal which is the data asynchronous signal NSTB, so that the quality of communication in the synchronous transfer mode is improved. Can be secured.

[0041]

According to the SCSI bus relay apparatus of the invention described in claim 1, a SCSI which relays a transmission signal from one SCSI bus to another SCSI bus by connecting a plurality of SCSI buses and a relay transmission line. In the bus relay device,
The data to be transmitted from the output circuit, which is provided with a timer circuit, a timing control circuit, and an output circuit, is provided with retiming means for adapting the transmission timing of the data synchronization signal which is the transfer request signal or the response signal in the information transfer phase to the SCSI standard. The data synchronization signal to be sent from the output circuit is defined as the output start timing of the synchronization signal, which is a time point of 55 ns or more and 70 ns or less with respect to the output timing of the data signal by the timing of the timer circuit and the timing control of the timing control circuit After the start of output, the output end timing of 9 is detected by the reception detection time of the leading edge of the next data synchronization signal or by the timing of the timer circuit and the timing control of the timing control circuit.
Since it is the time when the data synchronization signal being received has ended after 0 ns or more has passed, whether the relay-transmitted signal is Fast-SCSI or normal-speed SCSI is excellent without changing the setting. The transmission quality can be ensured and the operation can be performed without requiring a switching operation. Anyone can easily use it, and there is no need to pay special attention to the arrangement of devices connected via a relay transmission line. The degree of freedom in system construction can be dramatically improved.

According to the SCSI bus relay apparatus of the second aspect of the invention, in the SCSI bus relay apparatus of the first aspect of the invention, the output start timing of the data synchronization signals continuously received is set to the first data synchronization. For signals, the time measured based on the first clock with guaranteed frequency accuracy is set as the time set by the recognition of the second clock with guaranteed oscillation start synchronized with the start of signal reception. With respect to the data synchronization signal, the first clock and the signal reception with guaranteed frequency accuracy are set by setting the timing value set and stored based on the recognition of the second clock to the time point based on the second clock. Since the output start timing is controlled in combination with the second clock that is guaranteed to start oscillation in synchronization with the start, the accuracy of the output start timing is maintained. Becoming that the generation of jitter can be prevented, Therefore even without requiring a particularly high precision elements and design can be realized in a configuration using an inexpensive device for general purpose.

According to the SCSI bus relay apparatus of the third aspect of the invention, in the SCSI bus relay apparatus of the second aspect of the invention, a predetermined time or more has elapsed from the input of the data synchronization signal at a certain time point, and the data When the sync signal is continuing or the next data sync signal is not input,
By certifying the first data synchronization signal by making the next data synchronization signal the first data synchronization signal, stable transmission quality can be secured over time, and for this reason characteristic fluctuation However, it does not require a particularly excellent element or design and can be realized at low cost.

According to a fourth aspect of the SCSI bus relay apparatus of the present invention, a SCSI bus relay for connecting a plurality of SCSI buses to a relay transmission line and relaying a transmission signal from one SCSI bus to the other SCSI bus. In the device, a pulse width distortion that includes a timer circuit, a timing control circuit, and an output circuit to correct the pulse width distortion of the non-data synchronization signal that is not the data synchronization signal among the transfer request signal and the response signal in the information transfer phase Correcting means is provided, and the output start timing of the data asynchronous signal to be sent from the output circuit is 30 ns or more and 70 ns or less from the time of receiving the data asynchronous signal due to the timing of the timer circuit and the timing control of the timing control circuit. At this point, the output of the data asynchronous signal sent from the output circuit ends. The timing is the time when the reception of the leading edge of the next data asynchronous signal is detected or the time when the data asynchronous signal being received has ended 90 ns or more after the start of output due to the timing by the timer circuit and the timing control by the timing control circuit. , Can guarantee the correction of pulse width distortion for data asynchronous signals that are not data synchronous signals,
High quality communication can be secured in the synchronous transfer mode.

According to the SCSI bus repeater of the invention described in claim 5, in the SCSI bus repeater of the invention described in claim 4, the output start timing of the continuously received data asynchronous signals is set to the first data asynchronous. For the signal, the time measured based on the first clock whose frequency accuracy is guaranteed is set as the time set by the recognition of the second clock whose oscillation start synchronized with the reception start of the signal is guaranteed,
7. The SCSI bus relay device according to claim 6, wherein the second and subsequent data asynchronous signals are set to time points based on the second clock of the timing values set and stored based on the recognition of the second clock. According to the fifth aspect of the present invention, in the SCSI bus relay apparatus according to the fifth aspect, when a predetermined time or more has elapsed from the input of the data asynchronous signal at a certain time point and the data asynchronous signal is continuing or the next data asynchronous signal is not input. Since the data asynchronous signal input next is the first data asynchronous signal, it is possible to further improve the transmission quality at a low cost, as in the case of the SCSI bus relay device according to the present invention. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration.

FIG. 3 is a timing chart showing an operation example thereof.

FIG. 4 is a timing chart showing another operation example.

FIG. 5 is a timing chart showing still another operation example.

FIG. 6 is a logic circuit diagram showing a configuration example of an oscillation circuit.

FIG. 7 is a block diagram showing the basic configuration of an example SCSI system.

FIG. 8 is a block diagram showing the configurations of the SCSI bus relay device and the relay transmission line.

FIG. 9 is a block diagram showing a retiming circuit according to a proposed example.

[Explanation of symbols]

11a, 11b SCSI bus 12 Relay transmission line 15 Retiming means 17 Pulse width distortion correction means 18 Timer circuit 19 Timing control circuit 20 Output circuit STB Data synchronization signal in information transfer phase NSTB Data asynchronous signal in information transfer phase SCLK First clock CLK 2nd clock

Claims (6)

[Claims] 1. A SCSI bus relay device for connecting a plurality of SCSI buses and a relay transmission line and relaying a transmission signal from one SCSI bus to another SCSI bus,
The data to be transmitted from the output circuit, which is provided with a timer circuit, a timing control circuit, and an output circuit, is provided with retiming means for adapting the transmission timing of the data synchronization signal which is the transfer request signal or the response signal in the information transfer phase to the SCSI standard. The data synchronization signal to be sent from the output circuit is defined as the output start timing of the synchronization signal, which is a time point of 55 ns or more and 70 ns or less with respect to the output timing of the data signal due to the timing of the timer circuit and the timing control of the timing control circuit. After the start of output, the output end timing of 9 is detected by the reception detection time of the leading edge of the next data synchronization signal or by the timing of the timer circuit and the timing control of the timing control circuit.
A SCSI bus relay device characterized in that it is a time point when a data synchronization signal being received has ended after 0 ns or more has elapsed. 2. The reception start of the signal, which is the output start timing of the continuously received data synchronization signal, the time measured based on the first clock of which the frequency accuracy is guaranteed for the first data synchronization signal. It is assumed that the time set by the recognition of the second clock for which the oscillation start synchronized with
2. The SCSI bus relay according to claim 1, wherein the second and subsequent data synchronization signals are set to time points based on the second clock of timing values set and stored based on the recognition of the second clock. apparatus. 3. When a predetermined time or more has elapsed from the input of the data synchronization signal at a certain time point, and the data synchronization signal is continuing or the next data synchronization signal is not input, the next data synchronization signal is input. 3. The SCSI according to claim 2, wherein the first data synchronization signal is used.
Bus relay device. 4. A SCSI bus relay device for connecting a plurality of SCSI buses and a relay transmission line to relay a transmission signal from one SCSI bus to another SCSI bus,
A pulse width distortion correction means that includes a timer circuit, a timing control circuit, and an output circuit and corrects the pulse width distortion of the non-data synchronization signal that is not the data synchronization signal among the transfer request signal and the response signal in the information transfer phase. The output start timing of the data asynchronous signal sent from the output circuit is set to a time point of 30 ns or more and 70 ns or less from the reception time point of the data asynchronous signal by the time measurement by the timer circuit and the timing control by the timing control circuit, The output end timing of the data asynchronous signal sent from the output circuit is 90 ns or more after the output is started by the reception detection timing of the leading edge of the next data asynchronous signal or the time measurement by the timer circuit and the timing control by the timing control circuit. When the data asynchronous signal being received ends SCSI bus relay apparatus characterized by the. 5. The reception start timing of the output start timing of the data asynchronous signal continuously received is the time measured based on the first clock whose frequency accuracy is guaranteed for the first data asynchronous signal. It is assumed that the time point set by the recognition of the second clock that is guaranteed to start the oscillation in synchronism with the second data asynchronous signal
5. The SCSI bus relay device according to claim 4, wherein the timing value set and stored based on the recognition of the clock is the time point based on the second clock. 6. When a predetermined time or more has elapsed from the input of the data asynchronous signal at a certain time, and the data asynchronous signal is continuing or the next data asynchronous signal is not input, the data asynchronous signal to be input next is 6. The SCSI bus relay device according to claim 5, wherein the first data asynchronous signal is used.